MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13   Module Name:  x86Cache.c
  14
  15 **/
  16
  17 /**
  18   Invalidates the entire instruction cache in cache coherency domain of the
  19   calling CPU.
  20
  21   Invalidates the entire instruction cache in cache coherency domain of the
  22   calling CPU.
  23
  24 **/
  25 VOID
  26 EFIAPI
  27 InvalidateInstructionCache (
  28   VOID
  29   )
  30 {
  31 }
  32
  33 /**
  34   Invalidates a range of instruction cache lines in the cache coherency domain
  35   of the calling CPU.
  36
  37   Invalidates the instruction cache lines specified by Address and Length. If
  38   Address is not aligned on a cache line boundary, then entire instruction
  39   cache line containing Address is invalidated. If Address + Length is not
  40   aligned on a cache line boundary, then the entire instruction cache line
  41   containing Address + Length -1 is invalidated. This function may choose to
  42   invalidate the entire instruction cache if that is more efficient than
  43   invalidating the specified range. If Length is 0, the no instruction cache
  44   lines are invalidated. Address is returned.
  45
  46   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  47
  48   @param  Address The base address of the instruction cache lines to
  49                   invalidate. If the CPU is in a physical addressing mode, then
  50                   Address is a physical address. If the CPU is in a virtual
  51                   addressing mode, then Address is a virtual address.
  52
  53   @param  Length  The number of bytes to invalidate from the instruction cache.
  54
  55   @return Address
  56
  57 **/
  58 VOID *
  59 EFIAPI
  60 InvalidateInstructionCacheRange (
  61   IN      VOID                      *Address,
  62   IN      UINTN                     Length
  63   )
  64 {
  65   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
  66   return Address;
  67 }
  68
  69 /**
  70   Writes Back and Invalidates the entire data cache in cache coherency domain
  71   of the calling CPU.
  72
  73   Writes Back and Invalidates the entire data cache in cache coherency domain
  74   of the calling CPU. This function guarantees that all dirty cache lines are
  75   written back to system memory, and also invalidates all the data cache lines
  76   in the cache coherency domain of the calling CPU.
  77
  78 **/
  79 VOID
  80 EFIAPI
  81 WriteBackInvalidateDataCache (
  82   VOID
  83   )
  84 {
  85   AsmWbinvd ();
  86 }
  87
  88 /**
  89   Writes Back and Invalidates a range of data cache lines in the cache
  90   coherency domain of the calling CPU.
  91
  92   Writes Back and Invalidate the data cache lines specified by Address and
  93   Length. If Address is not aligned on a cache line boundary, then entire data
  94   cache line containing Address is written back and invalidated. If Address +
  95   Length is not aligned on a cache line boundary, then the entire data cache
  96   line containing Address + Length -1 is written back and invalidated. This
  97   function may choose to write back and invalidate the entire data cache if
  98   that is more efficient than writing back and invalidating the specified
  99   range. If Length is 0, the no data cache lines are written back and
 100   invalidated. Address is returned.
 101
 102   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 103
 104   @param  Address The base address of the data cache lines to write back and
 105                   invalidate. If the CPU is in a physical addressing mode, then
 106                   Address is a physical address. If the CPU is in a virtual
 107                   addressing mode, then Address is a virtual address.
 108   @param  Length  The number of bytes to write back and invalidate from the
 109                   data cache.
 110
 111   @return Address
 112
 113 **/
 114 VOID *
 115 EFIAPI
 116 WriteBackInvalidateDataCacheRange (
 117   IN      VOID                      *Address,
 118   IN      UINTN                     Length
 119   )
 120 {
 121   UINT8                             (*Uint8Ptr)[32];
 122
 123   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 124
 125   Uint8Ptr = Address;
 126   while (Length > sizeof (*Uint8Ptr)) {
 127     AsmFlushCacheLine (Uint8Ptr++);
 128     Length -= sizeof (*Uint8Ptr);
 129   }
 130   if (Length > 0) {
 131     AsmFlushCacheLine (Uint8Ptr);
 132     AsmFlushCacheLine (&(*Uint8Ptr)[Length - 1]);
 133   }
 134   return Address;
 135 }
 136
 137 /**
 138   Writes Back the entire data cache in cache coherency domain of the calling
 139   CPU.
 140
 141   Writes Back the entire data cache in cache coherency domain of the calling
 142   CPU. This function guarantees that all dirty cache lines are written back to
 143   system memory. This function may also invalidate all the data cache lines in
 144   the cache coherency domain of the calling CPU.
 145
 146 **/
 147 VOID
 148 EFIAPI
 149 WriteBackDataCache (
 150   VOID
 151   )
 152 {
 153   WriteBackInvalidateDataCache ();
 154 }
 155
 156 /**
 157   Writes Back a range of data cache lines in the cache coherency domain of the
 158   calling CPU.
 159
 160   Writes Back the data cache lines specified by Address and Length. If Address
 161   is not aligned on a cache line boundary, then entire data cache line
 162   containing Address is written back. If Address + Length is not aligned on a
 163   cache line boundary, then the entire data cache line containing Address +
 164   Length -1 is written back. This function may choose to write back the entire
 165   data cache if that is more efficient than writing back the specified range.
 166   If Length is 0, the no data cache lines are written back. This function may
 167   also invalidate all the data cache lines in the specified range of the cache
 168   coherency domain of the calling CPU. Address is returned.
 169
 170   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 171
 172   @param  Address The base address of the data cache lines to write back. If
 173                   the CPU is in a physical addressing mode, then Address is a
 174                   physical address. If the CPU is in a virtual addressing
 175                   mode, then Address is a virtual address.
 176   @param  Length  The number of bytes to write back from the data cache.
 177
 178   @return Address
 179
 180 **/
 181 VOID *
 182 EFIAPI
 183 WriteBackDataCacheRange (
 184   IN      VOID                      *Address,
 185   IN      UINTN                     Length
 186   )
 187 {
 188   return WriteBackInvalidateDataCacheRange (Address, Length);
 189 }
 190
 191 /**
 192   Invalidates the entire data cache in cache coherency domain of the calling
 193   CPU.
 194
 195   Invalidates the entire data cache in cache coherency domain of the calling
 196   CPU. This function must be used with care because dirty cache lines are not
 197   written back to system memory. It is typically used for cache diagnostics. If
 198   the CPU does not support invalidation of the entire data cache, then a write
 199   back and invalidate operation should be performed on the entire data cache.
 200
 201 **/
 202 VOID
 203 EFIAPI
 204 InvalidateDataCache (
 205   VOID
 206   )
 207 {
 208   AsmInvd ();
 209 }
 210
 211 /**
 212   Invalidates a range of data cache lines in the cache coherency domain of the
 213   calling CPU.
 214
 215   Invalidates the data cache lines specified by Address and Length. If Address
 216   is not aligned on a cache line boundary, then entire data cache line
 217   containing Address is invalidated. If Address + Length is not aligned on a
 218   cache line boundary, then the entire data cache line containing Address +
 219   Length -1 is invalidated. This function must never invalidate any cache lines
 220   outside the specified range. If Length is 0, the no data cache lines are
 221   invalidated. Address is returned. This function must be used with care
 222   because dirty cache lines are not written back to system memory. It is
 223   typically used for cache diagnostics. If the CPU does not support
 224   invalidation of a data cache range, then a write back and invalidate
 225   operation should be performed on the data cache range.
 226
 227   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 228
 229   @param  Address The base address of the data cache lines to invalidate. If
 230                   the CPU is in a physical addressing mode, then Address is a
 231                   physical address. If the CPU is in a virtual addressing mode,
 232                   then Address is a virtual address.
 233   @param  Length  The number of bytes to invalidate from the data cache.
 234
 235   @return Address
 236
 237 **/
 238 VOID *
 239 EFIAPI
 240 InvalidateDataCacheRange (
 241   IN      VOID                      *Address,
 242   IN      UINTN                     Length
 243   )
 244 {
 245   return WriteBackInvalidateDataCacheRange (Address, Length);
 246 }