Fixed a bug in WriteBackInvalidDataCache() that always flush cache lines even when...
[mirror_edk2.git] / MdePkg / Library / BaseCacheMaintenanceLib / x86Cache.c
1 /** @file
2 Cache Maintenance Functions.
3
4 Copyright (c) 2006, Intel Corporation<BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 Module Name: x86Cache.c
14
15 **/
16
17 //
18 // This size must be at or below the smallest cache size possible among all
19 // supported processors
20 //
21 #define CACHE_LINE_SIZE 0x20
22
23 /**
24 Invalidates the entire instruction cache in cache coherency domain of the
25 calling CPU.
26
27 Invalidates the entire instruction cache in cache coherency domain of the
28 calling CPU.
29
30 **/
31 VOID
32 EFIAPI
33 InvalidateInstructionCache (
34 VOID
35 )
36 {
37 }
38
39 /**
40 Invalidates a range of instruction cache lines in the cache coherency domain
41 of the calling CPU.
42
43 Invalidates the instruction cache lines specified by Address and Length. If
44 Address is not aligned on a cache line boundary, then entire instruction
45 cache line containing Address is invalidated. If Address + Length is not
46 aligned on a cache line boundary, then the entire instruction cache line
47 containing Address + Length -1 is invalidated. This function may choose to
48 invalidate the entire instruction cache if that is more efficient than
49 invalidating the specified range. If Length is 0, the no instruction cache
50 lines are invalidated. Address is returned.
51
52 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
53
54 @param Address The base address of the instruction cache lines to
55 invalidate. If the CPU is in a physical addressing mode, then
56 Address is a physical address. If the CPU is in a virtual
57 addressing mode, then Address is a virtual address.
58
59 @param Length The number of bytes to invalidate from the instruction cache.
60
61 @return Address
62
63 **/
64 VOID *
65 EFIAPI
66 InvalidateInstructionCacheRange (
67 IN VOID *Address,
68 IN UINTN Length
69 )
70 {
71 ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
72 return Address;
73 }
74
75 /**
76 Writes Back and Invalidates the entire data cache in cache coherency domain
77 of the calling CPU.
78
79 Writes Back and Invalidates the entire data cache in cache coherency domain
80 of the calling CPU. This function guarantees that all dirty cache lines are
81 written back to system memory, and also invalidates all the data cache lines
82 in the cache coherency domain of the calling CPU.
83
84 **/
85 VOID
86 EFIAPI
87 WriteBackInvalidateDataCache (
88 VOID
89 )
90 {
91 AsmWbinvd ();
92 }
93
94 /**
95 Writes Back and Invalidates a range of data cache lines in the cache
96 coherency domain of the calling CPU.
97
98 Writes Back and Invalidate the data cache lines specified by Address and
99 Length. If Address is not aligned on a cache line boundary, then entire data
100 cache line containing Address is written back and invalidated. If Address +
101 Length is not aligned on a cache line boundary, then the entire data cache
102 line containing Address + Length -1 is written back and invalidated. This
103 function may choose to write back and invalidate the entire data cache if
104 that is more efficient than writing back and invalidating the specified
105 range. If Length is 0, the no data cache lines are written back and
106 invalidated. Address is returned.
107
108 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
109
110 @param Address The base address of the data cache lines to write back and
111 invalidate. If the CPU is in a physical addressing mode, then
112 Address is a physical address. If the CPU is in a virtual
113 addressing mode, then Address is a virtual address.
114 @param Length The number of bytes to write back and invalidate from the
115 data cache.
116
117 @return Address
118
119 **/
120 VOID *
121 EFIAPI
122 WriteBackInvalidateDataCacheRange (
123 IN VOID *Address,
124 IN UINTN Length
125 )
126 {
127 UINTN Start, End;
128
129 ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
130
131 if (Length == 0) {
132 return Address;
133 }
134
135 Start = (UINTN)Address;
136 End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);
137 Start &= ~(CACHE_LINE_SIZE - 1);
138
139 do {
140 Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;
141 } while (Start != End);
142 return Address;
143 }
144
145 /**
146 Writes Back the entire data cache in cache coherency domain of the calling
147 CPU.
148
149 Writes Back the entire data cache in cache coherency domain of the calling
150 CPU. This function guarantees that all dirty cache lines are written back to
151 system memory. This function may also invalidate all the data cache lines in
152 the cache coherency domain of the calling CPU.
153
154 **/
155 VOID
156 EFIAPI
157 WriteBackDataCache (
158 VOID
159 )
160 {
161 WriteBackInvalidateDataCache ();
162 }
163
164 /**
165 Writes Back a range of data cache lines in the cache coherency domain of the
166 calling CPU.
167
168 Writes Back the data cache lines specified by Address and Length. If Address
169 is not aligned on a cache line boundary, then entire data cache line
170 containing Address is written back. If Address + Length is not aligned on a
171 cache line boundary, then the entire data cache line containing Address +
172 Length -1 is written back. This function may choose to write back the entire
173 data cache if that is more efficient than writing back the specified range.
174 If Length is 0, the no data cache lines are written back. This function may
175 also invalidate all the data cache lines in the specified range of the cache
176 coherency domain of the calling CPU. Address is returned.
177
178 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
179
180 @param Address The base address of the data cache lines to write back. If
181 the CPU is in a physical addressing mode, then Address is a
182 physical address. If the CPU is in a virtual addressing
183 mode, then Address is a virtual address.
184 @param Length The number of bytes to write back from the data cache.
185
186 @return Address
187
188 **/
189 VOID *
190 EFIAPI
191 WriteBackDataCacheRange (
192 IN VOID *Address,
193 IN UINTN Length
194 )
195 {
196 return WriteBackInvalidateDataCacheRange (Address, Length);
197 }
198
199 /**
200 Invalidates the entire data cache in cache coherency domain of the calling
201 CPU.
202
203 Invalidates the entire data cache in cache coherency domain of the calling
204 CPU. This function must be used with care because dirty cache lines are not
205 written back to system memory. It is typically used for cache diagnostics. If
206 the CPU does not support invalidation of the entire data cache, then a write
207 back and invalidate operation should be performed on the entire data cache.
208
209 **/
210 VOID
211 EFIAPI
212 InvalidateDataCache (
213 VOID
214 )
215 {
216 AsmInvd ();
217 }
218
219 /**
220 Invalidates a range of data cache lines in the cache coherency domain of the
221 calling CPU.
222
223 Invalidates the data cache lines specified by Address and Length. If Address
224 is not aligned on a cache line boundary, then entire data cache line
225 containing Address is invalidated. If Address + Length is not aligned on a
226 cache line boundary, then the entire data cache line containing Address +
227 Length -1 is invalidated. This function must never invalidate any cache lines
228 outside the specified range. If Length is 0, the no data cache lines are
229 invalidated. Address is returned. This function must be used with care
230 because dirty cache lines are not written back to system memory. It is
231 typically used for cache diagnostics. If the CPU does not support
232 invalidation of a data cache range, then a write back and invalidate
233 operation should be performed on the data cache range.
234
235 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
236
237 @param Address The base address of the data cache lines to invalidate. If
238 the CPU is in a physical addressing mode, then Address is a
239 physical address. If the CPU is in a virtual addressing mode,
240 then Address is a virtual address.
241 @param Length The number of bytes to invalidate from the data cache.
242
243 @return Address
244
245 **/
246 VOID *
247 EFIAPI
248 InvalidateDataCacheRange (
249 IN VOID *Address,
250 IN UINTN Length
251 )
252 {
253 return WriteBackInvalidateDataCacheRange (Address, Length);
254 }