MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14 **/
  15
  16 //
  17 // Include common header file for this module.
  18 //
  19 #include <Base.h>
  20 #include <Library/BaseLib.h>
  21 #include <Library/DebugLib.h>
  22
  23 //
  24 // This size must be at or below the smallest cache size possible among all
  25 // supported processors
  26 //
  27 #define CACHE_LINE_SIZE             0x20
  28
  29 /**
  30   Invalidates the entire instruction cache in cache coherency domain of the
  31   calling CPU.
  32
  33   Invalidates the entire instruction cache in cache coherency domain of the
  34   calling CPU.
  35
  36 **/
  37 VOID
  38 EFIAPI
  39 InvalidateInstructionCache (
  40   VOID
  41   )
  42 {
  43 }
  44
  45 /**
  46   Invalidates a range of instruction cache lines in the cache coherency domain
  47   of the calling CPU.
  48
  49   Invalidates the instruction cache lines specified by Address and Length. If
  50   Address is not aligned on a cache line boundary, then entire instruction
  51   cache line containing Address is invalidated. If Address + Length is not
  52   aligned on a cache line boundary, then the entire instruction cache line
  53   containing Address + Length -1 is invalidated. This function may choose to
  54   invalidate the entire instruction cache if that is more efficient than
  55   invalidating the specified range. If Length is 0, the no instruction cache
  56   lines are invalidated. Address is returned.
  57
  58   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  59
  60   @param  Address The base address of the instruction cache lines to
  61                   invalidate. If the CPU is in a physical addressing mode, then
  62                   Address is a physical address. If the CPU is in a virtual
  63                   addressing mode, then Address is a virtual address.
  64
  65   @param  Length  The number of bytes to invalidate from the instruction cache.
  66
  67   @return Address
  68
  69 **/
  70 VOID *
  71 EFIAPI
  72 InvalidateInstructionCacheRange (
  73   IN      VOID                      *Address,
  74   IN      UINTN                     Length
  75   )
  76 {
  77   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
  78   return Address;
  79 }
  80
  81 /**
  82   Writes Back and Invalidates the entire data cache in cache coherency domain
  83   of the calling CPU.
  84
  85   Writes Back and Invalidates the entire data cache in cache coherency domain
  86   of the calling CPU. This function guarantees that all dirty cache lines are
  87   written back to system memory, and also invalidates all the data cache lines
  88   in the cache coherency domain of the calling CPU.
  89
  90 **/
  91 VOID
  92 EFIAPI
  93 WriteBackInvalidateDataCache (
  94   VOID
  95   )
  96 {
  97   AsmWbinvd ();
  98 }
  99
 100 /**
 101   Writes Back and Invalidates a range of data cache lines in the cache
 102   coherency domain of the calling CPU.
 103
 104   Writes Back and Invalidate the data cache lines specified by Address and
 105   Length. If Address is not aligned on a cache line boundary, then entire data
 106   cache line containing Address is written back and invalidated. If Address +
 107   Length is not aligned on a cache line boundary, then the entire data cache
 108   line containing Address + Length -1 is written back and invalidated. This
 109   function may choose to write back and invalidate the entire data cache if
 110   that is more efficient than writing back and invalidating the specified
 111   range. If Length is 0, the no data cache lines are written back and
 112   invalidated. Address is returned.
 113
 114   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 115
 116   @param  Address The base address of the data cache lines to write back and
 117                   invalidate. If the CPU is in a physical addressing mode, then
 118                   Address is a physical address. If the CPU is in a virtual
 119                   addressing mode, then Address is a virtual address.
 120   @param  Length  The number of bytes to write back and invalidate from the
 121                   data cache.
 122
 123   @return Address
 124
 125 **/
 126 VOID *
 127 EFIAPI
 128 WriteBackInvalidateDataCacheRange (
 129   IN      VOID                      *Address,
 130   IN      UINTN                     Length
 131   )
 132 {
 133   UINTN                             Start, End;
 134
 135   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 136
 137   if (Length == 0) {
 138     return Address;
 139   }
 140
 141   Start = (UINTN)Address;
 142   End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);
 143   Start &= ~(CACHE_LINE_SIZE - 1);
 144
 145   do {
 146     Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;
 147   } while (Start != End);
 148   return Address;
 149 }
 150
 151 /**
 152   Writes Back the entire data cache in cache coherency domain of the calling
 153   CPU.
 154
 155   Writes Back the entire data cache in cache coherency domain of the calling
 156   CPU. This function guarantees that all dirty cache lines are written back to
 157   system memory. This function may also invalidate all the data cache lines in
 158   the cache coherency domain of the calling CPU.
 159
 160 **/
 161 VOID
 162 EFIAPI
 163 WriteBackDataCache (
 164   VOID
 165   )
 166 {
 167   WriteBackInvalidateDataCache ();
 168 }
 169
 170 /**
 171   Writes Back a range of data cache lines in the cache coherency domain of the
 172   calling CPU.
 173
 174   Writes Back the data cache lines specified by Address and Length. If Address
 175   is not aligned on a cache line boundary, then entire data cache line
 176   containing Address is written back. If Address + Length is not aligned on a
 177   cache line boundary, then the entire data cache line containing Address +
 178   Length -1 is written back. This function may choose to write back the entire
 179   data cache if that is more efficient than writing back the specified range.
 180   If Length is 0, the no data cache lines are written back. This function may
 181   also invalidate all the data cache lines in the specified range of the cache
 182   coherency domain of the calling CPU. Address is returned.
 183
 184   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 185
 186   @param  Address The base address of the data cache lines to write back. If
 187                   the CPU is in a physical addressing mode, then Address is a
 188                   physical address. If the CPU is in a virtual addressing
 189                   mode, then Address is a virtual address.
 190   @param  Length  The number of bytes to write back from the data cache.
 191
 192   @return Address
 193
 194 **/
 195 VOID *
 196 EFIAPI
 197 WriteBackDataCacheRange (
 198   IN      VOID                      *Address,
 199   IN      UINTN                     Length
 200   )
 201 {
 202   return WriteBackInvalidateDataCacheRange (Address, Length);
 203 }
 204
 205 /**
 206   Invalidates the entire data cache in cache coherency domain of the calling
 207   CPU.
 208
 209   Invalidates the entire data cache in cache coherency domain of the calling
 210   CPU. This function must be used with care because dirty cache lines are not
 211   written back to system memory. It is typically used for cache diagnostics. If
 212   the CPU does not support invalidation of the entire data cache, then a write
 213   back and invalidate operation should be performed on the entire data cache.
 214
 215 **/
 216 VOID
 217 EFIAPI
 218 InvalidateDataCache (
 219   VOID
 220   )
 221 {
 222   AsmInvd ();
 223 }
 224
 225 /**
 226   Invalidates a range of data cache lines in the cache coherency domain of the
 227   calling CPU.
 228
 229   Invalidates the data cache lines specified by Address and Length. If Address
 230   is not aligned on a cache line boundary, then entire data cache line
 231   containing Address is invalidated. If Address + Length is not aligned on a
 232   cache line boundary, then the entire data cache line containing Address +
 233   Length -1 is invalidated. This function must never invalidate any cache lines
 234   outside the specified range. If Length is 0, the no data cache lines are
 235   invalidated. Address is returned. This function must be used with care
 236   because dirty cache lines are not written back to system memory. It is
 237   typically used for cache diagnostics. If the CPU does not support
 238   invalidation of a data cache range, then a write back and invalidate
 239   operation should be performed on the data cache range.
 240
 241   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 242
 243   @param  Address The base address of the data cache lines to invalidate. If
 244                   the CPU is in a physical addressing mode, then Address is a
 245                   physical address. If the CPU is in a virtual addressing mode,
 246                   then Address is a virtual address.
 247   @param  Length  The number of bytes to invalidate from the data cache.
 248
 249   @return Address
 250
 251 **/
 252 VOID *
 253 EFIAPI
 254 InvalidateDataCacheRange (
 255   IN      VOID                      *Address,
 256   IN      UINTN                     Length
 257   )
 258 {
 259   return WriteBackInvalidateDataCacheRange (Address, Length);
 260 }