MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c

   1 /** @file
   2   AsmFlushCacheLine function
   3
   4   Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9
  10
  11
  12 /**
  13   Flushes a cache line from all the instruction and data caches within the
  14   coherency domain of the CPU.
  15
  16   Flushed the cache line specified by LinearAddress, and returns LinearAddress.
  17   This function is only available on IA-32 and x64.
  18
  19   @param  LinearAddress The address of the cache line to flush. If the CPU is
  20                         in a physical addressing mode, then LinearAddress is a
  21                         physical address. If the CPU is in a virtual
  22                         addressing mode, then LinearAddress is a virtual
  23                         address.
  24
  25   @return LinearAddress
  26 **/
  27 VOID *
  28 EFIAPI
  29 AsmFlushCacheLine (
  30   IN      VOID                      *LinearAddress
  31   )
  32 {
  33   //
  34   // If the CPU does not support CLFLUSH instruction,
  35   // then promote flush range to flush entire cache.
  36   //
  37   _asm {
  38     mov     eax, 1
  39     cpuid
  40     test    edx, BIT19
  41     jz      NoClflush
  42     mov     eax, dword ptr [LinearAddress]
  43     clflush [eax]
  44     jmp     Done
  45 NoClflush:
  46     wbinvd
  47 Done:
  48   }
  49
  50   return LinearAddress;
  51 }
  52