MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c

   1 /** @file
   2   AsmFlushCacheLine function
   3
   4   Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 /**
  10   Flushes a cache line from all the instruction and data caches within the
  11   coherency domain of the CPU.
  12
  13   Flushed the cache line specified by LinearAddress, and returns LinearAddress.
  14   This function is only available on IA-32 and x64.
  15
  16   @param  LinearAddress The address of the cache line to flush. If the CPU is
  17                         in a physical addressing mode, then LinearAddress is a
  18                         physical address. If the CPU is in a virtual
  19                         addressing mode, then LinearAddress is a virtual
  20                         address.
  21
  22   @return LinearAddress
  23 **/
  24 VOID *
  25 EFIAPI
  26 AsmFlushCacheLine (
  27   IN      VOID  *LinearAddress
  28   )
  29 {
  30   //
  31   // If the CPU does not support CLFLUSH instruction,
  32   // then promote flush range to flush entire cache.
  33   //
  34   _asm {
  35     mov     eax, 1
  36     cpuid
  37     test    edx, BIT19
  38     jz      NoClflush
  39     mov     eax, dword ptr [LinearAddress]
  40     clflush [eax]
  41     jmp     Done
  42 NoClflush:
  43     wbinvd
  44 Done:
  45   }
  46
  47   return LinearAddress;
  48 }