4 Copyright (c) 2006, Intel Corporation<BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 // Declare I/O Ports used to perform PCI Confguration Cycles
20 #define PCI_CONFIGURATION_ADDRESS_PORT 0xCF8
21 #define PCI_CONFIGURATION_DATA_PORT 0xCFC
24 // Declare macro to convert PCI Library formatted address to CF8 formatted address
26 // PCI Library formatted address CF8 Formatted Address
27 // ============================= ======================
28 // Bits 00..11 Register Bits 00..07 Register
29 // Bits 12..14 Function Bits 08..10 Function
30 // Bits 15..19 Device Bits 11..15 Device
31 // Bits 20..27 Bus Bits 16..23 Bus
32 // Bits 28..31 Reserved(MBZ) Bits 24..30 Reserved(MBZ)
33 // Bits 31..31 Must be 1
37 Assert the validity of a PCI address. A valid PCI address should contain 1's
38 only in the low 28 bits.
40 @param A The address to validate.
41 @param M Additional bits to assert to be zero.
44 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
45 ASSERT (((A) & (~0xffff0ff | (M))) == 0)
48 Convert a PCI Express address to PCI CF8 address.
50 @param A The address to convert.
52 @retval The coverted address.
55 #define PCI_TO_CF8_ADDRESS(A) \
56 ((UINT32) ((((A) >> 4) & 0xffffff00) | ((A) & 0xfc) | 0x80000000))
61 Reads an 8-bit PCI configuration register.
63 Reads and returns the 8-bit PCI configuration register specified by Address.
64 This function must guarantee that all PCI read and write operations are
67 If Address > 0x0FFFFFFF, then ASSERT().
68 If the register specified by Address >= 0x100, then ASSERT().
70 @param Address Address that encodes the PCI Bus, Device, Function and
73 @return The read value from the PCI configuration register.
82 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
83 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
84 return IoRead8 (PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3));
88 Writes an 8-bit PCI configuration register.
90 Writes the 8-bit PCI configuration register specified by Address with the
91 value specified by Value. Value is returned. This function must guarantee
92 that all PCI read and write operations are serialized.
94 If Address > 0x0FFFFFFF, then ASSERT().
95 If the register specified by Address >= 0x100, then ASSERT().
97 @param Address Address that encodes the PCI Bus, Device, Function and
99 @param Value The value to write.
101 @return The value written to the PCI configuration register.
111 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
112 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
114 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
120 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
123 Reads the 8-bit PCI configuration register specified by Address, performs a
124 bitwise inclusive OR between the read result and the value specified by
125 OrData, and writes the result to the 8-bit PCI configuration register
126 specified by Address. The value written to the PCI configuration register is
127 returned. This function must guarantee that all PCI read and write operations
130 If Address > 0x0FFFFFFF, then ASSERT().
131 If the register specified by Address >= 0x100, then ASSERT().
133 @param Address Address that encodes the PCI Bus, Device, Function and
135 @param OrData The value to OR with the PCI configuration register.
137 @return The value written back to the PCI configuration register.
147 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
148 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
150 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
156 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
159 Reads the 8-bit PCI configuration register specified by Address, performs a
160 bitwise AND between the read result and the value specified by AndData, and
161 writes the result to the 8-bit PCI configuration register specified by
162 Address. The value written to the PCI configuration register is returned.
163 This function must guarantee that all PCI read and write operations are
166 If Address > 0x0FFFFFFF, then ASSERT().
167 If the register specified by Address >= 0x100, then ASSERT().
169 @param Address Address that encodes the PCI Bus, Device, Function and
171 @param AndData The value to AND with the PCI configuration register.
173 @return The value written back to the PCI configuration register.
183 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
184 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
186 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
192 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
193 value, followed a bitwise inclusive OR with another 8-bit value.
195 Reads the 8-bit PCI configuration register specified by Address, performs a
196 bitwise AND between the read result and the value specified by AndData,
197 performs a bitwise inclusive OR between the result of the AND operation and
198 the value specified by OrData, and writes the result to the 8-bit PCI
199 configuration register specified by Address. The value written to the PCI
200 configuration register is returned. This function must guarantee that all PCI
201 read and write operations are serialized.
203 If Address > 0x0FFFFFFF, then ASSERT().
204 If the register specified by Address >= 0x100, then ASSERT().
206 @param Address Address that encodes the PCI Bus, Device, Function and
208 @param AndData The value to AND with the PCI configuration register.
209 @param OrData The value to OR with the result of the AND operation.
211 @return The value written back to the PCI configuration register.
222 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
223 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
224 return IoAndThenOr8 (
225 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
232 Reads a bit field of a PCI configuration register.
234 Reads the bit field in an 8-bit PCI configuration register. The bit field is
235 specified by the StartBit and the EndBit. The value of the bit field is
238 If Address > 0x0FFFFFFF, then ASSERT().
239 If the register specified by Address >= 0x100, then ASSERT().
240 If StartBit is greater than 7, then ASSERT().
241 If EndBit is greater than 7, then ASSERT().
242 If EndBit is less than or equal to StartBit, then ASSERT().
244 @param Address PCI configuration register to read.
245 @param StartBit The ordinal of the least significant bit in the bit field.
247 @param EndBit The ordinal of the most significant bit in the bit field.
250 @return The value of the bit field read from the PCI configuration register.
255 PciCf8BitFieldRead8 (
261 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
262 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
263 return IoBitFieldRead8 (
264 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
271 Writes a bit field to a PCI configuration register.
273 Writes Value to the bit field of the PCI configuration register. The bit
274 field is specified by the StartBit and the EndBit. All other bits in the
275 destination PCI configuration register are preserved. The new value of the
276 8-bit register is returned.
278 If Address > 0x0FFFFFFF, then ASSERT().
279 If the register specified by Address >= 0x100, then ASSERT().
280 If StartBit is greater than 7, then ASSERT().
281 If EndBit is greater than 7, then ASSERT().
282 If EndBit is less than or equal to StartBit, then ASSERT().
284 @param Address PCI configuration register to write.
285 @param StartBit The ordinal of the least significant bit in the bit field.
287 @param EndBit The ordinal of the most significant bit in the bit field.
289 @param Value New value of the bit field.
291 @return The value written back to the PCI configuration register.
296 PciCf8BitFieldWrite8 (
303 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
304 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
305 return IoBitFieldWrite8 (
306 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
314 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
315 writes the result back to the bit field in the 8-bit port.
317 Reads the 8-bit PCI configuration register specified by Address, performs a
318 bitwise inclusive OR between the read result and the value specified by
319 OrData, and writes the result to the 8-bit PCI configuration register
320 specified by Address. The value written to the PCI configuration register is
321 returned. This function must guarantee that all PCI read and write operations
322 are serialized. Extra left bits in OrData are stripped.
324 If Address > 0x0FFFFFFF, then ASSERT().
325 If the register specified by Address >= 0x100, then ASSERT().
326 If StartBit is greater than 7, then ASSERT().
327 If EndBit is greater than 7, then ASSERT().
328 If EndBit is less than or equal to StartBit, then ASSERT().
330 @param Address PCI configuration register to write.
331 @param StartBit The ordinal of the least significant bit in the bit field.
333 @param EndBit The ordinal of the most significant bit in the bit field.
335 @param OrData The value to OR with the PCI configuration register.
337 @return The value written back to the PCI configuration register.
349 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
350 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
351 return IoBitFieldOr8 (
352 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
360 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
361 AND, and writes the result back to the bit field in the 8-bit register.
363 Reads the 8-bit PCI configuration register specified by Address, performs a
364 bitwise AND between the read result and the value specified by AndData, and
365 writes the result to the 8-bit PCI configuration register specified by
366 Address. The value written to the PCI configuration register is returned.
367 This function must guarantee that all PCI read and write operations are
368 serialized. Extra left bits in AndData are stripped.
370 If Address > 0x0FFFFFFF, then ASSERT().
371 If the register specified by Address >= 0x100, then ASSERT().
372 If StartBit is greater than 7, then ASSERT().
373 If EndBit is greater than 7, then ASSERT().
374 If EndBit is less than or equal to StartBit, then ASSERT().
376 @param Address PCI configuration register to write.
377 @param StartBit The ordinal of the least significant bit in the bit field.
379 @param EndBit The ordinal of the most significant bit in the bit field.
381 @param AndData The value to AND with the PCI configuration register.
383 @return The value written back to the PCI configuration register.
395 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
396 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
397 return IoBitFieldAnd8 (
398 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
406 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
407 bitwise inclusive OR, and writes the result back to the bit field in the
410 Reads the 8-bit PCI configuration register specified by Address, performs a
411 bitwise AND followed by a bitwise inclusive OR between the read result and
412 the value specified by AndData, and writes the result to the 8-bit PCI
413 configuration register specified by Address. The value written to the PCI
414 configuration register is returned. This function must guarantee that all PCI
415 read and write operations are serialized. Extra left bits in both AndData and
418 If Address > 0x0FFFFFFF, then ASSERT().
419 If the register specified by Address >= 0x100, then ASSERT().
420 If StartBit is greater than 7, then ASSERT().
421 If EndBit is greater than 7, then ASSERT().
422 If EndBit is less than or equal to StartBit, then ASSERT().
424 @param Address PCI configuration register to write.
425 @param StartBit The ordinal of the least significant bit in the bit field.
427 @param EndBit The ordinal of the most significant bit in the bit field.
429 @param AndData The value to AND with the PCI configuration register.
430 @param OrData The value to OR with the result of the AND operation.
432 @return The value written back to the PCI configuration register.
437 PciCf8BitFieldAndThenOr8(
445 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
446 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
447 return IoBitFieldAndThenOr8 (
448 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
457 Reads a 16-bit PCI configuration register.
459 Reads and returns the 16-bit PCI configuration register specified by Address.
460 This function must guarantee that all PCI read and write operations are
463 If Address > 0x0FFFFFFF, then ASSERT().
464 If Address is not aligned on a 16-bit boundary, then ASSERT().
465 If the register specified by Address >= 0x100, then ASSERT().
467 @param Address Address that encodes the PCI Bus, Device, Function and
470 @return The read value from the PCI configuration register.
479 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
480 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
481 return IoRead16 (PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2));
485 Writes a 16-bit PCI configuration register.
487 Writes the 16-bit PCI configuration register specified by Address with the
488 value specified by Value. Value is returned. This function must guarantee
489 that all PCI read and write operations are serialized.
491 If Address > 0x0FFFFFFF, then ASSERT().
492 If Address is not aligned on a 16-bit boundary, then ASSERT().
493 If the register specified by Address >= 0x100, then ASSERT().
495 @param Address Address that encodes the PCI Bus, Device, Function and
497 @param Value The value to write.
499 @return The value written to the PCI configuration register.
509 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
510 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
512 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
518 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
521 Reads the 16-bit PCI configuration register specified by Address, performs a
522 bitwise inclusive OR between the read result and the value specified by
523 OrData, and writes the result to the 16-bit PCI configuration register
524 specified by Address. The value written to the PCI configuration register is
525 returned. This function must guarantee that all PCI read and write operations
528 If Address > 0x0FFFFFFF, then ASSERT().
529 If Address is not aligned on a 16-bit boundary, then ASSERT().
530 If the register specified by Address >= 0x100, then ASSERT().
532 @param Address Address that encodes the PCI Bus, Device, Function and
534 @param OrData The value to OR with the PCI configuration register.
536 @return The value written back to the PCI configuration register.
546 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
547 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
549 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
555 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
558 Reads the 16-bit PCI configuration register specified by Address, performs a
559 bitwise AND between the read result and the value specified by AndData, and
560 writes the result to the 16-bit PCI configuration register specified by
561 Address. The value written to the PCI configuration register is returned.
562 This function must guarantee that all PCI read and write operations are
565 If Address > 0x0FFFFFFF, then ASSERT().
566 If Address is not aligned on a 16-bit boundary, then ASSERT().
567 If the register specified by Address >= 0x100, then ASSERT().
569 @param Address Address that encodes the PCI Bus, Device, Function and
571 @param AndData The value to AND with the PCI configuration register.
573 @return The value written back to the PCI configuration register.
583 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
584 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
586 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
592 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
593 value, followed a bitwise inclusive OR with another 16-bit value.
595 Reads the 16-bit PCI configuration register specified by Address, performs a
596 bitwise AND between the read result and the value specified by AndData,
597 performs a bitwise inclusive OR between the result of the AND operation and
598 the value specified by OrData, and writes the result to the 16-bit PCI
599 configuration register specified by Address. The value written to the PCI
600 configuration register is returned. This function must guarantee that all PCI
601 read and write operations are serialized.
603 If Address > 0x0FFFFFFF, then ASSERT().
604 If Address is not aligned on a 16-bit boundary, then ASSERT().
605 If the register specified by Address >= 0x100, then ASSERT().
607 @param Address Address that encodes the PCI Bus, Device, Function and
609 @param AndData The value to AND with the PCI configuration register.
610 @param OrData The value to OR with the result of the AND operation.
612 @return The value written back to the PCI configuration register.
623 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
624 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
625 return IoAndThenOr16 (
626 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
633 Reads a bit field of a PCI configuration register.
635 Reads the bit field in a 16-bit PCI configuration register. The bit field is
636 specified by the StartBit and the EndBit. The value of the bit field is
639 If Address > 0x0FFFFFFF, then ASSERT().
640 If Address is not aligned on a 16-bit boundary, then ASSERT().
641 If the register specified by Address >= 0x100, then ASSERT().
642 If StartBit is greater than 15, then ASSERT().
643 If EndBit is greater than 15, then ASSERT().
644 If EndBit is less than or equal to StartBit, then ASSERT().
646 @param Address PCI configuration register to read.
647 @param StartBit The ordinal of the least significant bit in the bit field.
649 @param EndBit The ordinal of the most significant bit in the bit field.
652 @return The value of the bit field read from the PCI configuration register.
657 PciCf8BitFieldRead16 (
663 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
664 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
665 return IoBitFieldRead16 (
666 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
673 Writes a bit field to a PCI configuration register.
675 Writes Value to the bit field of the PCI configuration register. The bit
676 field is specified by the StartBit and the EndBit. All other bits in the
677 destination PCI configuration register are preserved. The new value of the
678 16-bit register is returned.
680 If Address > 0x0FFFFFFF, then ASSERT().
681 If Address is not aligned on a 16-bit boundary, then ASSERT().
682 If the register specified by Address >= 0x100, then ASSERT().
683 If StartBit is greater than 15, then ASSERT().
684 If EndBit is greater than 15, then ASSERT().
685 If EndBit is less than or equal to StartBit, then ASSERT().
687 @param Address PCI configuration register to write.
688 @param StartBit The ordinal of the least significant bit in the bit field.
690 @param EndBit The ordinal of the most significant bit in the bit field.
692 @param Value New value of the bit field.
694 @return The value written back to the PCI configuration register.
699 PciCf8BitFieldWrite16 (
706 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
707 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
708 return IoBitFieldWrite16 (
709 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
717 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
718 writes the result back to the bit field in the 16-bit port.
720 Reads the 16-bit PCI configuration register specified by Address, performs a
721 bitwise inclusive OR between the read result and the value specified by
722 OrData, and writes the result to the 16-bit PCI configuration register
723 specified by Address. The value written to the PCI configuration register is
724 returned. This function must guarantee that all PCI read and write operations
725 are serialized. Extra left bits in OrData are stripped.
727 If Address > 0x0FFFFFFF, then ASSERT().
728 If Address is not aligned on a 16-bit boundary, then ASSERT().
729 If the register specified by Address >= 0x100, then ASSERT().
730 If StartBit is greater than 15, then ASSERT().
731 If EndBit is greater than 15, then ASSERT().
732 If EndBit is less than or equal to StartBit, then ASSERT().
734 @param Address PCI configuration register to write.
735 @param StartBit The ordinal of the least significant bit in the bit field.
737 @param EndBit The ordinal of the most significant bit in the bit field.
739 @param OrData The value to OR with the PCI configuration register.
741 @return The value written back to the PCI configuration register.
753 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
754 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
755 return IoBitFieldOr16 (
756 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
764 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
765 AND, and writes the result back to the bit field in the 16-bit register.
767 Reads the 16-bit PCI configuration register specified by Address, performs a
768 bitwise AND between the read result and the value specified by AndData, and
769 writes the result to the 16-bit PCI configuration register specified by
770 Address. The value written to the PCI configuration register is returned.
771 This function must guarantee that all PCI read and write operations are
772 serialized. Extra left bits in AndData are stripped.
774 If Address > 0x0FFFFFFF, then ASSERT().
775 If Address is not aligned on a 16-bit boundary, then ASSERT().
776 If the register specified by Address >= 0x100, then ASSERT().
777 If StartBit is greater than 15, then ASSERT().
778 If EndBit is greater than 15, then ASSERT().
779 If EndBit is less than or equal to StartBit, then ASSERT().
781 @param Address PCI configuration register to write.
782 @param StartBit The ordinal of the least significant bit in the bit field.
784 @param EndBit The ordinal of the most significant bit in the bit field.
786 @param AndData The value to AND with the PCI configuration register.
788 @return The value written back to the PCI configuration register.
793 PciCf8BitFieldAnd16 (
800 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
801 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
802 return IoBitFieldAnd16 (
803 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
811 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
812 bitwise inclusive OR, and writes the result back to the bit field in the
815 Reads the 16-bit PCI configuration register specified by Address, performs a
816 bitwise AND followed by a bitwise inclusive OR between the read result and
817 the value specified by AndData, and writes the result to the 16-bit PCI
818 configuration register specified by Address. The value written to the PCI
819 configuration register is returned. This function must guarantee that all PCI
820 read and write operations are serialized. Extra left bits in both AndData and
823 If Address > 0x0FFFFFFF, then ASSERT().
824 If Address is not aligned on a 16-bit boundary, then ASSERT().
825 If the register specified by Address >= 0x100, then ASSERT().
826 If StartBit is greater than 15, then ASSERT().
827 If EndBit is greater than 15, then ASSERT().
828 If EndBit is less than or equal to StartBit, then ASSERT().
830 @param Address PCI configuration register to write.
831 @param StartBit The ordinal of the least significant bit in the bit field.
833 @param EndBit The ordinal of the most significant bit in the bit field.
835 @param AndData The value to AND with the PCI configuration register.
836 @param OrData The value to OR with the result of the AND operation.
838 @return The value written back to the PCI configuration register.
843 PciCf8BitFieldAndThenOr16(
851 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
852 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
853 return IoBitFieldAndThenOr16 (
854 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
863 Reads a 32-bit PCI configuration register.
865 Reads and returns the 32-bit PCI configuration register specified by Address.
866 This function must guarantee that all PCI read and write operations are
869 If Address > 0x0FFFFFFF, then ASSERT().
870 If Address is not aligned on a 32-bit boundary, then ASSERT().
871 If the register specified by Address >= 0x100, then ASSERT().
873 @param Address Address that encodes the PCI Bus, Device, Function and
876 @return The read value from the PCI configuration register.
885 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
886 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
887 return IoRead32 (PCI_CONFIGURATION_DATA_PORT
);
891 Writes a 32-bit PCI configuration register.
893 Writes the 32-bit PCI configuration register specified by Address with the
894 value specified by Value. Value is returned. This function must guarantee
895 that all PCI read and write operations are serialized.
897 If Address > 0x0FFFFFFF, then ASSERT().
898 If Address is not aligned on a 32-bit boundary, then ASSERT().
899 If the register specified by Address >= 0x100, then ASSERT().
901 @param Address Address that encodes the PCI Bus, Device, Function and
903 @param Value The value to write.
905 @return The value written to the PCI configuration register.
915 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
916 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
918 PCI_CONFIGURATION_DATA_PORT
,
924 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
927 Reads the 32-bit PCI configuration register specified by Address, performs a
928 bitwise inclusive OR between the read result and the value specified by
929 OrData, and writes the result to the 32-bit PCI configuration register
930 specified by Address. The value written to the PCI configuration register is
931 returned. This function must guarantee that all PCI read and write operations
934 If Address > 0x0FFFFFFF, then ASSERT().
935 If Address is not aligned on a 32-bit boundary, then ASSERT().
936 If the register specified by Address >= 0x100, then ASSERT().
938 @param Address Address that encodes the PCI Bus, Device, Function and
940 @param OrData The value to OR with the PCI configuration register.
942 @return The value written back to the PCI configuration register.
952 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
953 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
955 PCI_CONFIGURATION_DATA_PORT
,
961 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
964 Reads the 32-bit PCI configuration register specified by Address, performs a
965 bitwise AND between the read result and the value specified by AndData, and
966 writes the result to the 32-bit PCI configuration register specified by
967 Address. The value written to the PCI configuration register is returned.
968 This function must guarantee that all PCI read and write operations are
971 If Address > 0x0FFFFFFF, then ASSERT().
972 If Address is not aligned on a 32-bit boundary, then ASSERT().
973 If the register specified by Address >= 0x100, then ASSERT().
975 @param Address Address that encodes the PCI Bus, Device, Function and
977 @param AndData The value to AND with the PCI configuration register.
979 @return The value written back to the PCI configuration register.
989 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
990 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
992 PCI_CONFIGURATION_DATA_PORT
,
998 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
999 value, followed a bitwise inclusive OR with another 32-bit value.
1001 Reads the 32-bit PCI configuration register specified by Address, performs a
1002 bitwise AND between the read result and the value specified by AndData,
1003 performs a bitwise inclusive OR between the result of the AND operation and
1004 the value specified by OrData, and writes the result to the 32-bit PCI
1005 configuration register specified by Address. The value written to the PCI
1006 configuration register is returned. This function must guarantee that all PCI
1007 read and write operations are serialized.
1009 If Address > 0x0FFFFFFF, then ASSERT().
1010 If Address is not aligned on a 32-bit boundary, then ASSERT().
1011 If the register specified by Address >= 0x100, then ASSERT().
1013 @param Address Address that encodes the PCI Bus, Device, Function and
1015 @param AndData The value to AND with the PCI configuration register.
1016 @param OrData The value to OR with the result of the AND operation.
1018 @return The value written back to the PCI configuration register.
1029 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
1030 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
1031 return IoAndThenOr32 (
1032 PCI_CONFIGURATION_DATA_PORT
,
1039 Reads a bit field of a PCI configuration register.
1041 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1042 specified by the StartBit and the EndBit. The value of the bit field is
1045 If Address > 0x0FFFFFFF, then ASSERT().
1046 If Address is not aligned on a 32-bit boundary, then ASSERT().
1047 If the register specified by Address >= 0x100, then ASSERT().
1048 If StartBit is greater than 31, then ASSERT().
1049 If EndBit is greater than 31, then ASSERT().
1050 If EndBit is less than or equal to StartBit, then ASSERT().
1052 @param Address PCI configuration register to read.
1053 @param StartBit The ordinal of the least significant bit in the bit field.
1055 @param EndBit The ordinal of the most significant bit in the bit field.
1058 @return The value of the bit field read from the PCI configuration register.
1063 PciCf8BitFieldRead32 (
1069 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
1070 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
1071 return IoBitFieldRead32 (
1072 PCI_CONFIGURATION_DATA_PORT
,
1079 Writes a bit field to a PCI configuration register.
1081 Writes Value to the bit field of the PCI configuration register. The bit
1082 field is specified by the StartBit and the EndBit. All other bits in the
1083 destination PCI configuration register are preserved. The new value of the
1084 32-bit register is returned.
1086 If Address > 0x0FFFFFFF, then ASSERT().
1087 If Address is not aligned on a 32-bit boundary, then ASSERT().
1088 If the register specified by Address >= 0x100, then ASSERT().
1089 If StartBit is greater than 31, then ASSERT().
1090 If EndBit is greater than 31, then ASSERT().
1091 If EndBit is less than or equal to StartBit, then ASSERT().
1093 @param Address PCI configuration register to write.
1094 @param StartBit The ordinal of the least significant bit in the bit field.
1096 @param EndBit The ordinal of the most significant bit in the bit field.
1098 @param Value New value of the bit field.
1100 @return The value written back to the PCI configuration register.
1105 PciCf8BitFieldWrite32 (
1112 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
1113 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
1114 return IoBitFieldWrite32 (
1115 PCI_CONFIGURATION_DATA_PORT
,
1123 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1124 writes the result back to the bit field in the 32-bit port.
1126 Reads the 32-bit PCI configuration register specified by Address, performs a
1127 bitwise inclusive OR between the read result and the value specified by
1128 OrData, and writes the result to the 32-bit PCI configuration register
1129 specified by Address. The value written to the PCI configuration register is
1130 returned. This function must guarantee that all PCI read and write operations
1131 are serialized. Extra left bits in OrData are stripped.
1133 If Address > 0x0FFFFFFF, then ASSERT().
1134 If Address is not aligned on a 32-bit boundary, then ASSERT().
1135 If the register specified by Address >= 0x100, then ASSERT().
1136 If StartBit is greater than 31, then ASSERT().
1137 If EndBit is greater than 31, then ASSERT().
1138 If EndBit is less than or equal to StartBit, then ASSERT().
1140 @param Address PCI configuration register to write.
1141 @param StartBit The ordinal of the least significant bit in the bit field.
1143 @param EndBit The ordinal of the most significant bit in the bit field.
1145 @param OrData The value to OR with the PCI configuration register.
1147 @return The value written back to the PCI configuration register.
1152 PciCf8BitFieldOr32 (
1159 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
1160 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
1161 return IoBitFieldOr32 (
1162 PCI_CONFIGURATION_DATA_PORT
,
1170 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1171 AND, and writes the result back to the bit field in the 32-bit register.
1173 Reads the 32-bit PCI configuration register specified by Address, performs a
1174 bitwise AND between the read result and the value specified by AndData, and
1175 writes the result to the 32-bit PCI configuration register specified by
1176 Address. The value written to the PCI configuration register is returned.
1177 This function must guarantee that all PCI read and write operations are
1178 serialized. Extra left bits in AndData are stripped.
1180 If Address > 0x0FFFFFFF, then ASSERT().
1181 If Address is not aligned on a 32-bit boundary, then ASSERT().
1182 If the register specified by Address >= 0x100, then ASSERT().
1183 If StartBit is greater than 31, then ASSERT().
1184 If EndBit is greater than 31, then ASSERT().
1185 If EndBit is less than or equal to StartBit, then ASSERT().
1187 @param Address PCI configuration register to write.
1188 @param StartBit The ordinal of the least significant bit in the bit field.
1190 @param EndBit The ordinal of the most significant bit in the bit field.
1192 @param AndData The value to AND with the PCI configuration register.
1194 @return The value written back to the PCI configuration register.
1199 PciCf8BitFieldAnd32 (
1206 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
1207 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
1208 return IoBitFieldAnd32 (
1209 PCI_CONFIGURATION_DATA_PORT
,
1217 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1218 bitwise inclusive OR, and writes the result back to the bit field in the
1221 Reads the 32-bit PCI configuration register specified by Address, performs a
1222 bitwise AND followed by a bitwise inclusive OR between the read result and
1223 the value specified by AndData, and writes the result to the 32-bit PCI
1224 configuration register specified by Address. The value written to the PCI
1225 configuration register is returned. This function must guarantee that all PCI
1226 read and write operations are serialized. Extra left bits in both AndData and
1227 OrData are stripped.
1229 If Address > 0x0FFFFFFF, then ASSERT().
1230 If Address is not aligned on a 32-bit boundary, then ASSERT().
1231 If the register specified by Address >= 0x100, then ASSERT().
1232 If StartBit is greater than 31, then ASSERT().
1233 If EndBit is greater than 31, then ASSERT().
1234 If EndBit is less than or equal to StartBit, then ASSERT().
1236 @param Address PCI configuration register to write.
1237 @param StartBit The ordinal of the least significant bit in the bit field.
1239 @param EndBit The ordinal of the most significant bit in the bit field.
1241 @param AndData The value to AND with the PCI configuration register.
1242 @param OrData The value to OR with the result of the AND operation.
1244 @return The value written back to the PCI configuration register.
1249 PciCf8BitFieldAndThenOr32(
1257 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
1258 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
1259 return IoBitFieldAndThenOr32 (
1260 PCI_CONFIGURATION_DATA_PORT
,
1269 Reads a range of PCI configuration registers into a caller supplied buffer.
1271 Reads the range of PCI configuration registers specified by StartAddress and
1272 Size into the buffer specified by Buffer. This function only allows the PCI
1273 configuration registers from a single PCI function to be read. Size is
1274 returned. When possible 32-bit PCI configuration read cycles are used to read
1275 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1276 and 16-bit PCI configuration read cycles may be used at the beginning and the
1279 If StartAddress > 0x0FFFFFFF, then ASSERT().
1280 If the register specified by StartAddress >= 0x100, then ASSERT().
1281 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1282 If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().
1283 If Buffer is NULL, then ASSERT().
1285 @param StartAddress Starting address that encodes the PCI Bus, Device,
1286 Function and Register.
1287 @param Size Size in bytes of the transfer.
1288 @param Buffer Pointer to a buffer receiving the data read.
1296 IN UINTN StartAddress
,
1303 EndAddress
= StartAddress
+ Size
;
1305 if (StartAddress
< EndAddress
&& (StartAddress
& 1)) {
1307 // Read a byte if StartAddress is byte aligned
1309 *(UINT8
*)Buffer
= PciCf8Read8 (StartAddress
);
1310 StartAddress
+= sizeof (UINT8
);
1311 Buffer
= (UINT8
*)Buffer
+ 1;
1314 if (StartAddress
< EndAddress
&& (StartAddress
& 2)) {
1316 // Read a word if StartAddress is word aligned
1318 *(UINT16
*)Buffer
= PciCf8Read16 (StartAddress
);
1319 StartAddress
+= sizeof (UINT16
);
1320 Buffer
= (UINT16
*)Buffer
+ 1;
1323 while (EndAddress
- StartAddress
>= 4) {
1325 // Read as many double words as possible
1327 *(UINT32
*)Buffer
= PciCf8Read32 (StartAddress
);
1328 StartAddress
+= sizeof (UINT32
);
1329 Buffer
= (UINT32
*)Buffer
+ 1;
1332 if ((EndAddress
& 2) != 0) {
1334 // Read the last remaining word if exist
1336 *(UINT16
*)Buffer
= PciCf8Read16 (StartAddress
);
1337 StartAddress
+= sizeof (UINT16
);
1338 Buffer
= (UINT16
*)Buffer
+ 1;
1341 if (EndAddress
& 1) {
1343 // Read the last remaining byte if exist
1345 *(UINT8
*)Buffer
= PciCf8Read8 (StartAddress
);
1352 Copies the data in a caller supplied buffer to a specified range of PCI
1353 configuration space.
1355 Writes the range of PCI configuration registers specified by StartAddress and
1356 Size from the buffer specified by Buffer. This function only allows the PCI
1357 configuration registers from a single PCI function to be written. Size is
1358 returned. When possible 32-bit PCI configuration write cycles are used to
1359 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1360 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1361 and the end of the range.
1363 If StartAddress > 0x0FFFFFFF, then ASSERT().
1364 If the register specified by StartAddress >= 0x100, then ASSERT().
1365 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1366 If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().
1367 If Buffer is NULL, then ASSERT().
1369 @param StartAddress Starting address that encodes the PCI Bus, Device,
1370 Function and Register.
1371 @param Size Size in bytes of the transfer.
1372 @param Buffer Pointer to a buffer containing the data to write.
1380 IN UINTN StartAddress
,
1387 EndAddress
= StartAddress
+ Size
;
1389 if ((StartAddress
< EndAddress
) && ((StartAddress
& 1)!= 0)) {
1391 // Write a byte if StartAddress is byte aligned
1393 PciCf8Write8 (StartAddress
, *(UINT8
*)Buffer
);
1394 StartAddress
+= sizeof (UINT8
);
1395 Buffer
= (UINT8
*)Buffer
+ 1;
1398 if (StartAddress
< EndAddress
&& (StartAddress
& 2)) {
1400 // Write a word if StartAddress is word aligned
1402 PciCf8Write16 (StartAddress
, *(UINT16
*)Buffer
);
1403 StartAddress
+= sizeof (UINT16
);
1404 Buffer
= (UINT16
*)Buffer
+ 1;
1407 while (EndAddress
- StartAddress
>= 4) {
1409 // Write as many double words as possible
1411 PciCf8Write32 (StartAddress
, *(UINT32
*)Buffer
);
1412 StartAddress
+= sizeof (UINT32
);
1413 Buffer
= (UINT32
*)Buffer
+ 1;
1416 if (EndAddress
& 2) {
1418 // Write the last remaining word if exist
1420 PciCf8Write16 (StartAddress
, *(UINT16
*)Buffer
);
1421 StartAddress
+= sizeof (UINT16
);
1422 Buffer
= (UINT16
*)Buffer
+ 1;
1425 if (EndAddress
& 1) {
1427 // Write the last remaining byte if exist
1429 PciCf8Write8 (StartAddress
, *(UINT8
*)Buffer
);