a3dab38ec34f43a969d769325afc3d07fda201b6
[mirror_edk2.git] / MdePkg / Library / BasePciExpressLib / PciLib.c
1 /** @file
2 PCI Library.
3
4 Functions in this library instance make use of MMIO functions in IoLib to
5 access memory mapped PCI configuration space.
6
7 All assertions for I/O operations are handled in MMIO functions in the IoLib
8 Library.
9
10 Copyright (c) 2006, Intel Corporation<BR>
11 All rights reserved. This program and the accompanying materials
12 are licensed and made available under the terms and conditions of the BSD License
13 which accompanies this distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
15
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18
19 Module Name: PciLib.c
20
21 **/
22
23 /**
24 Assert the validity of a PCI address. A valid PCI address should contain 1's
25 only in the low 28 bits.
26
27 @param A The address to validate.
28
29 **/
30 #define ASSERT_INVALID_PCI_ADDRESS(A) \
31 ASSERT (((A) & ~0xfffffff) == 0)
32
33
34 UINTN
35 EFIAPI
36 GetPciExpressBaseAddress (
37 VOID
38 )
39 {
40 /// @bug Change this to a PCD Get call to retrieve the PCI-E Base Address
41 return 0xc0000000;
42 }
43
44 /**
45 Reads an 8-bit PCI configuration register.
46
47 Reads and returns the 8-bit PCI configuration register specified by Address.
48 This function must guarantee that all PCI read and write operations are
49 serialized.
50
51 If Address > 0x0FFFFFFF, then ASSERT().
52
53 @param Address Address that encodes the PCI Bus, Device, Function and
54 Register.
55
56 @return The read value from the PCI configuration register.
57
58 **/
59 UINT8
60 EFIAPI
61 PciExpressRead8 (
62 IN UINTN Address
63 )
64 {
65 ASSERT_INVALID_PCI_ADDRESS (Address);
66 return MmioRead8 (GetPciExpressBaseAddress () + Address);
67 }
68
69 /**
70 Writes an 8-bit PCI configuration register.
71
72 Writes the 8-bit PCI configuration register specified by Address with the
73 value specified by Value. Value is returned. This function must guarantee
74 that all PCI read and write operations are serialized.
75
76 If Address > 0x0FFFFFFF, then ASSERT().
77
78 @param Address Address that encodes the PCI Bus, Device, Function and
79 Register.
80 @param Value The value to write.
81
82 @return The value written to the PCI configuration register.
83
84 **/
85 UINT8
86 EFIAPI
87 PciExpressWrite8 (
88 IN UINTN Address,
89 IN UINT8 Value
90 )
91 {
92 ASSERT_INVALID_PCI_ADDRESS (Address);
93 return MmioWrite8 (GetPciExpressBaseAddress () + Address, Value);
94 }
95
96 /**
97 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
98 an 8-bit value.
99
100 Reads the 8-bit PCI configuration register specified by Address, performs a
101 bitwise inclusive OR between the read result and the value specified by
102 OrData, and writes the result to the 8-bit PCI configuration register
103 specified by Address. The value written to the PCI configuration register is
104 returned. This function must guarantee that all PCI read and write operations
105 are serialized.
106
107 If Address > 0x0FFFFFFF, then ASSERT().
108
109 @param Address Address that encodes the PCI Bus, Device, Function and
110 Register.
111 @param OrData The value to OR with the PCI configuration register.
112
113 @return The value written back to the PCI configuration register.
114
115 **/
116 UINT8
117 EFIAPI
118 PciExpressOr8 (
119 IN UINTN Address,
120 IN UINT8 OrData
121 )
122 {
123 ASSERT_INVALID_PCI_ADDRESS (Address);
124 return MmioOr8 (GetPciExpressBaseAddress () + Address, OrData);
125 }
126
127 /**
128 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
129 value.
130
131 Reads the 8-bit PCI configuration register specified by Address, performs a
132 bitwise AND between the read result and the value specified by AndData, and
133 writes the result to the 8-bit PCI configuration register specified by
134 Address. The value written to the PCI configuration register is returned.
135 This function must guarantee that all PCI read and write operations are
136 serialized.
137
138 If Address > 0x0FFFFFFF, then ASSERT().
139
140 @param Address Address that encodes the PCI Bus, Device, Function and
141 Register.
142 @param AndData The value to AND with the PCI configuration register.
143
144 @return The value written back to the PCI configuration register.
145
146 **/
147 UINT8
148 EFIAPI
149 PciExpressAnd8 (
150 IN UINTN Address,
151 IN UINT8 AndData
152 )
153 {
154 ASSERT_INVALID_PCI_ADDRESS (Address);
155 return MmioAnd8 (GetPciExpressBaseAddress () + Address, AndData);
156 }
157
158 /**
159 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
160 value, followed a bitwise inclusive OR with another 8-bit value.
161
162 Reads the 8-bit PCI configuration register specified by Address, performs a
163 bitwise AND between the read result and the value specified by AndData,
164 performs a bitwise inclusive OR between the result of the AND operation and
165 the value specified by OrData, and writes the result to the 8-bit PCI
166 configuration register specified by Address. The value written to the PCI
167 configuration register is returned. This function must guarantee that all PCI
168 read and write operations are serialized.
169
170 If Address > 0x0FFFFFFF, then ASSERT().
171
172 @param Address Address that encodes the PCI Bus, Device, Function and
173 Register.
174 @param AndData The value to AND with the PCI configuration register.
175 @param OrData The value to OR with the result of the AND operation.
176
177 @return The value written back to the PCI configuration register.
178
179 **/
180 UINT8
181 EFIAPI
182 PciExpressAndThenOr8 (
183 IN UINTN Address,
184 IN UINT8 AndData,
185 IN UINT8 OrData
186 )
187 {
188 ASSERT_INVALID_PCI_ADDRESS (Address);
189 return MmioAndThenOr8 (
190 GetPciExpressBaseAddress () + Address,
191 AndData,
192 OrData
193 );
194 }
195
196 /**
197 Reads a bit field of a PCI configuration register.
198
199 Reads the bit field in an 8-bit PCI configuration register. The bit field is
200 specified by the StartBit and the EndBit. The value of the bit field is
201 returned.
202
203 If Address > 0x0FFFFFFF, then ASSERT().
204 If StartBit is greater than 7, then ASSERT().
205 If EndBit is greater than 7, then ASSERT().
206 If EndBit is less than or equal to StartBit, then ASSERT().
207
208 @param Address PCI configuration register to read.
209 @param StartBit The ordinal of the least significant bit in the bit field.
210 Range 0..7.
211 @param EndBit The ordinal of the most significant bit in the bit field.
212 Range 0..7.
213
214 @return The value of the bit field read from the PCI configuration register.
215
216 **/
217 UINT8
218 EFIAPI
219 PciExpressBitFieldRead8 (
220 IN UINTN Address,
221 IN UINTN StartBit,
222 IN UINTN EndBit
223 )
224 {
225 ASSERT_INVALID_PCI_ADDRESS (Address);
226 return MmioBitFieldRead8 (
227 GetPciExpressBaseAddress () + Address,
228 StartBit,
229 EndBit
230 );
231 }
232
233 /**
234 Writes a bit field to a PCI configuration register.
235
236 Writes Value to the bit field of the PCI configuration register. The bit
237 field is specified by the StartBit and the EndBit. All other bits in the
238 destination PCI configuration register are preserved. The new value of the
239 8-bit register is returned.
240
241 If Address > 0x0FFFFFFF, then ASSERT().
242 If StartBit is greater than 7, then ASSERT().
243 If EndBit is greater than 7, then ASSERT().
244 If EndBit is less than or equal to StartBit, then ASSERT().
245
246 @param Address PCI configuration register to write.
247 @param StartBit The ordinal of the least significant bit in the bit field.
248 Range 0..7.
249 @param EndBit The ordinal of the most significant bit in the bit field.
250 Range 0..7.
251 @param Value New value of the bit field.
252
253 @return The value written back to the PCI configuration register.
254
255 **/
256 UINT8
257 EFIAPI
258 PciExpressBitFieldWrite8 (
259 IN UINTN Address,
260 IN UINTN StartBit,
261 IN UINTN EndBit,
262 IN UINT8 Value
263 )
264 {
265 ASSERT_INVALID_PCI_ADDRESS (Address);
266 return MmioBitFieldWrite8 (
267 GetPciExpressBaseAddress () + Address,
268 StartBit,
269 EndBit,
270 Value
271 );
272 }
273
274 /**
275 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
276 writes the result back to the bit field in the 8-bit port.
277
278 Reads the 8-bit PCI configuration register specified by Address, performs a
279 bitwise inclusive OR between the read result and the value specified by
280 OrData, and writes the result to the 8-bit PCI configuration register
281 specified by Address. The value written to the PCI configuration register is
282 returned. This function must guarantee that all PCI read and write operations
283 are serialized. Extra left bits in OrData are stripped.
284
285 If Address > 0x0FFFFFFF, then ASSERT().
286 If StartBit is greater than 7, then ASSERT().
287 If EndBit is greater than 7, then ASSERT().
288 If EndBit is less than or equal to StartBit, then ASSERT().
289
290 @param Address PCI configuration register to write.
291 @param StartBit The ordinal of the least significant bit in the bit field.
292 Range 0..7.
293 @param EndBit The ordinal of the most significant bit in the bit field.
294 Range 0..7.
295 @param OrData The value to OR with the PCI configuration register.
296
297 @return The value written back to the PCI configuration register.
298
299 **/
300 UINT8
301 EFIAPI
302 PciExpressBitFieldOr8 (
303 IN UINTN Address,
304 IN UINTN StartBit,
305 IN UINTN EndBit,
306 IN UINT8 OrData
307 )
308 {
309 ASSERT_INVALID_PCI_ADDRESS (Address);
310 return MmioBitFieldOr8 (
311 GetPciExpressBaseAddress () + Address,
312 StartBit,
313 EndBit,
314 OrData
315 );
316 }
317
318 /**
319 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
320 AND, and writes the result back to the bit field in the 8-bit register.
321
322 Reads the 8-bit PCI configuration register specified by Address, performs a
323 bitwise AND between the read result and the value specified by AndData, and
324 writes the result to the 8-bit PCI configuration register specified by
325 Address. The value written to the PCI configuration register is returned.
326 This function must guarantee that all PCI read and write operations are
327 serialized. Extra left bits in AndData are stripped.
328
329 If Address > 0x0FFFFFFF, then ASSERT().
330 If StartBit is greater than 7, then ASSERT().
331 If EndBit is greater than 7, then ASSERT().
332 If EndBit is less than or equal to StartBit, then ASSERT().
333
334 @param Address PCI configuration register to write.
335 @param StartBit The ordinal of the least significant bit in the bit field.
336 Range 0..7.
337 @param EndBit The ordinal of the most significant bit in the bit field.
338 Range 0..7.
339 @param AndData The value to AND with the PCI configuration register.
340
341 @return The value written back to the PCI configuration register.
342
343 **/
344 UINT8
345 EFIAPI
346 PciExpressBitFieldAnd8 (
347 IN UINTN Address,
348 IN UINTN StartBit,
349 IN UINTN EndBit,
350 IN UINT8 AndData
351 )
352 {
353 ASSERT_INVALID_PCI_ADDRESS (Address);
354 return MmioBitFieldAnd8 (
355 GetPciExpressBaseAddress () + Address,
356 StartBit,
357 EndBit,
358 AndData
359 );
360 }
361
362 /**
363 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
364 bitwise inclusive OR, and writes the result back to the bit field in the
365 8-bit port.
366
367 Reads the 8-bit PCI configuration register specified by Address, performs a
368 bitwise AND followed by a bitwise inclusive OR between the read result and
369 the value specified by AndData, and writes the result to the 8-bit PCI
370 configuration register specified by Address. The value written to the PCI
371 configuration register is returned. This function must guarantee that all PCI
372 read and write operations are serialized. Extra left bits in both AndData and
373 OrData are stripped.
374
375 If Address > 0x0FFFFFFF, then ASSERT().
376 If StartBit is greater than 7, then ASSERT().
377 If EndBit is greater than 7, then ASSERT().
378 If EndBit is less than or equal to StartBit, then ASSERT().
379
380 @param Address PCI configuration register to write.
381 @param StartBit The ordinal of the least significant bit in the bit field.
382 Range 0..7.
383 @param EndBit The ordinal of the most significant bit in the bit field.
384 Range 0..7.
385 @param AndData The value to AND with the PCI configuration register.
386 @param OrData The value to OR with the result of the AND operation.
387
388 @return The value written back to the PCI configuration register.
389
390 **/
391 UINT8
392 EFIAPI
393 PciExpressBitFieldAndThenOr8 (
394 IN UINTN Address,
395 IN UINTN StartBit,
396 IN UINTN EndBit,
397 IN UINT8 AndData,
398 IN UINT8 OrData
399 )
400 {
401 ASSERT_INVALID_PCI_ADDRESS (Address);
402 return MmioBitFieldAndThenOr8 (
403 GetPciExpressBaseAddress () + Address,
404 StartBit,
405 EndBit,
406 AndData,
407 OrData
408 );
409 }
410
411 /**
412 Reads a 16-bit PCI configuration register.
413
414 Reads and returns the 16-bit PCI configuration register specified by Address.
415 This function must guarantee that all PCI read and write operations are
416 serialized.
417
418 If Address > 0x0FFFFFFF, then ASSERT().
419 If Address is not aligned on a 16-bit boundary, then ASSERT().
420
421 @param Address Address that encodes the PCI Bus, Device, Function and
422 Register.
423
424 @return The read value from the PCI configuration register.
425
426 **/
427 UINT16
428 EFIAPI
429 PciExpressRead16 (
430 IN UINTN Address
431 )
432 {
433 ASSERT_INVALID_PCI_ADDRESS (Address);
434 return MmioRead16 (GetPciExpressBaseAddress () + Address);
435 }
436
437 /**
438 Writes a 16-bit PCI configuration register.
439
440 Writes the 16-bit PCI configuration register specified by Address with the
441 value specified by Value. Value is returned. This function must guarantee
442 that all PCI read and write operations are serialized.
443
444 If Address > 0x0FFFFFFF, then ASSERT().
445 If Address is not aligned on a 16-bit boundary, then ASSERT().
446
447 @param Address Address that encodes the PCI Bus, Device, Function and
448 Register.
449 @param Value The value to write.
450
451 @return The value written to the PCI configuration register.
452
453 **/
454 UINT16
455 EFIAPI
456 PciExpressWrite16 (
457 IN UINTN Address,
458 IN UINT16 Value
459 )
460 {
461 ASSERT_INVALID_PCI_ADDRESS (Address);
462 return MmioWrite16 (GetPciExpressBaseAddress () + Address, Value);
463 }
464
465 /**
466 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
467 a 16-bit value.
468
469 Reads the 16-bit PCI configuration register specified by Address, performs a
470 bitwise inclusive OR between the read result and the value specified by
471 OrData, and writes the result to the 16-bit PCI configuration register
472 specified by Address. The value written to the PCI configuration register is
473 returned. This function must guarantee that all PCI read and write operations
474 are serialized.
475
476 If Address > 0x0FFFFFFF, then ASSERT().
477 If Address is not aligned on a 16-bit boundary, then ASSERT().
478
479 @param Address Address that encodes the PCI Bus, Device, Function and
480 Register.
481 @param OrData The value to OR with the PCI configuration register.
482
483 @return The value written back to the PCI configuration register.
484
485 **/
486 UINT16
487 EFIAPI
488 PciExpressOr16 (
489 IN UINTN Address,
490 IN UINT16 OrData
491 )
492 {
493 ASSERT_INVALID_PCI_ADDRESS (Address);
494 return MmioOr16 (GetPciExpressBaseAddress () + Address, OrData);
495 }
496
497 /**
498 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
499 value.
500
501 Reads the 16-bit PCI configuration register specified by Address, performs a
502 bitwise AND between the read result and the value specified by AndData, and
503 writes the result to the 16-bit PCI configuration register specified by
504 Address. The value written to the PCI configuration register is returned.
505 This function must guarantee that all PCI read and write operations are
506 serialized.
507
508 If Address > 0x0FFFFFFF, then ASSERT().
509 If Address is not aligned on a 16-bit boundary, then ASSERT().
510
511 @param Address Address that encodes the PCI Bus, Device, Function and
512 Register.
513 @param AndData The value to AND with the PCI configuration register.
514
515 @return The value written back to the PCI configuration register.
516
517 **/
518 UINT16
519 EFIAPI
520 PciExpressAnd16 (
521 IN UINTN Address,
522 IN UINT16 AndData
523 )
524 {
525 ASSERT_INVALID_PCI_ADDRESS (Address);
526 return MmioAnd16 (GetPciExpressBaseAddress () + Address, AndData);
527 }
528
529 /**
530 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
531 value, followed a bitwise inclusive OR with another 16-bit value.
532
533 Reads the 16-bit PCI configuration register specified by Address, performs a
534 bitwise AND between the read result and the value specified by AndData,
535 performs a bitwise inclusive OR between the result of the AND operation and
536 the value specified by OrData, and writes the result to the 16-bit PCI
537 configuration register specified by Address. The value written to the PCI
538 configuration register is returned. This function must guarantee that all PCI
539 read and write operations are serialized.
540
541 If Address > 0x0FFFFFFF, then ASSERT().
542 If Address is not aligned on a 16-bit boundary, then ASSERT().
543
544 @param Address Address that encodes the PCI Bus, Device, Function and
545 Register.
546 @param AndData The value to AND with the PCI configuration register.
547 @param OrData The value to OR with the result of the AND operation.
548
549 @return The value written back to the PCI configuration register.
550
551 **/
552 UINT16
553 EFIAPI
554 PciExpressAndThenOr16 (
555 IN UINTN Address,
556 IN UINT16 AndData,
557 IN UINT16 OrData
558 )
559 {
560 ASSERT_INVALID_PCI_ADDRESS (Address);
561 return MmioAndThenOr16 (
562 GetPciExpressBaseAddress () + Address,
563 AndData,
564 OrData
565 );
566 }
567
568 /**
569 Reads a bit field of a PCI configuration register.
570
571 Reads the bit field in a 16-bit PCI configuration register. The bit field is
572 specified by the StartBit and the EndBit. The value of the bit field is
573 returned.
574
575 If Address > 0x0FFFFFFF, then ASSERT().
576 If Address is not aligned on a 16-bit boundary, then ASSERT().
577 If StartBit is greater than 15, then ASSERT().
578 If EndBit is greater than 15, then ASSERT().
579 If EndBit is less than or equal to StartBit, then ASSERT().
580
581 @param Address PCI configuration register to read.
582 @param StartBit The ordinal of the least significant bit in the bit field.
583 Range 0..15.
584 @param EndBit The ordinal of the most significant bit in the bit field.
585 Range 0..15.
586
587 @return The value of the bit field read from the PCI configuration register.
588
589 **/
590 UINT16
591 EFIAPI
592 PciExpressBitFieldRead16 (
593 IN UINTN Address,
594 IN UINTN StartBit,
595 IN UINTN EndBit
596 )
597 {
598 ASSERT_INVALID_PCI_ADDRESS (Address);
599 return MmioBitFieldRead16 (
600 GetPciExpressBaseAddress () + Address,
601 StartBit,
602 EndBit
603 );
604 }
605
606 /**
607 Writes a bit field to a PCI configuration register.
608
609 Writes Value to the bit field of the PCI configuration register. The bit
610 field is specified by the StartBit and the EndBit. All other bits in the
611 destination PCI configuration register are preserved. The new value of the
612 16-bit register is returned.
613
614 If Address > 0x0FFFFFFF, then ASSERT().
615 If Address is not aligned on a 16-bit boundary, then ASSERT().
616 If StartBit is greater than 15, then ASSERT().
617 If EndBit is greater than 15, then ASSERT().
618 If EndBit is less than or equal to StartBit, then ASSERT().
619
620 @param Address PCI configuration register to write.
621 @param StartBit The ordinal of the least significant bit in the bit field.
622 Range 0..15.
623 @param EndBit The ordinal of the most significant bit in the bit field.
624 Range 0..15.
625 @param Value New value of the bit field.
626
627 @return The value written back to the PCI configuration register.
628
629 **/
630 UINT16
631 EFIAPI
632 PciExpressBitFieldWrite16 (
633 IN UINTN Address,
634 IN UINTN StartBit,
635 IN UINTN EndBit,
636 IN UINT16 Value
637 )
638 {
639 ASSERT_INVALID_PCI_ADDRESS (Address);
640 return MmioBitFieldWrite16 (
641 GetPciExpressBaseAddress () + Address,
642 StartBit,
643 EndBit,
644 Value
645 );
646 }
647
648 /**
649 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
650 writes the result back to the bit field in the 16-bit port.
651
652 Reads the 16-bit PCI configuration register specified by Address, performs a
653 bitwise inclusive OR between the read result and the value specified by
654 OrData, and writes the result to the 16-bit PCI configuration register
655 specified by Address. The value written to the PCI configuration register is
656 returned. This function must guarantee that all PCI read and write operations
657 are serialized. Extra left bits in OrData are stripped.
658
659 If Address > 0x0FFFFFFF, then ASSERT().
660 If Address is not aligned on a 16-bit boundary, then ASSERT().
661 If StartBit is greater than 15, then ASSERT().
662 If EndBit is greater than 15, then ASSERT().
663 If EndBit is less than or equal to StartBit, then ASSERT().
664
665 @param Address PCI configuration register to write.
666 @param StartBit The ordinal of the least significant bit in the bit field.
667 Range 0..15.
668 @param EndBit The ordinal of the most significant bit in the bit field.
669 Range 0..15.
670 @param OrData The value to OR with the PCI configuration register.
671
672 @return The value written back to the PCI configuration register.
673
674 **/
675 UINT16
676 EFIAPI
677 PciExpressBitFieldOr16 (
678 IN UINTN Address,
679 IN UINTN StartBit,
680 IN UINTN EndBit,
681 IN UINT16 OrData
682 )
683 {
684 ASSERT_INVALID_PCI_ADDRESS (Address);
685 return MmioBitFieldOr16 (
686 GetPciExpressBaseAddress () + Address,
687 StartBit,
688 EndBit,
689 OrData
690 );
691 }
692
693 /**
694 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
695 AND, and writes the result back to the bit field in the 16-bit register.
696
697 Reads the 16-bit PCI configuration register specified by Address, performs a
698 bitwise AND between the read result and the value specified by AndData, and
699 writes the result to the 16-bit PCI configuration register specified by
700 Address. The value written to the PCI configuration register is returned.
701 This function must guarantee that all PCI read and write operations are
702 serialized. Extra left bits in AndData are stripped.
703
704 If Address > 0x0FFFFFFF, then ASSERT().
705 If Address is not aligned on a 16-bit boundary, then ASSERT().
706 If StartBit is greater than 15, then ASSERT().
707 If EndBit is greater than 15, then ASSERT().
708 If EndBit is less than or equal to StartBit, then ASSERT().
709
710 @param Address PCI configuration register to write.
711 @param StartBit The ordinal of the least significant bit in the bit field.
712 Range 0..15.
713 @param EndBit The ordinal of the most significant bit in the bit field.
714 Range 0..15.
715 @param AndData The value to AND with the PCI configuration register.
716
717 @return The value written back to the PCI configuration register.
718
719 **/
720 UINT16
721 EFIAPI
722 PciExpressBitFieldAnd16 (
723 IN UINTN Address,
724 IN UINTN StartBit,
725 IN UINTN EndBit,
726 IN UINT16 AndData
727 )
728 {
729 ASSERT_INVALID_PCI_ADDRESS (Address);
730 return MmioBitFieldAnd16 (
731 GetPciExpressBaseAddress () + Address,
732 StartBit,
733 EndBit,
734 AndData
735 );
736 }
737
738 /**
739 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
740 bitwise inclusive OR, and writes the result back to the bit field in the
741 16-bit port.
742
743 Reads the 16-bit PCI configuration register specified by Address, performs a
744 bitwise AND followed by a bitwise inclusive OR between the read result and
745 the value specified by AndData, and writes the result to the 16-bit PCI
746 configuration register specified by Address. The value written to the PCI
747 configuration register is returned. This function must guarantee that all PCI
748 read and write operations are serialized. Extra left bits in both AndData and
749 OrData are stripped.
750
751 If Address > 0x0FFFFFFF, then ASSERT().
752 If Address is not aligned on a 16-bit boundary, then ASSERT().
753 If StartBit is greater than 15, then ASSERT().
754 If EndBit is greater than 15, then ASSERT().
755 If EndBit is less than or equal to StartBit, then ASSERT().
756
757 @param Address PCI configuration register to write.
758 @param StartBit The ordinal of the least significant bit in the bit field.
759 Range 0..15.
760 @param EndBit The ordinal of the most significant bit in the bit field.
761 Range 0..15.
762 @param AndData The value to AND with the PCI configuration register.
763 @param OrData The value to OR with the result of the AND operation.
764
765 @return The value written back to the PCI configuration register.
766
767 **/
768 UINT16
769 EFIAPI
770 PciExpressBitFieldAndThenOr16 (
771 IN UINTN Address,
772 IN UINTN StartBit,
773 IN UINTN EndBit,
774 IN UINT16 AndData,
775 IN UINT16 OrData
776 )
777 {
778 ASSERT_INVALID_PCI_ADDRESS (Address);
779 return MmioBitFieldAndThenOr16 (
780 GetPciExpressBaseAddress () + Address,
781 StartBit,
782 EndBit,
783 AndData,
784 OrData
785 );
786 }
787
788 /**
789 Reads a 32-bit PCI configuration register.
790
791 Reads and returns the 32-bit PCI configuration register specified by Address.
792 This function must guarantee that all PCI read and write operations are
793 serialized.
794
795 If Address > 0x0FFFFFFF, then ASSERT().
796 If Address is not aligned on a 32-bit boundary, then ASSERT().
797
798 @param Address Address that encodes the PCI Bus, Device, Function and
799 Register.
800
801 @return The read value from the PCI configuration register.
802
803 **/
804 UINT32
805 EFIAPI
806 PciExpressRead32 (
807 IN UINTN Address
808 )
809 {
810 ASSERT_INVALID_PCI_ADDRESS (Address);
811 return MmioRead32 (GetPciExpressBaseAddress () + Address);
812 }
813
814 /**
815 Writes a 32-bit PCI configuration register.
816
817 Writes the 32-bit PCI configuration register specified by Address with the
818 value specified by Value. Value is returned. This function must guarantee
819 that all PCI read and write operations are serialized.
820
821 If Address > 0x0FFFFFFF, then ASSERT().
822 If Address is not aligned on a 32-bit boundary, then ASSERT().
823
824 @param Address Address that encodes the PCI Bus, Device, Function and
825 Register.
826 @param Value The value to write.
827
828 @return The value written to the PCI configuration register.
829
830 **/
831 UINT32
832 EFIAPI
833 PciExpressWrite32 (
834 IN UINTN Address,
835 IN UINT32 Value
836 )
837 {
838 ASSERT_INVALID_PCI_ADDRESS (Address);
839 return MmioWrite32 (GetPciExpressBaseAddress () + Address, Value);
840 }
841
842 /**
843 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
844 a 32-bit value.
845
846 Reads the 32-bit PCI configuration register specified by Address, performs a
847 bitwise inclusive OR between the read result and the value specified by
848 OrData, and writes the result to the 32-bit PCI configuration register
849 specified by Address. The value written to the PCI configuration register is
850 returned. This function must guarantee that all PCI read and write operations
851 are serialized.
852
853 If Address > 0x0FFFFFFF, then ASSERT().
854 If Address is not aligned on a 32-bit boundary, then ASSERT().
855
856 @param Address Address that encodes the PCI Bus, Device, Function and
857 Register.
858 @param OrData The value to OR with the PCI configuration register.
859
860 @return The value written back to the PCI configuration register.
861
862 **/
863 UINT32
864 EFIAPI
865 PciExpressOr32 (
866 IN UINTN Address,
867 IN UINT32 OrData
868 )
869 {
870 ASSERT_INVALID_PCI_ADDRESS (Address);
871 return MmioOr32 (GetPciExpressBaseAddress () + Address, OrData);
872 }
873
874 /**
875 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
876 value.
877
878 Reads the 32-bit PCI configuration register specified by Address, performs a
879 bitwise AND between the read result and the value specified by AndData, and
880 writes the result to the 32-bit PCI configuration register specified by
881 Address. The value written to the PCI configuration register is returned.
882 This function must guarantee that all PCI read and write operations are
883 serialized.
884
885 If Address > 0x0FFFFFFF, then ASSERT().
886 If Address is not aligned on a 32-bit boundary, then ASSERT().
887
888 @param Address Address that encodes the PCI Bus, Device, Function and
889 Register.
890 @param AndData The value to AND with the PCI configuration register.
891
892 @return The value written back to the PCI configuration register.
893
894 **/
895 UINT32
896 EFIAPI
897 PciExpressAnd32 (
898 IN UINTN Address,
899 IN UINT32 AndData
900 )
901 {
902 ASSERT_INVALID_PCI_ADDRESS (Address);
903 return MmioAnd32 (GetPciExpressBaseAddress () + Address, AndData);
904 }
905
906 /**
907 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
908 value, followed a bitwise inclusive OR with another 32-bit value.
909
910 Reads the 32-bit PCI configuration register specified by Address, performs a
911 bitwise AND between the read result and the value specified by AndData,
912 performs a bitwise inclusive OR between the result of the AND operation and
913 the value specified by OrData, and writes the result to the 32-bit PCI
914 configuration register specified by Address. The value written to the PCI
915 configuration register is returned. This function must guarantee that all PCI
916 read and write operations are serialized.
917
918 If Address > 0x0FFFFFFF, then ASSERT().
919 If Address is not aligned on a 32-bit boundary, then ASSERT().
920
921 @param Address Address that encodes the PCI Bus, Device, Function and
922 Register.
923 @param AndData The value to AND with the PCI configuration register.
924 @param OrData The value to OR with the result of the AND operation.
925
926 @return The value written back to the PCI configuration register.
927
928 **/
929 UINT32
930 EFIAPI
931 PciExpressAndThenOr32 (
932 IN UINTN Address,
933 IN UINT32 AndData,
934 IN UINT32 OrData
935 )
936 {
937 ASSERT_INVALID_PCI_ADDRESS (Address);
938 return MmioAndThenOr32 (
939 GetPciExpressBaseAddress () + Address,
940 AndData,
941 OrData
942 );
943 }
944
945 /**
946 Reads a bit field of a PCI configuration register.
947
948 Reads the bit field in a 32-bit PCI configuration register. The bit field is
949 specified by the StartBit and the EndBit. The value of the bit field is
950 returned.
951
952 If Address > 0x0FFFFFFF, then ASSERT().
953 If Address is not aligned on a 32-bit boundary, then ASSERT().
954 If StartBit is greater than 31, then ASSERT().
955 If EndBit is greater than 31, then ASSERT().
956 If EndBit is less than or equal to StartBit, then ASSERT().
957
958 @param Address PCI configuration register to read.
959 @param StartBit The ordinal of the least significant bit in the bit field.
960 Range 0..31.
961 @param EndBit The ordinal of the most significant bit in the bit field.
962 Range 0..31.
963
964 @return The value of the bit field read from the PCI configuration register.
965
966 **/
967 UINT32
968 EFIAPI
969 PciExpressBitFieldRead32 (
970 IN UINTN Address,
971 IN UINTN StartBit,
972 IN UINTN EndBit
973 )
974 {
975 ASSERT_INVALID_PCI_ADDRESS (Address);
976 return MmioBitFieldRead32 (
977 GetPciExpressBaseAddress () + Address,
978 StartBit,
979 EndBit
980 );
981 }
982
983 /**
984 Writes a bit field to a PCI configuration register.
985
986 Writes Value to the bit field of the PCI configuration register. The bit
987 field is specified by the StartBit and the EndBit. All other bits in the
988 destination PCI configuration register are preserved. The new value of the
989 32-bit register is returned.
990
991 If Address > 0x0FFFFFFF, then ASSERT().
992 If Address is not aligned on a 32-bit boundary, then ASSERT().
993 If StartBit is greater than 31, then ASSERT().
994 If EndBit is greater than 31, then ASSERT().
995 If EndBit is less than or equal to StartBit, then ASSERT().
996
997 @param Address PCI configuration register to write.
998 @param StartBit The ordinal of the least significant bit in the bit field.
999 Range 0..31.
1000 @param EndBit The ordinal of the most significant bit in the bit field.
1001 Range 0..31.
1002 @param Value New value of the bit field.
1003
1004 @return The value written back to the PCI configuration register.
1005
1006 **/
1007 UINT32
1008 EFIAPI
1009 PciExpressBitFieldWrite32 (
1010 IN UINTN Address,
1011 IN UINTN StartBit,
1012 IN UINTN EndBit,
1013 IN UINT32 Value
1014 )
1015 {
1016 ASSERT_INVALID_PCI_ADDRESS (Address);
1017 return MmioBitFieldWrite32 (
1018 GetPciExpressBaseAddress () + Address,
1019 StartBit,
1020 EndBit,
1021 Value
1022 );
1023 }
1024
1025 /**
1026 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1027 writes the result back to the bit field in the 32-bit port.
1028
1029 Reads the 32-bit PCI configuration register specified by Address, performs a
1030 bitwise inclusive OR between the read result and the value specified by
1031 OrData, and writes the result to the 32-bit PCI configuration register
1032 specified by Address. The value written to the PCI configuration register is
1033 returned. This function must guarantee that all PCI read and write operations
1034 are serialized. Extra left bits in OrData are stripped.
1035
1036 If Address > 0x0FFFFFFF, then ASSERT().
1037 If Address is not aligned on a 32-bit boundary, then ASSERT().
1038 If StartBit is greater than 31, then ASSERT().
1039 If EndBit is greater than 31, then ASSERT().
1040 If EndBit is less than or equal to StartBit, then ASSERT().
1041
1042 @param Address PCI configuration register to write.
1043 @param StartBit The ordinal of the least significant bit in the bit field.
1044 Range 0..31.
1045 @param EndBit The ordinal of the most significant bit in the bit field.
1046 Range 0..31.
1047 @param OrData The value to OR with the PCI configuration register.
1048
1049 @return The value written back to the PCI configuration register.
1050
1051 **/
1052 UINT32
1053 EFIAPI
1054 PciExpressBitFieldOr32 (
1055 IN UINTN Address,
1056 IN UINTN StartBit,
1057 IN UINTN EndBit,
1058 IN UINT32 OrData
1059 )
1060 {
1061 ASSERT_INVALID_PCI_ADDRESS (Address);
1062 return MmioBitFieldOr32 (
1063 GetPciExpressBaseAddress () + Address,
1064 StartBit,
1065 EndBit,
1066 OrData
1067 );
1068 }
1069
1070 /**
1071 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1072 AND, and writes the result back to the bit field in the 32-bit register.
1073
1074 Reads the 32-bit PCI configuration register specified by Address, performs a
1075 bitwise AND between the read result and the value specified by AndData, and
1076 writes the result to the 32-bit PCI configuration register specified by
1077 Address. The value written to the PCI configuration register is returned.
1078 This function must guarantee that all PCI read and write operations are
1079 serialized. Extra left bits in AndData are stripped.
1080
1081 If Address > 0x0FFFFFFF, then ASSERT().
1082 If Address is not aligned on a 32-bit boundary, then ASSERT().
1083 If StartBit is greater than 31, then ASSERT().
1084 If EndBit is greater than 31, then ASSERT().
1085 If EndBit is less than or equal to StartBit, then ASSERT().
1086
1087 @param Address PCI configuration register to write.
1088 @param StartBit The ordinal of the least significant bit in the bit field.
1089 Range 0..31.
1090 @param EndBit The ordinal of the most significant bit in the bit field.
1091 Range 0..31.
1092 @param AndData The value to AND with the PCI configuration register.
1093
1094 @return The value written back to the PCI configuration register.
1095
1096 **/
1097 UINT32
1098 EFIAPI
1099 PciExpressBitFieldAnd32 (
1100 IN UINTN Address,
1101 IN UINTN StartBit,
1102 IN UINTN EndBit,
1103 IN UINT32 AndData
1104 )
1105 {
1106 ASSERT_INVALID_PCI_ADDRESS (Address);
1107 return MmioBitFieldAnd32 (
1108 GetPciExpressBaseAddress () + Address,
1109 StartBit,
1110 EndBit,
1111 AndData
1112 );
1113 }
1114
1115 /**
1116 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1117 bitwise inclusive OR, and writes the result back to the bit field in the
1118 32-bit port.
1119
1120 Reads the 32-bit PCI configuration register specified by Address, performs a
1121 bitwise AND followed by a bitwise inclusive OR between the read result and
1122 the value specified by AndData, and writes the result to the 32-bit PCI
1123 configuration register specified by Address. The value written to the PCI
1124 configuration register is returned. This function must guarantee that all PCI
1125 read and write operations are serialized. Extra left bits in both AndData and
1126 OrData are stripped.
1127
1128 If Address > 0x0FFFFFFF, then ASSERT().
1129 If Address is not aligned on a 32-bit boundary, then ASSERT().
1130 If StartBit is greater than 31, then ASSERT().
1131 If EndBit is greater than 31, then ASSERT().
1132 If EndBit is less than or equal to StartBit, then ASSERT().
1133
1134 @param Address PCI configuration register to write.
1135 @param StartBit The ordinal of the least significant bit in the bit field.
1136 Range 0..31.
1137 @param EndBit The ordinal of the most significant bit in the bit field.
1138 Range 0..31.
1139 @param AndData The value to AND with the PCI configuration register.
1140 @param OrData The value to OR with the result of the AND operation.
1141
1142 @return The value written back to the PCI configuration register.
1143
1144 **/
1145 UINT32
1146 EFIAPI
1147 PciExpressBitFieldAndThenOr32 (
1148 IN UINTN Address,
1149 IN UINTN StartBit,
1150 IN UINTN EndBit,
1151 IN UINT32 AndData,
1152 IN UINT32 OrData
1153 )
1154 {
1155 ASSERT_INVALID_PCI_ADDRESS (Address);
1156 return MmioBitFieldAndThenOr32 (
1157 GetPciExpressBaseAddress () + Address,
1158 StartBit,
1159 EndBit,
1160 AndData,
1161 OrData
1162 );
1163 }
1164
1165 /**
1166 Reads a range of PCI configuration registers into a caller supplied buffer.
1167
1168 Reads the range of PCI configuration registers specified by StartAddress and
1169 Size into the buffer specified by Buffer. This function only allows the PCI
1170 configuration registers from a single PCI function to be read. Size is
1171 returned. When possible 32-bit PCI configuration read cycles are used to read
1172 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1173 and 16-bit PCI configuration read cycles may be used at the beginning and the
1174 end of the range.
1175
1176 If StartAddress > 0x0FFFFFFF, then ASSERT().
1177 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1178 If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().
1179 If Buffer is NULL, then ASSERT().
1180
1181 @param StartAddress Starting address that encodes the PCI Bus, Device,
1182 Function and Register.
1183 @param Size Size in bytes of the transfer.
1184 @param Buffer Pointer to a buffer receiving the data read.
1185
1186 @return Size
1187
1188 **/
1189 UINTN
1190 EFIAPI
1191 PciExpressReadBuffer (
1192 IN UINTN StartAddress,
1193 IN UINTN Size,
1194 OUT VOID *Buffer
1195 )
1196 {
1197 UINTN EndAddress;
1198
1199 EndAddress = StartAddress + Size;
1200
1201 if (StartAddress < EndAddress && (StartAddress & 1)) {
1202 //
1203 // Read a byte if StartAddress is byte aligned
1204 //
1205 *(UINT8*)Buffer = PciExpressRead8 (StartAddress);
1206 StartAddress += sizeof (UINT8);
1207 Buffer = (UINT8*)Buffer + 1;
1208 }
1209
1210 if (StartAddress < EndAddress && (StartAddress & 2)) {
1211 //
1212 // Read a word if StartAddress is word aligned
1213 //
1214 *(UINT16*)Buffer = PciExpressRead16 (StartAddress);
1215 StartAddress += sizeof (UINT16);
1216 Buffer = (UINT16*)Buffer + 1;
1217 }
1218
1219 while (EndAddress - StartAddress >= 4) {
1220 //
1221 // Read as many double words as possible
1222 //
1223 *(UINT32*)Buffer = PciExpressRead32 (StartAddress);
1224 StartAddress += sizeof (UINT32);
1225 Buffer = (UINT32*)Buffer + 1;
1226 }
1227
1228 if ((EndAddress & 2) != 0) {
1229 //
1230 // Read the last remaining word if exist
1231 //
1232 *(UINT16*)Buffer = PciExpressRead16 (StartAddress);
1233 StartAddress += sizeof (UINT16);
1234 Buffer = (UINT16*)Buffer + 1;
1235 }
1236
1237 if (EndAddress & 1) {
1238 //
1239 // Read the last remaining byte if exist
1240 //
1241 *(UINT8*)Buffer = PciExpressRead8 (StartAddress);
1242 }
1243
1244 return Size;
1245 }
1246
1247 /**
1248 Copies the data in a caller supplied buffer to a specified range of PCI
1249 configuration space.
1250
1251 Writes the range of PCI configuration registers specified by StartAddress and
1252 Size from the buffer specified by Buffer. This function only allows the PCI
1253 configuration registers from a single PCI function to be written. Size is
1254 returned. When possible 32-bit PCI configuration write cycles are used to
1255 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1256 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1257 and the end of the range.
1258
1259 If StartAddress > 0x0FFFFFFF, then ASSERT().
1260 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1261 If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().
1262 If Buffer is NULL, then ASSERT().
1263
1264 @param StartAddress Starting address that encodes the PCI Bus, Device,
1265 Function and Register.
1266 @param Size Size in bytes of the transfer.
1267 @param Buffer Pointer to a buffer containing the data to write.
1268
1269 @return Size
1270
1271 **/
1272 UINTN
1273 EFIAPI
1274 PciExpressWriteBuffer (
1275 IN UINTN StartAddress,
1276 IN UINTN Size,
1277 IN VOID *Buffer
1278 )
1279 {
1280 UINTN EndAddress;
1281
1282 EndAddress = StartAddress + Size;
1283
1284 if ((StartAddress < EndAddress) && ((StartAddress & 1)!= 0)) {
1285 //
1286 // Write a byte if StartAddress is byte aligned
1287 //
1288 PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
1289 StartAddress += sizeof (UINT8);
1290 Buffer = (UINT8*)Buffer + 1;
1291 }
1292
1293 if (StartAddress < EndAddress && (StartAddress & 2)) {
1294 //
1295 // Write a word if StartAddress is word aligned
1296 //
1297 PciExpressWrite16 (StartAddress, *(UINT16*)Buffer);
1298 StartAddress += sizeof (UINT16);
1299 Buffer = (UINT16*)Buffer + 1;
1300 }
1301
1302 while (EndAddress - StartAddress >= 4) {
1303 //
1304 // Write as many double words as possible
1305 //
1306 PciExpressWrite32 (StartAddress, *(UINT32*)Buffer);
1307 StartAddress += sizeof (UINT32);
1308 Buffer = (UINT32*)Buffer + 1;
1309 }
1310
1311 if (EndAddress & 2) {
1312 //
1313 // Write the last remaining word if exist
1314 //
1315 PciExpressWrite16 (StartAddress, *(UINT16*)Buffer);
1316 StartAddress += sizeof (UINT16);
1317 Buffer = (UINT16*)Buffer + 1;
1318 }
1319
1320 if (EndAddress & 1) {
1321 //
1322 // Write the last remaining byte if exist
1323 //
1324 PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
1325 }
1326
1327 return Size;
1328 }