]>
git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BasePciExpressLib/PciLib.c
dd1fcd4fd0e7f0448fa396073508dc53361cc74d
4 Functions in this library instance make use of MMIO functions in IoLib to
5 access memory mapped PCI configuration space.
7 All assertions for I/O operations are handled in MMIO functions in the IoLib
10 Copyright (c) 2006, Intel Corporation<BR>
11 All rights reserved. This program and the accompanying materials
12 are licensed and made available under the terms and conditions of the BSD License
13 which accompanies this distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 // The package level header files this module uses
26 // The protocols, PPI and GUID defintions for this module
29 // The Library classes this module consumes
31 #include <Library/PciExpressLib.h>
32 #include <Library/IoLib.h>
33 #include <Library/DebugLib.h>
34 #include <Library/PcdLib.h>
38 Assert the validity of a PCI address. A valid PCI address should contain 1's
39 only in the low 28 bits.
41 @param A The address to validate.
44 #define ASSERT_INVALID_PCI_ADDRESS(A) \
45 ASSERT (((A) & ~0xfffffff) == 0)
49 Gets the base address of PCI Express.
51 This internal functions retrieves PCI Express Base Address via a PCD entry
52 PcdPciExpressBaseAddress.
54 @return The base address of PCI Express.
59 GetPciExpressBaseAddress (
63 return (VOID
*)(UINTN
) PcdGet64 (PcdPciExpressBaseAddress
);
67 Reads an 8-bit PCI configuration register.
69 Reads and returns the 8-bit PCI configuration register specified by Address.
70 This function must guarantee that all PCI read and write operations are
73 If Address > 0x0FFFFFFF, then ASSERT().
75 @param Address Address that encodes the PCI Bus, Device, Function and
78 @return The read value from the PCI configuration register.
87 ASSERT_INVALID_PCI_ADDRESS (Address
);
88 return MmioRead8 ((UINTN
) GetPciExpressBaseAddress () + Address
);
92 Writes an 8-bit PCI configuration register.
94 Writes the 8-bit PCI configuration register specified by Address with the
95 value specified by Value. Value is returned. This function must guarantee
96 that all PCI read and write operations are serialized.
98 If Address > 0x0FFFFFFF, then ASSERT().
100 @param Address Address that encodes the PCI Bus, Device, Function and
102 @param Value The value to write.
104 @return The value written to the PCI configuration register.
114 ASSERT_INVALID_PCI_ADDRESS (Address
);
115 return MmioWrite8 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
119 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
122 Reads the 8-bit PCI configuration register specified by Address, performs a
123 bitwise inclusive OR between the read result and the value specified by
124 OrData, and writes the result to the 8-bit PCI configuration register
125 specified by Address. The value written to the PCI configuration register is
126 returned. This function must guarantee that all PCI read and write operations
129 If Address > 0x0FFFFFFF, then ASSERT().
131 @param Address Address that encodes the PCI Bus, Device, Function and
133 @param OrData The value to OR with the PCI configuration register.
135 @return The value written back to the PCI configuration register.
145 ASSERT_INVALID_PCI_ADDRESS (Address
);
146 return MmioOr8 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
150 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
153 Reads the 8-bit PCI configuration register specified by Address, performs a
154 bitwise AND between the read result and the value specified by AndData, and
155 writes the result to the 8-bit PCI configuration register specified by
156 Address. The value written to the PCI configuration register is returned.
157 This function must guarantee that all PCI read and write operations are
160 If Address > 0x0FFFFFFF, then ASSERT().
162 @param Address Address that encodes the PCI Bus, Device, Function and
164 @param AndData The value to AND with the PCI configuration register.
166 @return The value written back to the PCI configuration register.
176 ASSERT_INVALID_PCI_ADDRESS (Address
);
177 return MmioAnd8 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
181 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
182 value, followed a bitwise inclusive OR with another 8-bit value.
184 Reads the 8-bit PCI configuration register specified by Address, performs a
185 bitwise AND between the read result and the value specified by AndData,
186 performs a bitwise inclusive OR between the result of the AND operation and
187 the value specified by OrData, and writes the result to the 8-bit PCI
188 configuration register specified by Address. The value written to the PCI
189 configuration register is returned. This function must guarantee that all PCI
190 read and write operations are serialized.
192 If Address > 0x0FFFFFFF, then ASSERT().
194 @param Address Address that encodes the PCI Bus, Device, Function and
196 @param AndData The value to AND with the PCI configuration register.
197 @param OrData The value to OR with the result of the AND operation.
199 @return The value written back to the PCI configuration register.
204 PciExpressAndThenOr8 (
210 ASSERT_INVALID_PCI_ADDRESS (Address
);
211 return MmioAndThenOr8 (
212 (UINTN
) GetPciExpressBaseAddress () + Address
,
219 Reads a bit field of a PCI configuration register.
221 Reads the bit field in an 8-bit PCI configuration register. The bit field is
222 specified by the StartBit and the EndBit. The value of the bit field is
225 If Address > 0x0FFFFFFF, then ASSERT().
226 If StartBit is greater than 7, then ASSERT().
227 If EndBit is greater than 7, then ASSERT().
228 If EndBit is less than StartBit, then ASSERT().
230 @param Address PCI configuration register to read.
231 @param StartBit The ordinal of the least significant bit in the bit field.
233 @param EndBit The ordinal of the most significant bit in the bit field.
236 @return The value of the bit field read from the PCI configuration register.
241 PciExpressBitFieldRead8 (
247 ASSERT_INVALID_PCI_ADDRESS (Address
);
248 return MmioBitFieldRead8 (
249 (UINTN
) GetPciExpressBaseAddress () + Address
,
256 Writes a bit field to a PCI configuration register.
258 Writes Value to the bit field of the PCI configuration register. The bit
259 field is specified by the StartBit and the EndBit. All other bits in the
260 destination PCI configuration register are preserved. The new value of the
261 8-bit register is returned.
263 If Address > 0x0FFFFFFF, then ASSERT().
264 If StartBit is greater than 7, then ASSERT().
265 If EndBit is greater than 7, then ASSERT().
266 If EndBit is less than StartBit, then ASSERT().
268 @param Address PCI configuration register to write.
269 @param StartBit The ordinal of the least significant bit in the bit field.
271 @param EndBit The ordinal of the most significant bit in the bit field.
273 @param Value New value of the bit field.
275 @return The value written back to the PCI configuration register.
280 PciExpressBitFieldWrite8 (
287 ASSERT_INVALID_PCI_ADDRESS (Address
);
288 return MmioBitFieldWrite8 (
289 (UINTN
) GetPciExpressBaseAddress () + Address
,
297 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
298 writes the result back to the bit field in the 8-bit port.
300 Reads the 8-bit PCI configuration register specified by Address, performs a
301 bitwise inclusive OR between the read result and the value specified by
302 OrData, and writes the result to the 8-bit PCI configuration register
303 specified by Address. The value written to the PCI configuration register is
304 returned. This function must guarantee that all PCI read and write operations
305 are serialized. Extra left bits in OrData are stripped.
307 If Address > 0x0FFFFFFF, then ASSERT().
308 If StartBit is greater than 7, then ASSERT().
309 If EndBit is greater than 7, then ASSERT().
310 If EndBit is less than StartBit, then ASSERT().
312 @param Address PCI configuration register to write.
313 @param StartBit The ordinal of the least significant bit in the bit field.
315 @param EndBit The ordinal of the most significant bit in the bit field.
317 @param OrData The value to OR with the PCI configuration register.
319 @return The value written back to the PCI configuration register.
324 PciExpressBitFieldOr8 (
331 ASSERT_INVALID_PCI_ADDRESS (Address
);
332 return MmioBitFieldOr8 (
333 (UINTN
) GetPciExpressBaseAddress () + Address
,
341 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
342 AND, and writes the result back to the bit field in the 8-bit register.
344 Reads the 8-bit PCI configuration register specified by Address, performs a
345 bitwise AND between the read result and the value specified by AndData, and
346 writes the result to the 8-bit PCI configuration register specified by
347 Address. The value written to the PCI configuration register is returned.
348 This function must guarantee that all PCI read and write operations are
349 serialized. Extra left bits in AndData are stripped.
351 If Address > 0x0FFFFFFF, then ASSERT().
352 If StartBit is greater than 7, then ASSERT().
353 If EndBit is greater than 7, then ASSERT().
354 If EndBit is less than StartBit, then ASSERT().
356 @param Address PCI configuration register to write.
357 @param StartBit The ordinal of the least significant bit in the bit field.
359 @param EndBit The ordinal of the most significant bit in the bit field.
361 @param AndData The value to AND with the PCI configuration register.
363 @return The value written back to the PCI configuration register.
368 PciExpressBitFieldAnd8 (
375 ASSERT_INVALID_PCI_ADDRESS (Address
);
376 return MmioBitFieldAnd8 (
377 (UINTN
) GetPciExpressBaseAddress () + Address
,
385 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
386 bitwise inclusive OR, and writes the result back to the bit field in the
389 Reads the 8-bit PCI configuration register specified by Address, performs a
390 bitwise AND followed by a bitwise inclusive OR between the read result and
391 the value specified by AndData, and writes the result to the 8-bit PCI
392 configuration register specified by Address. The value written to the PCI
393 configuration register is returned. This function must guarantee that all PCI
394 read and write operations are serialized. Extra left bits in both AndData and
397 If Address > 0x0FFFFFFF, then ASSERT().
398 If StartBit is greater than 7, then ASSERT().
399 If EndBit is greater than 7, then ASSERT().
400 If EndBit is less than StartBit, then ASSERT().
402 @param Address PCI configuration register to write.
403 @param StartBit The ordinal of the least significant bit in the bit field.
405 @param EndBit The ordinal of the most significant bit in the bit field.
407 @param AndData The value to AND with the PCI configuration register.
408 @param OrData The value to OR with the result of the AND operation.
410 @return The value written back to the PCI configuration register.
415 PciExpressBitFieldAndThenOr8 (
423 ASSERT_INVALID_PCI_ADDRESS (Address
);
424 return MmioBitFieldAndThenOr8 (
425 (UINTN
) GetPciExpressBaseAddress () + Address
,
434 Reads a 16-bit PCI configuration register.
436 Reads and returns the 16-bit PCI configuration register specified by Address.
437 This function must guarantee that all PCI read and write operations are
440 If Address > 0x0FFFFFFF, then ASSERT().
441 If Address is not aligned on a 16-bit boundary, then ASSERT().
443 @param Address Address that encodes the PCI Bus, Device, Function and
446 @return The read value from the PCI configuration register.
455 ASSERT_INVALID_PCI_ADDRESS (Address
);
456 return MmioRead16 ((UINTN
) GetPciExpressBaseAddress () + Address
);
460 Writes a 16-bit PCI configuration register.
462 Writes the 16-bit PCI configuration register specified by Address with the
463 value specified by Value. Value is returned. This function must guarantee
464 that all PCI read and write operations are serialized.
466 If Address > 0x0FFFFFFF, then ASSERT().
467 If Address is not aligned on a 16-bit boundary, then ASSERT().
469 @param Address Address that encodes the PCI Bus, Device, Function and
471 @param Value The value to write.
473 @return The value written to the PCI configuration register.
483 ASSERT_INVALID_PCI_ADDRESS (Address
);
484 return MmioWrite16 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
488 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
491 Reads the 16-bit PCI configuration register specified by Address, performs a
492 bitwise inclusive OR between the read result and the value specified by
493 OrData, and writes the result to the 16-bit PCI configuration register
494 specified by Address. The value written to the PCI configuration register is
495 returned. This function must guarantee that all PCI read and write operations
498 If Address > 0x0FFFFFFF, then ASSERT().
499 If Address is not aligned on a 16-bit boundary, then ASSERT().
501 @param Address Address that encodes the PCI Bus, Device, Function and
503 @param OrData The value to OR with the PCI configuration register.
505 @return The value written back to the PCI configuration register.
515 ASSERT_INVALID_PCI_ADDRESS (Address
);
516 return MmioOr16 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
520 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
523 Reads the 16-bit PCI configuration register specified by Address, performs a
524 bitwise AND between the read result and the value specified by AndData, and
525 writes the result to the 16-bit PCI configuration register specified by
526 Address. The value written to the PCI configuration register is returned.
527 This function must guarantee that all PCI read and write operations are
530 If Address > 0x0FFFFFFF, then ASSERT().
531 If Address is not aligned on a 16-bit boundary, then ASSERT().
533 @param Address Address that encodes the PCI Bus, Device, Function and
535 @param AndData The value to AND with the PCI configuration register.
537 @return The value written back to the PCI configuration register.
547 ASSERT_INVALID_PCI_ADDRESS (Address
);
548 return MmioAnd16 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
552 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
553 value, followed a bitwise inclusive OR with another 16-bit value.
555 Reads the 16-bit PCI configuration register specified by Address, performs a
556 bitwise AND between the read result and the value specified by AndData,
557 performs a bitwise inclusive OR between the result of the AND operation and
558 the value specified by OrData, and writes the result to the 16-bit PCI
559 configuration register specified by Address. The value written to the PCI
560 configuration register is returned. This function must guarantee that all PCI
561 read and write operations are serialized.
563 If Address > 0x0FFFFFFF, then ASSERT().
564 If Address is not aligned on a 16-bit boundary, then ASSERT().
566 @param Address Address that encodes the PCI Bus, Device, Function and
568 @param AndData The value to AND with the PCI configuration register.
569 @param OrData The value to OR with the result of the AND operation.
571 @return The value written back to the PCI configuration register.
576 PciExpressAndThenOr16 (
582 ASSERT_INVALID_PCI_ADDRESS (Address
);
583 return MmioAndThenOr16 (
584 (UINTN
) GetPciExpressBaseAddress () + Address
,
591 Reads a bit field of a PCI configuration register.
593 Reads the bit field in a 16-bit PCI configuration register. The bit field is
594 specified by the StartBit and the EndBit. The value of the bit field is
597 If Address > 0x0FFFFFFF, then ASSERT().
598 If Address is not aligned on a 16-bit boundary, then ASSERT().
599 If StartBit is greater than 15, then ASSERT().
600 If EndBit is greater than 15, then ASSERT().
601 If EndBit is less than StartBit, then ASSERT().
603 @param Address PCI configuration register to read.
604 @param StartBit The ordinal of the least significant bit in the bit field.
606 @param EndBit The ordinal of the most significant bit in the bit field.
609 @return The value of the bit field read from the PCI configuration register.
614 PciExpressBitFieldRead16 (
620 ASSERT_INVALID_PCI_ADDRESS (Address
);
621 return MmioBitFieldRead16 (
622 (UINTN
) GetPciExpressBaseAddress () + Address
,
629 Writes a bit field to a PCI configuration register.
631 Writes Value to the bit field of the PCI configuration register. The bit
632 field is specified by the StartBit and the EndBit. All other bits in the
633 destination PCI configuration register are preserved. The new value of the
634 16-bit register is returned.
636 If Address > 0x0FFFFFFF, then ASSERT().
637 If Address is not aligned on a 16-bit boundary, then ASSERT().
638 If StartBit is greater than 15, then ASSERT().
639 If EndBit is greater than 15, then ASSERT().
640 If EndBit is less than StartBit, then ASSERT().
642 @param Address PCI configuration register to write.
643 @param StartBit The ordinal of the least significant bit in the bit field.
645 @param EndBit The ordinal of the most significant bit in the bit field.
647 @param Value New value of the bit field.
649 @return The value written back to the PCI configuration register.
654 PciExpressBitFieldWrite16 (
661 ASSERT_INVALID_PCI_ADDRESS (Address
);
662 return MmioBitFieldWrite16 (
663 (UINTN
) GetPciExpressBaseAddress () + Address
,
671 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
672 writes the result back to the bit field in the 16-bit port.
674 Reads the 16-bit PCI configuration register specified by Address, performs a
675 bitwise inclusive OR between the read result and the value specified by
676 OrData, and writes the result to the 16-bit PCI configuration register
677 specified by Address. The value written to the PCI configuration register is
678 returned. This function must guarantee that all PCI read and write operations
679 are serialized. Extra left bits in OrData are stripped.
681 If Address > 0x0FFFFFFF, then ASSERT().
682 If Address is not aligned on a 16-bit boundary, then ASSERT().
683 If StartBit is greater than 15, then ASSERT().
684 If EndBit is greater than 15, then ASSERT().
685 If EndBit is less than StartBit, then ASSERT().
687 @param Address PCI configuration register to write.
688 @param StartBit The ordinal of the least significant bit in the bit field.
690 @param EndBit The ordinal of the most significant bit in the bit field.
692 @param OrData The value to OR with the PCI configuration register.
694 @return The value written back to the PCI configuration register.
699 PciExpressBitFieldOr16 (
706 ASSERT_INVALID_PCI_ADDRESS (Address
);
707 return MmioBitFieldOr16 (
708 (UINTN
) GetPciExpressBaseAddress () + Address
,
716 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
717 AND, and writes the result back to the bit field in the 16-bit register.
719 Reads the 16-bit PCI configuration register specified by Address, performs a
720 bitwise AND between the read result and the value specified by AndData, and
721 writes the result to the 16-bit PCI configuration register specified by
722 Address. The value written to the PCI configuration register is returned.
723 This function must guarantee that all PCI read and write operations are
724 serialized. Extra left bits in AndData are stripped.
726 If Address > 0x0FFFFFFF, then ASSERT().
727 If Address is not aligned on a 16-bit boundary, then ASSERT().
728 If StartBit is greater than 15, then ASSERT().
729 If EndBit is greater than 15, then ASSERT().
730 If EndBit is less than StartBit, then ASSERT().
732 @param Address PCI configuration register to write.
733 @param StartBit The ordinal of the least significant bit in the bit field.
735 @param EndBit The ordinal of the most significant bit in the bit field.
737 @param AndData The value to AND with the PCI configuration register.
739 @return The value written back to the PCI configuration register.
744 PciExpressBitFieldAnd16 (
751 ASSERT_INVALID_PCI_ADDRESS (Address
);
752 return MmioBitFieldAnd16 (
753 (UINTN
) GetPciExpressBaseAddress () + Address
,
761 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
762 bitwise inclusive OR, and writes the result back to the bit field in the
765 Reads the 16-bit PCI configuration register specified by Address, performs a
766 bitwise AND followed by a bitwise inclusive OR between the read result and
767 the value specified by AndData, and writes the result to the 16-bit PCI
768 configuration register specified by Address. The value written to the PCI
769 configuration register is returned. This function must guarantee that all PCI
770 read and write operations are serialized. Extra left bits in both AndData and
773 If Address > 0x0FFFFFFF, then ASSERT().
774 If Address is not aligned on a 16-bit boundary, then ASSERT().
775 If StartBit is greater than 15, then ASSERT().
776 If EndBit is greater than 15, then ASSERT().
777 If EndBit is less than StartBit, then ASSERT().
779 @param Address PCI configuration register to write.
780 @param StartBit The ordinal of the least significant bit in the bit field.
782 @param EndBit The ordinal of the most significant bit in the bit field.
784 @param AndData The value to AND with the PCI configuration register.
785 @param OrData The value to OR with the result of the AND operation.
787 @return The value written back to the PCI configuration register.
792 PciExpressBitFieldAndThenOr16 (
800 ASSERT_INVALID_PCI_ADDRESS (Address
);
801 return MmioBitFieldAndThenOr16 (
802 (UINTN
) GetPciExpressBaseAddress () + Address
,
811 Reads a 32-bit PCI configuration register.
813 Reads and returns the 32-bit PCI configuration register specified by Address.
814 This function must guarantee that all PCI read and write operations are
817 If Address > 0x0FFFFFFF, then ASSERT().
818 If Address is not aligned on a 32-bit boundary, then ASSERT().
820 @param Address Address that encodes the PCI Bus, Device, Function and
823 @return The read value from the PCI configuration register.
832 ASSERT_INVALID_PCI_ADDRESS (Address
);
833 return MmioRead32 ((UINTN
) GetPciExpressBaseAddress () + Address
);
837 Writes a 32-bit PCI configuration register.
839 Writes the 32-bit PCI configuration register specified by Address with the
840 value specified by Value. Value is returned. This function must guarantee
841 that all PCI read and write operations are serialized.
843 If Address > 0x0FFFFFFF, then ASSERT().
844 If Address is not aligned on a 32-bit boundary, then ASSERT().
846 @param Address Address that encodes the PCI Bus, Device, Function and
848 @param Value The value to write.
850 @return The value written to the PCI configuration register.
860 ASSERT_INVALID_PCI_ADDRESS (Address
);
861 return MmioWrite32 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
865 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
868 Reads the 32-bit PCI configuration register specified by Address, performs a
869 bitwise inclusive OR between the read result and the value specified by
870 OrData, and writes the result to the 32-bit PCI configuration register
871 specified by Address. The value written to the PCI configuration register is
872 returned. This function must guarantee that all PCI read and write operations
875 If Address > 0x0FFFFFFF, then ASSERT().
876 If Address is not aligned on a 32-bit boundary, then ASSERT().
878 @param Address Address that encodes the PCI Bus, Device, Function and
880 @param OrData The value to OR with the PCI configuration register.
882 @return The value written back to the PCI configuration register.
892 ASSERT_INVALID_PCI_ADDRESS (Address
);
893 return MmioOr32 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
897 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
900 Reads the 32-bit PCI configuration register specified by Address, performs a
901 bitwise AND between the read result and the value specified by AndData, and
902 writes the result to the 32-bit PCI configuration register specified by
903 Address. The value written to the PCI configuration register is returned.
904 This function must guarantee that all PCI read and write operations are
907 If Address > 0x0FFFFFFF, then ASSERT().
908 If Address is not aligned on a 32-bit boundary, then ASSERT().
910 @param Address Address that encodes the PCI Bus, Device, Function and
912 @param AndData The value to AND with the PCI configuration register.
914 @return The value written back to the PCI configuration register.
924 ASSERT_INVALID_PCI_ADDRESS (Address
);
925 return MmioAnd32 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
929 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
930 value, followed a bitwise inclusive OR with another 32-bit value.
932 Reads the 32-bit PCI configuration register specified by Address, performs a
933 bitwise AND between the read result and the value specified by AndData,
934 performs a bitwise inclusive OR between the result of the AND operation and
935 the value specified by OrData, and writes the result to the 32-bit PCI
936 configuration register specified by Address. The value written to the PCI
937 configuration register is returned. This function must guarantee that all PCI
938 read and write operations are serialized.
940 If Address > 0x0FFFFFFF, then ASSERT().
941 If Address is not aligned on a 32-bit boundary, then ASSERT().
943 @param Address Address that encodes the PCI Bus, Device, Function and
945 @param AndData The value to AND with the PCI configuration register.
946 @param OrData The value to OR with the result of the AND operation.
948 @return The value written back to the PCI configuration register.
953 PciExpressAndThenOr32 (
959 ASSERT_INVALID_PCI_ADDRESS (Address
);
960 return MmioAndThenOr32 (
961 (UINTN
) GetPciExpressBaseAddress () + Address
,
968 Reads a bit field of a PCI configuration register.
970 Reads the bit field in a 32-bit PCI configuration register. The bit field is
971 specified by the StartBit and the EndBit. The value of the bit field is
974 If Address > 0x0FFFFFFF, then ASSERT().
975 If Address is not aligned on a 32-bit boundary, then ASSERT().
976 If StartBit is greater than 31, then ASSERT().
977 If EndBit is greater than 31, then ASSERT().
978 If EndBit is less than StartBit, then ASSERT().
980 @param Address PCI configuration register to read.
981 @param StartBit The ordinal of the least significant bit in the bit field.
983 @param EndBit The ordinal of the most significant bit in the bit field.
986 @return The value of the bit field read from the PCI configuration register.
991 PciExpressBitFieldRead32 (
997 ASSERT_INVALID_PCI_ADDRESS (Address
);
998 return MmioBitFieldRead32 (
999 (UINTN
) GetPciExpressBaseAddress () + Address
,
1006 Writes a bit field to a PCI configuration register.
1008 Writes Value to the bit field of the PCI configuration register. The bit
1009 field is specified by the StartBit and the EndBit. All other bits in the
1010 destination PCI configuration register are preserved. The new value of the
1011 32-bit register is returned.
1013 If Address > 0x0FFFFFFF, then ASSERT().
1014 If Address is not aligned on a 32-bit boundary, then ASSERT().
1015 If StartBit is greater than 31, then ASSERT().
1016 If EndBit is greater than 31, then ASSERT().
1017 If EndBit is less than StartBit, then ASSERT().
1019 @param Address PCI configuration register to write.
1020 @param StartBit The ordinal of the least significant bit in the bit field.
1022 @param EndBit The ordinal of the most significant bit in the bit field.
1024 @param Value New value of the bit field.
1026 @return The value written back to the PCI configuration register.
1031 PciExpressBitFieldWrite32 (
1038 ASSERT_INVALID_PCI_ADDRESS (Address
);
1039 return MmioBitFieldWrite32 (
1040 (UINTN
) GetPciExpressBaseAddress () + Address
,
1048 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1049 writes the result back to the bit field in the 32-bit port.
1051 Reads the 32-bit PCI configuration register specified by Address, performs a
1052 bitwise inclusive OR between the read result and the value specified by
1053 OrData, and writes the result to the 32-bit PCI configuration register
1054 specified by Address. The value written to the PCI configuration register is
1055 returned. This function must guarantee that all PCI read and write operations
1056 are serialized. Extra left bits in OrData are stripped.
1058 If Address > 0x0FFFFFFF, then ASSERT().
1059 If Address is not aligned on a 32-bit boundary, then ASSERT().
1060 If StartBit is greater than 31, then ASSERT().
1061 If EndBit is greater than 31, then ASSERT().
1062 If EndBit is less than StartBit, then ASSERT().
1064 @param Address PCI configuration register to write.
1065 @param StartBit The ordinal of the least significant bit in the bit field.
1067 @param EndBit The ordinal of the most significant bit in the bit field.
1069 @param OrData The value to OR with the PCI configuration register.
1071 @return The value written back to the PCI configuration register.
1076 PciExpressBitFieldOr32 (
1083 ASSERT_INVALID_PCI_ADDRESS (Address
);
1084 return MmioBitFieldOr32 (
1085 (UINTN
) GetPciExpressBaseAddress () + Address
,
1093 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1094 AND, and writes the result back to the bit field in the 32-bit register.
1096 Reads the 32-bit PCI configuration register specified by Address, performs a
1097 bitwise AND between the read result and the value specified by AndData, and
1098 writes the result to the 32-bit PCI configuration register specified by
1099 Address. The value written to the PCI configuration register is returned.
1100 This function must guarantee that all PCI read and write operations are
1101 serialized. Extra left bits in AndData are stripped.
1103 If Address > 0x0FFFFFFF, then ASSERT().
1104 If Address is not aligned on a 32-bit boundary, then ASSERT().
1105 If StartBit is greater than 31, then ASSERT().
1106 If EndBit is greater than 31, then ASSERT().
1107 If EndBit is less than StartBit, then ASSERT().
1109 @param Address PCI configuration register to write.
1110 @param StartBit The ordinal of the least significant bit in the bit field.
1112 @param EndBit The ordinal of the most significant bit in the bit field.
1114 @param AndData The value to AND with the PCI configuration register.
1116 @return The value written back to the PCI configuration register.
1121 PciExpressBitFieldAnd32 (
1128 ASSERT_INVALID_PCI_ADDRESS (Address
);
1129 return MmioBitFieldAnd32 (
1130 (UINTN
) GetPciExpressBaseAddress () + Address
,
1138 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1139 bitwise inclusive OR, and writes the result back to the bit field in the
1142 Reads the 32-bit PCI configuration register specified by Address, performs a
1143 bitwise AND followed by a bitwise inclusive OR between the read result and
1144 the value specified by AndData, and writes the result to the 32-bit PCI
1145 configuration register specified by Address. The value written to the PCI
1146 configuration register is returned. This function must guarantee that all PCI
1147 read and write operations are serialized. Extra left bits in both AndData and
1148 OrData are stripped.
1150 If Address > 0x0FFFFFFF, then ASSERT().
1151 If Address is not aligned on a 32-bit boundary, then ASSERT().
1152 If StartBit is greater than 31, then ASSERT().
1153 If EndBit is greater than 31, then ASSERT().
1154 If EndBit is less than StartBit, then ASSERT().
1156 @param Address PCI configuration register to write.
1157 @param StartBit The ordinal of the least significant bit in the bit field.
1159 @param EndBit The ordinal of the most significant bit in the bit field.
1161 @param AndData The value to AND with the PCI configuration register.
1162 @param OrData The value to OR with the result of the AND operation.
1164 @return The value written back to the PCI configuration register.
1169 PciExpressBitFieldAndThenOr32 (
1177 ASSERT_INVALID_PCI_ADDRESS (Address
);
1178 return MmioBitFieldAndThenOr32 (
1179 (UINTN
) GetPciExpressBaseAddress () + Address
,
1188 Reads a range of PCI configuration registers into a caller supplied buffer.
1190 Reads the range of PCI configuration registers specified by StartAddress and
1191 Size into the buffer specified by Buffer. This function only allows the PCI
1192 configuration registers from a single PCI function to be read. Size is
1193 returned. When possible 32-bit PCI configuration read cycles are used to read
1194 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1195 and 16-bit PCI configuration read cycles may be used at the beginning and the
1198 If StartAddress > 0x0FFFFFFF, then ASSERT().
1199 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1200 If Size > 0 and Buffer is NULL, then ASSERT().
1202 @param StartAddress Starting address that encodes the PCI Bus, Device,
1203 Function and Register.
1204 @param Size Size in bytes of the transfer.
1205 @param Buffer Pointer to a buffer receiving the data read.
1212 PciExpressReadBuffer (
1213 IN UINTN StartAddress
,
1220 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1221 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1227 ASSERT (Buffer
!= NULL
);
1230 // Save Size for return
1234 if ((StartAddress
& 1) != 0) {
1236 // Read a byte if StartAddress is byte aligned
1238 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1239 StartAddress
+= sizeof (UINT8
);
1240 Size
-= sizeof (UINT8
);
1241 Buffer
= (UINT8
*)Buffer
+ 1;
1244 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1246 // Read a word if StartAddress is word aligned
1248 *(volatile UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1249 StartAddress
+= sizeof (UINT16
);
1250 Size
-= sizeof (UINT16
);
1251 Buffer
= (UINT16
*)Buffer
+ 1;
1254 while (Size
>= sizeof (UINT32
)) {
1256 // Read as many double words as possible
1258 *(volatile UINT32
*)Buffer
= PciExpressRead32 (StartAddress
);
1259 StartAddress
+= sizeof (UINT32
);
1260 Size
-= sizeof (UINT32
);
1261 Buffer
= (UINT32
*)Buffer
+ 1;
1264 if (Size
>= sizeof (UINT16
)) {
1266 // Read the last remaining word if exist
1268 *(volatile UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1269 StartAddress
+= sizeof (UINT16
);
1270 Size
-= sizeof (UINT16
);
1271 Buffer
= (UINT16
*)Buffer
+ 1;
1274 if (Size
>= sizeof (UINT8
)) {
1276 // Read the last remaining byte if exist
1278 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1285 Copies the data in a caller supplied buffer to a specified range of PCI
1286 configuration space.
1288 Writes the range of PCI configuration registers specified by StartAddress and
1289 Size from the buffer specified by Buffer. This function only allows the PCI
1290 configuration registers from a single PCI function to be written. Size is
1291 returned. When possible 32-bit PCI configuration write cycles are used to
1292 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1293 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1294 and the end of the range.
1296 If StartAddress > 0x0FFFFFFF, then ASSERT().
1297 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1298 If Size > 0 and Buffer is NULL, then ASSERT().
1300 @param StartAddress Starting address that encodes the PCI Bus, Device,
1301 Function and Register.
1302 @param Size Size in bytes of the transfer.
1303 @param Buffer Pointer to a buffer containing the data to write.
1310 PciExpressWriteBuffer (
1311 IN UINTN StartAddress
,
1318 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1319 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1325 ASSERT (Buffer
!= NULL
);
1328 // Save Size for return
1332 if ((StartAddress
& 1) != 0) {
1334 // Write a byte if StartAddress is byte aligned
1336 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1337 StartAddress
+= sizeof (UINT8
);
1338 Size
-= sizeof (UINT8
);
1339 Buffer
= (UINT8
*)Buffer
+ 1;
1342 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1344 // Write a word if StartAddress is word aligned
1346 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1347 StartAddress
+= sizeof (UINT16
);
1348 Size
-= sizeof (UINT16
);
1349 Buffer
= (UINT16
*)Buffer
+ 1;
1352 while (Size
>= sizeof (UINT32
)) {
1354 // Write as many double words as possible
1356 PciExpressWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1357 StartAddress
+= sizeof (UINT32
);
1358 Size
-= sizeof (UINT32
);
1359 Buffer
= (UINT32
*)Buffer
+ 1;
1362 if (Size
>= sizeof (UINT16
)) {
1364 // Write the last remaining word if exist
1366 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1367 StartAddress
+= sizeof (UINT16
);
1368 Size
-= sizeof (UINT16
);
1369 Buffer
= (UINT16
*)Buffer
+ 1;
1372 if (Size
>= sizeof (UINT8
)) {
1374 // Write the last remaining byte if exist
1376 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);