]>
git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BasePciExpressLib/PciLib.c
4 Functions in this library instance make use of MMIO functions in IoLib to
5 access memory mapped PCI configuration space.
7 All assertions for I/O operations are handled in MMIO functions in the IoLib
10 Copyright (c) 2006, Intel Corporation<BR>
11 All rights reserved. This program and the accompanying materials
12 are licensed and made available under the terms and conditions of the BSD License
13 which accompanies this distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
24 // The package level header files this module uses
28 // The protocols, PPI and GUID defintions for this module
31 // The Library classes this module consumes
33 #include <Library/PciExpressLib.h>
34 #include <Library/IoLib.h>
35 #include <Library/DebugLib.h>
36 #include <Library/PcdLib.h>
40 Assert the validity of a PCI address. A valid PCI address should contain 1's
41 only in the low 28 bits.
43 @param A The address to validate.
46 #define ASSERT_INVALID_PCI_ADDRESS(A) \
47 ASSERT (((A) & ~0xfffffff) == 0)
51 Gets the base address of PCI Express.
53 This internal functions retrieves PCI Express Base Address via a PCD entry
54 PcdPciExpressBaseAddress.
56 @return The base address of PCI Express.
61 GetPciExpressBaseAddress (
65 return (VOID
*)(UINTN
) PcdGet64 (PcdPciExpressBaseAddress
);
69 Reads an 8-bit PCI configuration register.
71 Reads and returns the 8-bit PCI configuration register specified by Address.
72 This function must guarantee that all PCI read and write operations are
75 If Address > 0x0FFFFFFF, then ASSERT().
77 @param Address Address that encodes the PCI Bus, Device, Function and
80 @return The read value from the PCI configuration register.
89 ASSERT_INVALID_PCI_ADDRESS (Address
);
90 return MmioRead8 ((UINTN
) GetPciExpressBaseAddress () + Address
);
94 Writes an 8-bit PCI configuration register.
96 Writes the 8-bit PCI configuration register specified by Address with the
97 value specified by Value. Value is returned. This function must guarantee
98 that all PCI read and write operations are serialized.
100 If Address > 0x0FFFFFFF, then ASSERT().
102 @param Address Address that encodes the PCI Bus, Device, Function and
104 @param Value The value to write.
106 @return The value written to the PCI configuration register.
116 ASSERT_INVALID_PCI_ADDRESS (Address
);
117 return MmioWrite8 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
121 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
124 Reads the 8-bit PCI configuration register specified by Address, performs a
125 bitwise inclusive OR between the read result and the value specified by
126 OrData, and writes the result to the 8-bit PCI configuration register
127 specified by Address. The value written to the PCI configuration register is
128 returned. This function must guarantee that all PCI read and write operations
131 If Address > 0x0FFFFFFF, then ASSERT().
133 @param Address Address that encodes the PCI Bus, Device, Function and
135 @param OrData The value to OR with the PCI configuration register.
137 @return The value written back to the PCI configuration register.
147 ASSERT_INVALID_PCI_ADDRESS (Address
);
148 return MmioOr8 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
152 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
155 Reads the 8-bit PCI configuration register specified by Address, performs a
156 bitwise AND between the read result and the value specified by AndData, and
157 writes the result to the 8-bit PCI configuration register specified by
158 Address. The value written to the PCI configuration register is returned.
159 This function must guarantee that all PCI read and write operations are
162 If Address > 0x0FFFFFFF, then ASSERT().
164 @param Address Address that encodes the PCI Bus, Device, Function and
166 @param AndData The value to AND with the PCI configuration register.
168 @return The value written back to the PCI configuration register.
178 ASSERT_INVALID_PCI_ADDRESS (Address
);
179 return MmioAnd8 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
183 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
184 value, followed a bitwise inclusive OR with another 8-bit value.
186 Reads the 8-bit PCI configuration register specified by Address, performs a
187 bitwise AND between the read result and the value specified by AndData,
188 performs a bitwise inclusive OR between the result of the AND operation and
189 the value specified by OrData, and writes the result to the 8-bit PCI
190 configuration register specified by Address. The value written to the PCI
191 configuration register is returned. This function must guarantee that all PCI
192 read and write operations are serialized.
194 If Address > 0x0FFFFFFF, then ASSERT().
196 @param Address Address that encodes the PCI Bus, Device, Function and
198 @param AndData The value to AND with the PCI configuration register.
199 @param OrData The value to OR with the result of the AND operation.
201 @return The value written back to the PCI configuration register.
206 PciExpressAndThenOr8 (
212 ASSERT_INVALID_PCI_ADDRESS (Address
);
213 return MmioAndThenOr8 (
214 (UINTN
) GetPciExpressBaseAddress () + Address
,
221 Reads a bit field of a PCI configuration register.
223 Reads the bit field in an 8-bit PCI configuration register. The bit field is
224 specified by the StartBit and the EndBit. The value of the bit field is
227 If Address > 0x0FFFFFFF, then ASSERT().
228 If StartBit is greater than 7, then ASSERT().
229 If EndBit is greater than 7, then ASSERT().
230 If EndBit is less than StartBit, then ASSERT().
232 @param Address PCI configuration register to read.
233 @param StartBit The ordinal of the least significant bit in the bit field.
235 @param EndBit The ordinal of the most significant bit in the bit field.
238 @return The value of the bit field read from the PCI configuration register.
243 PciExpressBitFieldRead8 (
249 ASSERT_INVALID_PCI_ADDRESS (Address
);
250 return MmioBitFieldRead8 (
251 (UINTN
) GetPciExpressBaseAddress () + Address
,
258 Writes a bit field to a PCI configuration register.
260 Writes Value to the bit field of the PCI configuration register. The bit
261 field is specified by the StartBit and the EndBit. All other bits in the
262 destination PCI configuration register are preserved. The new value of the
263 8-bit register is returned.
265 If Address > 0x0FFFFFFF, then ASSERT().
266 If StartBit is greater than 7, then ASSERT().
267 If EndBit is greater than 7, then ASSERT().
268 If EndBit is less than StartBit, then ASSERT().
270 @param Address PCI configuration register to write.
271 @param StartBit The ordinal of the least significant bit in the bit field.
273 @param EndBit The ordinal of the most significant bit in the bit field.
275 @param Value New value of the bit field.
277 @return The value written back to the PCI configuration register.
282 PciExpressBitFieldWrite8 (
289 ASSERT_INVALID_PCI_ADDRESS (Address
);
290 return MmioBitFieldWrite8 (
291 (UINTN
) GetPciExpressBaseAddress () + Address
,
299 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
300 writes the result back to the bit field in the 8-bit port.
302 Reads the 8-bit PCI configuration register specified by Address, performs a
303 bitwise inclusive OR between the read result and the value specified by
304 OrData, and writes the result to the 8-bit PCI configuration register
305 specified by Address. The value written to the PCI configuration register is
306 returned. This function must guarantee that all PCI read and write operations
307 are serialized. Extra left bits in OrData are stripped.
309 If Address > 0x0FFFFFFF, then ASSERT().
310 If StartBit is greater than 7, then ASSERT().
311 If EndBit is greater than 7, then ASSERT().
312 If EndBit is less than StartBit, then ASSERT().
314 @param Address PCI configuration register to write.
315 @param StartBit The ordinal of the least significant bit in the bit field.
317 @param EndBit The ordinal of the most significant bit in the bit field.
319 @param OrData The value to OR with the PCI configuration register.
321 @return The value written back to the PCI configuration register.
326 PciExpressBitFieldOr8 (
333 ASSERT_INVALID_PCI_ADDRESS (Address
);
334 return MmioBitFieldOr8 (
335 (UINTN
) GetPciExpressBaseAddress () + Address
,
343 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
344 AND, and writes the result back to the bit field in the 8-bit register.
346 Reads the 8-bit PCI configuration register specified by Address, performs a
347 bitwise AND between the read result and the value specified by AndData, and
348 writes the result to the 8-bit PCI configuration register specified by
349 Address. The value written to the PCI configuration register is returned.
350 This function must guarantee that all PCI read and write operations are
351 serialized. Extra left bits in AndData are stripped.
353 If Address > 0x0FFFFFFF, then ASSERT().
354 If StartBit is greater than 7, then ASSERT().
355 If EndBit is greater than 7, then ASSERT().
356 If EndBit is less than StartBit, then ASSERT().
358 @param Address PCI configuration register to write.
359 @param StartBit The ordinal of the least significant bit in the bit field.
361 @param EndBit The ordinal of the most significant bit in the bit field.
363 @param AndData The value to AND with the PCI configuration register.
365 @return The value written back to the PCI configuration register.
370 PciExpressBitFieldAnd8 (
377 ASSERT_INVALID_PCI_ADDRESS (Address
);
378 return MmioBitFieldAnd8 (
379 (UINTN
) GetPciExpressBaseAddress () + Address
,
387 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
388 bitwise inclusive OR, and writes the result back to the bit field in the
391 Reads the 8-bit PCI configuration register specified by Address, performs a
392 bitwise AND followed by a bitwise inclusive OR between the read result and
393 the value specified by AndData, and writes the result to the 8-bit PCI
394 configuration register specified by Address. The value written to the PCI
395 configuration register is returned. This function must guarantee that all PCI
396 read and write operations are serialized. Extra left bits in both AndData and
399 If Address > 0x0FFFFFFF, then ASSERT().
400 If StartBit is greater than 7, then ASSERT().
401 If EndBit is greater than 7, then ASSERT().
402 If EndBit is less than StartBit, then ASSERT().
404 @param Address PCI configuration register to write.
405 @param StartBit The ordinal of the least significant bit in the bit field.
407 @param EndBit The ordinal of the most significant bit in the bit field.
409 @param AndData The value to AND with the PCI configuration register.
410 @param OrData The value to OR with the result of the AND operation.
412 @return The value written back to the PCI configuration register.
417 PciExpressBitFieldAndThenOr8 (
425 ASSERT_INVALID_PCI_ADDRESS (Address
);
426 return MmioBitFieldAndThenOr8 (
427 (UINTN
) GetPciExpressBaseAddress () + Address
,
436 Reads a 16-bit PCI configuration register.
438 Reads and returns the 16-bit PCI configuration register specified by Address.
439 This function must guarantee that all PCI read and write operations are
442 If Address > 0x0FFFFFFF, then ASSERT().
443 If Address is not aligned on a 16-bit boundary, then ASSERT().
445 @param Address Address that encodes the PCI Bus, Device, Function and
448 @return The read value from the PCI configuration register.
457 ASSERT_INVALID_PCI_ADDRESS (Address
);
458 return MmioRead16 ((UINTN
) GetPciExpressBaseAddress () + Address
);
462 Writes a 16-bit PCI configuration register.
464 Writes the 16-bit PCI configuration register specified by Address with the
465 value specified by Value. Value is returned. This function must guarantee
466 that all PCI read and write operations are serialized.
468 If Address > 0x0FFFFFFF, then ASSERT().
469 If Address is not aligned on a 16-bit boundary, then ASSERT().
471 @param Address Address that encodes the PCI Bus, Device, Function and
473 @param Value The value to write.
475 @return The value written to the PCI configuration register.
485 ASSERT_INVALID_PCI_ADDRESS (Address
);
486 return MmioWrite16 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
490 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
493 Reads the 16-bit PCI configuration register specified by Address, performs a
494 bitwise inclusive OR between the read result and the value specified by
495 OrData, and writes the result to the 16-bit PCI configuration register
496 specified by Address. The value written to the PCI configuration register is
497 returned. This function must guarantee that all PCI read and write operations
500 If Address > 0x0FFFFFFF, then ASSERT().
501 If Address is not aligned on a 16-bit boundary, then ASSERT().
503 @param Address Address that encodes the PCI Bus, Device, Function and
505 @param OrData The value to OR with the PCI configuration register.
507 @return The value written back to the PCI configuration register.
517 ASSERT_INVALID_PCI_ADDRESS (Address
);
518 return MmioOr16 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
522 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
525 Reads the 16-bit PCI configuration register specified by Address, performs a
526 bitwise AND between the read result and the value specified by AndData, and
527 writes the result to the 16-bit PCI configuration register specified by
528 Address. The value written to the PCI configuration register is returned.
529 This function must guarantee that all PCI read and write operations are
532 If Address > 0x0FFFFFFF, then ASSERT().
533 If Address is not aligned on a 16-bit boundary, then ASSERT().
535 @param Address Address that encodes the PCI Bus, Device, Function and
537 @param AndData The value to AND with the PCI configuration register.
539 @return The value written back to the PCI configuration register.
549 ASSERT_INVALID_PCI_ADDRESS (Address
);
550 return MmioAnd16 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
554 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
555 value, followed a bitwise inclusive OR with another 16-bit value.
557 Reads the 16-bit PCI configuration register specified by Address, performs a
558 bitwise AND between the read result and the value specified by AndData,
559 performs a bitwise inclusive OR between the result of the AND operation and
560 the value specified by OrData, and writes the result to the 16-bit PCI
561 configuration register specified by Address. The value written to the PCI
562 configuration register is returned. This function must guarantee that all PCI
563 read and write operations are serialized.
565 If Address > 0x0FFFFFFF, then ASSERT().
566 If Address is not aligned on a 16-bit boundary, then ASSERT().
568 @param Address Address that encodes the PCI Bus, Device, Function and
570 @param AndData The value to AND with the PCI configuration register.
571 @param OrData The value to OR with the result of the AND operation.
573 @return The value written back to the PCI configuration register.
578 PciExpressAndThenOr16 (
584 ASSERT_INVALID_PCI_ADDRESS (Address
);
585 return MmioAndThenOr16 (
586 (UINTN
) GetPciExpressBaseAddress () + Address
,
593 Reads a bit field of a PCI configuration register.
595 Reads the bit field in a 16-bit PCI configuration register. The bit field is
596 specified by the StartBit and the EndBit. The value of the bit field is
599 If Address > 0x0FFFFFFF, then ASSERT().
600 If Address is not aligned on a 16-bit boundary, then ASSERT().
601 If StartBit is greater than 15, then ASSERT().
602 If EndBit is greater than 15, then ASSERT().
603 If EndBit is less than StartBit, then ASSERT().
605 @param Address PCI configuration register to read.
606 @param StartBit The ordinal of the least significant bit in the bit field.
608 @param EndBit The ordinal of the most significant bit in the bit field.
611 @return The value of the bit field read from the PCI configuration register.
616 PciExpressBitFieldRead16 (
622 ASSERT_INVALID_PCI_ADDRESS (Address
);
623 return MmioBitFieldRead16 (
624 (UINTN
) GetPciExpressBaseAddress () + Address
,
631 Writes a bit field to a PCI configuration register.
633 Writes Value to the bit field of the PCI configuration register. The bit
634 field is specified by the StartBit and the EndBit. All other bits in the
635 destination PCI configuration register are preserved. The new value of the
636 16-bit register is returned.
638 If Address > 0x0FFFFFFF, then ASSERT().
639 If Address is not aligned on a 16-bit boundary, then ASSERT().
640 If StartBit is greater than 15, then ASSERT().
641 If EndBit is greater than 15, then ASSERT().
642 If EndBit is less than StartBit, then ASSERT().
644 @param Address PCI configuration register to write.
645 @param StartBit The ordinal of the least significant bit in the bit field.
647 @param EndBit The ordinal of the most significant bit in the bit field.
649 @param Value New value of the bit field.
651 @return The value written back to the PCI configuration register.
656 PciExpressBitFieldWrite16 (
663 ASSERT_INVALID_PCI_ADDRESS (Address
);
664 return MmioBitFieldWrite16 (
665 (UINTN
) GetPciExpressBaseAddress () + Address
,
673 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
674 writes the result back to the bit field in the 16-bit port.
676 Reads the 16-bit PCI configuration register specified by Address, performs a
677 bitwise inclusive OR between the read result and the value specified by
678 OrData, and writes the result to the 16-bit PCI configuration register
679 specified by Address. The value written to the PCI configuration register is
680 returned. This function must guarantee that all PCI read and write operations
681 are serialized. Extra left bits in OrData are stripped.
683 If Address > 0x0FFFFFFF, then ASSERT().
684 If Address is not aligned on a 16-bit boundary, then ASSERT().
685 If StartBit is greater than 15, then ASSERT().
686 If EndBit is greater than 15, then ASSERT().
687 If EndBit is less than StartBit, then ASSERT().
689 @param Address PCI configuration register to write.
690 @param StartBit The ordinal of the least significant bit in the bit field.
692 @param EndBit The ordinal of the most significant bit in the bit field.
694 @param OrData The value to OR with the PCI configuration register.
696 @return The value written back to the PCI configuration register.
701 PciExpressBitFieldOr16 (
708 ASSERT_INVALID_PCI_ADDRESS (Address
);
709 return MmioBitFieldOr16 (
710 (UINTN
) GetPciExpressBaseAddress () + Address
,
718 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
719 AND, and writes the result back to the bit field in the 16-bit register.
721 Reads the 16-bit PCI configuration register specified by Address, performs a
722 bitwise AND between the read result and the value specified by AndData, and
723 writes the result to the 16-bit PCI configuration register specified by
724 Address. The value written to the PCI configuration register is returned.
725 This function must guarantee that all PCI read and write operations are
726 serialized. Extra left bits in AndData are stripped.
728 If Address > 0x0FFFFFFF, then ASSERT().
729 If Address is not aligned on a 16-bit boundary, then ASSERT().
730 If StartBit is greater than 15, then ASSERT().
731 If EndBit is greater than 15, then ASSERT().
732 If EndBit is less than StartBit, then ASSERT().
734 @param Address PCI configuration register to write.
735 @param StartBit The ordinal of the least significant bit in the bit field.
737 @param EndBit The ordinal of the most significant bit in the bit field.
739 @param AndData The value to AND with the PCI configuration register.
741 @return The value written back to the PCI configuration register.
746 PciExpressBitFieldAnd16 (
753 ASSERT_INVALID_PCI_ADDRESS (Address
);
754 return MmioBitFieldAnd16 (
755 (UINTN
) GetPciExpressBaseAddress () + Address
,
763 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
764 bitwise inclusive OR, and writes the result back to the bit field in the
767 Reads the 16-bit PCI configuration register specified by Address, performs a
768 bitwise AND followed by a bitwise inclusive OR between the read result and
769 the value specified by AndData, and writes the result to the 16-bit PCI
770 configuration register specified by Address. The value written to the PCI
771 configuration register is returned. This function must guarantee that all PCI
772 read and write operations are serialized. Extra left bits in both AndData and
775 If Address > 0x0FFFFFFF, then ASSERT().
776 If Address is not aligned on a 16-bit boundary, then ASSERT().
777 If StartBit is greater than 15, then ASSERT().
778 If EndBit is greater than 15, then ASSERT().
779 If EndBit is less than StartBit, then ASSERT().
781 @param Address PCI configuration register to write.
782 @param StartBit The ordinal of the least significant bit in the bit field.
784 @param EndBit The ordinal of the most significant bit in the bit field.
786 @param AndData The value to AND with the PCI configuration register.
787 @param OrData The value to OR with the result of the AND operation.
789 @return The value written back to the PCI configuration register.
794 PciExpressBitFieldAndThenOr16 (
802 ASSERT_INVALID_PCI_ADDRESS (Address
);
803 return MmioBitFieldAndThenOr16 (
804 (UINTN
) GetPciExpressBaseAddress () + Address
,
813 Reads a 32-bit PCI configuration register.
815 Reads and returns the 32-bit PCI configuration register specified by Address.
816 This function must guarantee that all PCI read and write operations are
819 If Address > 0x0FFFFFFF, then ASSERT().
820 If Address is not aligned on a 32-bit boundary, then ASSERT().
822 @param Address Address that encodes the PCI Bus, Device, Function and
825 @return The read value from the PCI configuration register.
834 ASSERT_INVALID_PCI_ADDRESS (Address
);
835 return MmioRead32 ((UINTN
) GetPciExpressBaseAddress () + Address
);
839 Writes a 32-bit PCI configuration register.
841 Writes the 32-bit PCI configuration register specified by Address with the
842 value specified by Value. Value is returned. This function must guarantee
843 that all PCI read and write operations are serialized.
845 If Address > 0x0FFFFFFF, then ASSERT().
846 If Address is not aligned on a 32-bit boundary, then ASSERT().
848 @param Address Address that encodes the PCI Bus, Device, Function and
850 @param Value The value to write.
852 @return The value written to the PCI configuration register.
862 ASSERT_INVALID_PCI_ADDRESS (Address
);
863 return MmioWrite32 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
867 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
870 Reads the 32-bit PCI configuration register specified by Address, performs a
871 bitwise inclusive OR between the read result and the value specified by
872 OrData, and writes the result to the 32-bit PCI configuration register
873 specified by Address. The value written to the PCI configuration register is
874 returned. This function must guarantee that all PCI read and write operations
877 If Address > 0x0FFFFFFF, then ASSERT().
878 If Address is not aligned on a 32-bit boundary, then ASSERT().
880 @param Address Address that encodes the PCI Bus, Device, Function and
882 @param OrData The value to OR with the PCI configuration register.
884 @return The value written back to the PCI configuration register.
894 ASSERT_INVALID_PCI_ADDRESS (Address
);
895 return MmioOr32 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
899 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
902 Reads the 32-bit PCI configuration register specified by Address, performs a
903 bitwise AND between the read result and the value specified by AndData, and
904 writes the result to the 32-bit PCI configuration register specified by
905 Address. The value written to the PCI configuration register is returned.
906 This function must guarantee that all PCI read and write operations are
909 If Address > 0x0FFFFFFF, then ASSERT().
910 If Address is not aligned on a 32-bit boundary, then ASSERT().
912 @param Address Address that encodes the PCI Bus, Device, Function and
914 @param AndData The value to AND with the PCI configuration register.
916 @return The value written back to the PCI configuration register.
926 ASSERT_INVALID_PCI_ADDRESS (Address
);
927 return MmioAnd32 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
931 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
932 value, followed a bitwise inclusive OR with another 32-bit value.
934 Reads the 32-bit PCI configuration register specified by Address, performs a
935 bitwise AND between the read result and the value specified by AndData,
936 performs a bitwise inclusive OR between the result of the AND operation and
937 the value specified by OrData, and writes the result to the 32-bit PCI
938 configuration register specified by Address. The value written to the PCI
939 configuration register is returned. This function must guarantee that all PCI
940 read and write operations are serialized.
942 If Address > 0x0FFFFFFF, then ASSERT().
943 If Address is not aligned on a 32-bit boundary, then ASSERT().
945 @param Address Address that encodes the PCI Bus, Device, Function and
947 @param AndData The value to AND with the PCI configuration register.
948 @param OrData The value to OR with the result of the AND operation.
950 @return The value written back to the PCI configuration register.
955 PciExpressAndThenOr32 (
961 ASSERT_INVALID_PCI_ADDRESS (Address
);
962 return MmioAndThenOr32 (
963 (UINTN
) GetPciExpressBaseAddress () + Address
,
970 Reads a bit field of a PCI configuration register.
972 Reads the bit field in a 32-bit PCI configuration register. The bit field is
973 specified by the StartBit and the EndBit. The value of the bit field is
976 If Address > 0x0FFFFFFF, then ASSERT().
977 If Address is not aligned on a 32-bit boundary, then ASSERT().
978 If StartBit is greater than 31, then ASSERT().
979 If EndBit is greater than 31, then ASSERT().
980 If EndBit is less than StartBit, then ASSERT().
982 @param Address PCI configuration register to read.
983 @param StartBit The ordinal of the least significant bit in the bit field.
985 @param EndBit The ordinal of the most significant bit in the bit field.
988 @return The value of the bit field read from the PCI configuration register.
993 PciExpressBitFieldRead32 (
999 ASSERT_INVALID_PCI_ADDRESS (Address
);
1000 return MmioBitFieldRead32 (
1001 (UINTN
) GetPciExpressBaseAddress () + Address
,
1008 Writes a bit field to a PCI configuration register.
1010 Writes Value to the bit field of the PCI configuration register. The bit
1011 field is specified by the StartBit and the EndBit. All other bits in the
1012 destination PCI configuration register are preserved. The new value of the
1013 32-bit register is returned.
1015 If Address > 0x0FFFFFFF, then ASSERT().
1016 If Address is not aligned on a 32-bit boundary, then ASSERT().
1017 If StartBit is greater than 31, then ASSERT().
1018 If EndBit is greater than 31, then ASSERT().
1019 If EndBit is less than StartBit, then ASSERT().
1021 @param Address PCI configuration register to write.
1022 @param StartBit The ordinal of the least significant bit in the bit field.
1024 @param EndBit The ordinal of the most significant bit in the bit field.
1026 @param Value New value of the bit field.
1028 @return The value written back to the PCI configuration register.
1033 PciExpressBitFieldWrite32 (
1040 ASSERT_INVALID_PCI_ADDRESS (Address
);
1041 return MmioBitFieldWrite32 (
1042 (UINTN
) GetPciExpressBaseAddress () + Address
,
1050 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1051 writes the result back to the bit field in the 32-bit port.
1053 Reads the 32-bit PCI configuration register specified by Address, performs a
1054 bitwise inclusive OR between the read result and the value specified by
1055 OrData, and writes the result to the 32-bit PCI configuration register
1056 specified by Address. The value written to the PCI configuration register is
1057 returned. This function must guarantee that all PCI read and write operations
1058 are serialized. Extra left bits in OrData are stripped.
1060 If Address > 0x0FFFFFFF, then ASSERT().
1061 If Address is not aligned on a 32-bit boundary, then ASSERT().
1062 If StartBit is greater than 31, then ASSERT().
1063 If EndBit is greater than 31, then ASSERT().
1064 If EndBit is less than StartBit, then ASSERT().
1066 @param Address PCI configuration register to write.
1067 @param StartBit The ordinal of the least significant bit in the bit field.
1069 @param EndBit The ordinal of the most significant bit in the bit field.
1071 @param OrData The value to OR with the PCI configuration register.
1073 @return The value written back to the PCI configuration register.
1078 PciExpressBitFieldOr32 (
1085 ASSERT_INVALID_PCI_ADDRESS (Address
);
1086 return MmioBitFieldOr32 (
1087 (UINTN
) GetPciExpressBaseAddress () + Address
,
1095 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1096 AND, and writes the result back to the bit field in the 32-bit register.
1098 Reads the 32-bit PCI configuration register specified by Address, performs a
1099 bitwise AND between the read result and the value specified by AndData, and
1100 writes the result to the 32-bit PCI configuration register specified by
1101 Address. The value written to the PCI configuration register is returned.
1102 This function must guarantee that all PCI read and write operations are
1103 serialized. Extra left bits in AndData are stripped.
1105 If Address > 0x0FFFFFFF, then ASSERT().
1106 If Address is not aligned on a 32-bit boundary, then ASSERT().
1107 If StartBit is greater than 31, then ASSERT().
1108 If EndBit is greater than 31, then ASSERT().
1109 If EndBit is less than StartBit, then ASSERT().
1111 @param Address PCI configuration register to write.
1112 @param StartBit The ordinal of the least significant bit in the bit field.
1114 @param EndBit The ordinal of the most significant bit in the bit field.
1116 @param AndData The value to AND with the PCI configuration register.
1118 @return The value written back to the PCI configuration register.
1123 PciExpressBitFieldAnd32 (
1130 ASSERT_INVALID_PCI_ADDRESS (Address
);
1131 return MmioBitFieldAnd32 (
1132 (UINTN
) GetPciExpressBaseAddress () + Address
,
1140 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1141 bitwise inclusive OR, and writes the result back to the bit field in the
1144 Reads the 32-bit PCI configuration register specified by Address, performs a
1145 bitwise AND followed by a bitwise inclusive OR between the read result and
1146 the value specified by AndData, and writes the result to the 32-bit PCI
1147 configuration register specified by Address. The value written to the PCI
1148 configuration register is returned. This function must guarantee that all PCI
1149 read and write operations are serialized. Extra left bits in both AndData and
1150 OrData are stripped.
1152 If Address > 0x0FFFFFFF, then ASSERT().
1153 If Address is not aligned on a 32-bit boundary, then ASSERT().
1154 If StartBit is greater than 31, then ASSERT().
1155 If EndBit is greater than 31, then ASSERT().
1156 If EndBit is less than StartBit, then ASSERT().
1158 @param Address PCI configuration register to write.
1159 @param StartBit The ordinal of the least significant bit in the bit field.
1161 @param EndBit The ordinal of the most significant bit in the bit field.
1163 @param AndData The value to AND with the PCI configuration register.
1164 @param OrData The value to OR with the result of the AND operation.
1166 @return The value written back to the PCI configuration register.
1171 PciExpressBitFieldAndThenOr32 (
1179 ASSERT_INVALID_PCI_ADDRESS (Address
);
1180 return MmioBitFieldAndThenOr32 (
1181 (UINTN
) GetPciExpressBaseAddress () + Address
,
1190 Reads a range of PCI configuration registers into a caller supplied buffer.
1192 Reads the range of PCI configuration registers specified by StartAddress and
1193 Size into the buffer specified by Buffer. This function only allows the PCI
1194 configuration registers from a single PCI function to be read. Size is
1195 returned. When possible 32-bit PCI configuration read cycles are used to read
1196 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1197 and 16-bit PCI configuration read cycles may be used at the beginning and the
1200 If StartAddress > 0x0FFFFFFF, then ASSERT().
1201 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1202 If Size > 0 and Buffer is NULL, then ASSERT().
1204 @param StartAddress Starting address that encodes the PCI Bus, Device,
1205 Function and Register.
1206 @param Size Size in bytes of the transfer.
1207 @param Buffer Pointer to a buffer receiving the data read.
1214 PciExpressReadBuffer (
1215 IN UINTN StartAddress
,
1222 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1223 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1229 ASSERT (Buffer
!= NULL
);
1232 // Save Size for return
1236 if ((StartAddress
& 1) != 0) {
1238 // Read a byte if StartAddress is byte aligned
1240 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1241 StartAddress
+= sizeof (UINT8
);
1242 Size
-= sizeof (UINT8
);
1243 Buffer
= (UINT8
*)Buffer
+ 1;
1246 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1248 // Read a word if StartAddress is word aligned
1250 *(volatile UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1251 StartAddress
+= sizeof (UINT16
);
1252 Size
-= sizeof (UINT16
);
1253 Buffer
= (UINT16
*)Buffer
+ 1;
1256 while (Size
>= sizeof (UINT32
)) {
1258 // Read as many double words as possible
1260 *(volatile UINT32
*)Buffer
= PciExpressRead32 (StartAddress
);
1261 StartAddress
+= sizeof (UINT32
);
1262 Size
-= sizeof (UINT32
);
1263 Buffer
= (UINT32
*)Buffer
+ 1;
1266 if (Size
>= sizeof (UINT16
)) {
1268 // Read the last remaining word if exist
1270 *(volatile UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1271 StartAddress
+= sizeof (UINT16
);
1272 Size
-= sizeof (UINT16
);
1273 Buffer
= (UINT16
*)Buffer
+ 1;
1276 if (Size
>= sizeof (UINT8
)) {
1278 // Read the last remaining byte if exist
1280 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1287 Copies the data in a caller supplied buffer to a specified range of PCI
1288 configuration space.
1290 Writes the range of PCI configuration registers specified by StartAddress and
1291 Size from the buffer specified by Buffer. This function only allows the PCI
1292 configuration registers from a single PCI function to be written. Size is
1293 returned. When possible 32-bit PCI configuration write cycles are used to
1294 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1295 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1296 and the end of the range.
1298 If StartAddress > 0x0FFFFFFF, then ASSERT().
1299 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1300 If Size > 0 and Buffer is NULL, then ASSERT().
1302 @param StartAddress Starting address that encodes the PCI Bus, Device,
1303 Function and Register.
1304 @param Size Size in bytes of the transfer.
1305 @param Buffer Pointer to a buffer containing the data to write.
1312 PciExpressWriteBuffer (
1313 IN UINTN StartAddress
,
1320 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1321 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1327 ASSERT (Buffer
!= NULL
);
1330 // Save Size for return
1334 if ((StartAddress
& 1) != 0) {
1336 // Write a byte if StartAddress is byte aligned
1338 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1339 StartAddress
+= sizeof (UINT8
);
1340 Size
-= sizeof (UINT8
);
1341 Buffer
= (UINT8
*)Buffer
+ 1;
1344 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1346 // Write a word if StartAddress is word aligned
1348 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1349 StartAddress
+= sizeof (UINT16
);
1350 Size
-= sizeof (UINT16
);
1351 Buffer
= (UINT16
*)Buffer
+ 1;
1354 while (Size
>= sizeof (UINT32
)) {
1356 // Write as many double words as possible
1358 PciExpressWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1359 StartAddress
+= sizeof (UINT32
);
1360 Size
-= sizeof (UINT32
);
1361 Buffer
= (UINT32
*)Buffer
+ 1;
1364 if (Size
>= sizeof (UINT16
)) {
1366 // Write the last remaining word if exist
1368 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1369 StartAddress
+= sizeof (UINT16
);
1370 Size
-= sizeof (UINT16
);
1371 Buffer
= (UINT16
*)Buffer
+ 1;
1374 if (Size
>= sizeof (UINT8
)) {
1376 // Write the last remaining byte if exist
1378 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);