]>
git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BasePciExpressLib/PciLib.c
4 Functions in this library instance make use of MMIO functions in IoLib to
5 access memory mapped PCI configuration space.
7 All assertions for I/O operations are handled in MMIO functions in the IoLib
10 Copyright (c) 2006, Intel Corporation<BR>
11 All rights reserved. This program and the accompanying materials
12 are licensed and made available under the terms and conditions of the BSD License
13 which accompanies this distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
25 #include <Library/PciExpressLib.h>
26 #include <Library/IoLib.h>
27 #include <Library/DebugLib.h>
28 #include <Library/PcdLib.h>
32 Assert the validity of a PCI address. A valid PCI address should contain 1's
33 only in the low 28 bits.
35 @param A The address to validate.
38 #define ASSERT_INVALID_PCI_ADDRESS(A) \
39 ASSERT (((A) & ~0xfffffff) == 0)
43 Gets the base address of PCI Express.
45 This internal functions retrieves PCI Express Base Address via a PCD entry
46 PcdPciExpressBaseAddress.
48 @return The base address of PCI Express.
53 GetPciExpressBaseAddress (
57 return (VOID
*)(UINTN
) PcdGet64 (PcdPciExpressBaseAddress
);
61 Reads an 8-bit PCI configuration register.
63 Reads and returns the 8-bit PCI configuration register specified by Address.
64 This function must guarantee that all PCI read and write operations are
67 If Address > 0x0FFFFFFF, then ASSERT().
69 @param Address Address that encodes the PCI Bus, Device, Function and
72 @return The read value from the PCI configuration register.
81 ASSERT_INVALID_PCI_ADDRESS (Address
);
82 return MmioRead8 ((UINTN
) GetPciExpressBaseAddress () + Address
);
86 Writes an 8-bit PCI configuration register.
88 Writes the 8-bit PCI configuration register specified by Address with the
89 value specified by Value. Value is returned. This function must guarantee
90 that all PCI read and write operations are serialized.
92 If Address > 0x0FFFFFFF, then ASSERT().
94 @param Address Address that encodes the PCI Bus, Device, Function and
96 @param Value The value to write.
98 @return The value written to the PCI configuration register.
108 ASSERT_INVALID_PCI_ADDRESS (Address
);
109 return MmioWrite8 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
113 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
116 Reads the 8-bit PCI configuration register specified by Address, performs a
117 bitwise inclusive OR between the read result and the value specified by
118 OrData, and writes the result to the 8-bit PCI configuration register
119 specified by Address. The value written to the PCI configuration register is
120 returned. This function must guarantee that all PCI read and write operations
123 If Address > 0x0FFFFFFF, then ASSERT().
125 @param Address Address that encodes the PCI Bus, Device, Function and
127 @param OrData The value to OR with the PCI configuration register.
129 @return The value written back to the PCI configuration register.
139 ASSERT_INVALID_PCI_ADDRESS (Address
);
140 return MmioOr8 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
144 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
147 Reads the 8-bit PCI configuration register specified by Address, performs a
148 bitwise AND between the read result and the value specified by AndData, and
149 writes the result to the 8-bit PCI configuration register specified by
150 Address. The value written to the PCI configuration register is returned.
151 This function must guarantee that all PCI read and write operations are
154 If Address > 0x0FFFFFFF, then ASSERT().
156 @param Address Address that encodes the PCI Bus, Device, Function and
158 @param AndData The value to AND with the PCI configuration register.
160 @return The value written back to the PCI configuration register.
170 ASSERT_INVALID_PCI_ADDRESS (Address
);
171 return MmioAnd8 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
175 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
176 value, followed a bitwise inclusive OR with another 8-bit value.
178 Reads the 8-bit PCI configuration register specified by Address, performs a
179 bitwise AND between the read result and the value specified by AndData,
180 performs a bitwise inclusive OR between the result of the AND operation and
181 the value specified by OrData, and writes the result to the 8-bit PCI
182 configuration register specified by Address. The value written to the PCI
183 configuration register is returned. This function must guarantee that all PCI
184 read and write operations are serialized.
186 If Address > 0x0FFFFFFF, then ASSERT().
188 @param Address Address that encodes the PCI Bus, Device, Function and
190 @param AndData The value to AND with the PCI configuration register.
191 @param OrData The value to OR with the result of the AND operation.
193 @return The value written back to the PCI configuration register.
198 PciExpressAndThenOr8 (
204 ASSERT_INVALID_PCI_ADDRESS (Address
);
205 return MmioAndThenOr8 (
206 (UINTN
) GetPciExpressBaseAddress () + Address
,
213 Reads a bit field of a PCI configuration register.
215 Reads the bit field in an 8-bit PCI configuration register. The bit field is
216 specified by the StartBit and the EndBit. The value of the bit field is
219 If Address > 0x0FFFFFFF, then ASSERT().
220 If StartBit is greater than 7, then ASSERT().
221 If EndBit is greater than 7, then ASSERT().
222 If EndBit is less than StartBit, then ASSERT().
224 @param Address PCI configuration register to read.
225 @param StartBit The ordinal of the least significant bit in the bit field.
227 @param EndBit The ordinal of the most significant bit in the bit field.
230 @return The value of the bit field read from the PCI configuration register.
235 PciExpressBitFieldRead8 (
241 ASSERT_INVALID_PCI_ADDRESS (Address
);
242 return MmioBitFieldRead8 (
243 (UINTN
) GetPciExpressBaseAddress () + Address
,
250 Writes a bit field to a PCI configuration register.
252 Writes Value to the bit field of the PCI configuration register. The bit
253 field is specified by the StartBit and the EndBit. All other bits in the
254 destination PCI configuration register are preserved. The new value of the
255 8-bit register is returned.
257 If Address > 0x0FFFFFFF, then ASSERT().
258 If StartBit is greater than 7, then ASSERT().
259 If EndBit is greater than 7, then ASSERT().
260 If EndBit is less than StartBit, then ASSERT().
262 @param Address PCI configuration register to write.
263 @param StartBit The ordinal of the least significant bit in the bit field.
265 @param EndBit The ordinal of the most significant bit in the bit field.
267 @param Value New value of the bit field.
269 @return The value written back to the PCI configuration register.
274 PciExpressBitFieldWrite8 (
281 ASSERT_INVALID_PCI_ADDRESS (Address
);
282 return MmioBitFieldWrite8 (
283 (UINTN
) GetPciExpressBaseAddress () + Address
,
291 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
292 writes the result back to the bit field in the 8-bit port.
294 Reads the 8-bit PCI configuration register specified by Address, performs a
295 bitwise inclusive OR between the read result and the value specified by
296 OrData, and writes the result to the 8-bit PCI configuration register
297 specified by Address. The value written to the PCI configuration register is
298 returned. This function must guarantee that all PCI read and write operations
299 are serialized. Extra left bits in OrData are stripped.
301 If Address > 0x0FFFFFFF, then ASSERT().
302 If StartBit is greater than 7, then ASSERT().
303 If EndBit is greater than 7, then ASSERT().
304 If EndBit is less than StartBit, then ASSERT().
306 @param Address PCI configuration register to write.
307 @param StartBit The ordinal of the least significant bit in the bit field.
309 @param EndBit The ordinal of the most significant bit in the bit field.
311 @param OrData The value to OR with the PCI configuration register.
313 @return The value written back to the PCI configuration register.
318 PciExpressBitFieldOr8 (
325 ASSERT_INVALID_PCI_ADDRESS (Address
);
326 return MmioBitFieldOr8 (
327 (UINTN
) GetPciExpressBaseAddress () + Address
,
335 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
336 AND, and writes the result back to the bit field in the 8-bit register.
338 Reads the 8-bit PCI configuration register specified by Address, performs a
339 bitwise AND between the read result and the value specified by AndData, and
340 writes the result to the 8-bit PCI configuration register specified by
341 Address. The value written to the PCI configuration register is returned.
342 This function must guarantee that all PCI read and write operations are
343 serialized. Extra left bits in AndData are stripped.
345 If Address > 0x0FFFFFFF, then ASSERT().
346 If StartBit is greater than 7, then ASSERT().
347 If EndBit is greater than 7, then ASSERT().
348 If EndBit is less than StartBit, then ASSERT().
350 @param Address PCI configuration register to write.
351 @param StartBit The ordinal of the least significant bit in the bit field.
353 @param EndBit The ordinal of the most significant bit in the bit field.
355 @param AndData The value to AND with the PCI configuration register.
357 @return The value written back to the PCI configuration register.
362 PciExpressBitFieldAnd8 (
369 ASSERT_INVALID_PCI_ADDRESS (Address
);
370 return MmioBitFieldAnd8 (
371 (UINTN
) GetPciExpressBaseAddress () + Address
,
379 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
380 bitwise inclusive OR, and writes the result back to the bit field in the
383 Reads the 8-bit PCI configuration register specified by Address, performs a
384 bitwise AND followed by a bitwise inclusive OR between the read result and
385 the value specified by AndData, and writes the result to the 8-bit PCI
386 configuration register specified by Address. The value written to the PCI
387 configuration register is returned. This function must guarantee that all PCI
388 read and write operations are serialized. Extra left bits in both AndData and
391 If Address > 0x0FFFFFFF, then ASSERT().
392 If StartBit is greater than 7, then ASSERT().
393 If EndBit is greater than 7, then ASSERT().
394 If EndBit is less than StartBit, then ASSERT().
396 @param Address PCI configuration register to write.
397 @param StartBit The ordinal of the least significant bit in the bit field.
399 @param EndBit The ordinal of the most significant bit in the bit field.
401 @param AndData The value to AND with the PCI configuration register.
402 @param OrData The value to OR with the result of the AND operation.
404 @return The value written back to the PCI configuration register.
409 PciExpressBitFieldAndThenOr8 (
417 ASSERT_INVALID_PCI_ADDRESS (Address
);
418 return MmioBitFieldAndThenOr8 (
419 (UINTN
) GetPciExpressBaseAddress () + Address
,
428 Reads a 16-bit PCI configuration register.
430 Reads and returns the 16-bit PCI configuration register specified by Address.
431 This function must guarantee that all PCI read and write operations are
434 If Address > 0x0FFFFFFF, then ASSERT().
435 If Address is not aligned on a 16-bit boundary, then ASSERT().
437 @param Address Address that encodes the PCI Bus, Device, Function and
440 @return The read value from the PCI configuration register.
449 ASSERT_INVALID_PCI_ADDRESS (Address
);
450 return MmioRead16 ((UINTN
) GetPciExpressBaseAddress () + Address
);
454 Writes a 16-bit PCI configuration register.
456 Writes the 16-bit PCI configuration register specified by Address with the
457 value specified by Value. Value is returned. This function must guarantee
458 that all PCI read and write operations are serialized.
460 If Address > 0x0FFFFFFF, then ASSERT().
461 If Address is not aligned on a 16-bit boundary, then ASSERT().
463 @param Address Address that encodes the PCI Bus, Device, Function and
465 @param Value The value to write.
467 @return The value written to the PCI configuration register.
477 ASSERT_INVALID_PCI_ADDRESS (Address
);
478 return MmioWrite16 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
482 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
485 Reads the 16-bit PCI configuration register specified by Address, performs a
486 bitwise inclusive OR between the read result and the value specified by
487 OrData, and writes the result to the 16-bit PCI configuration register
488 specified by Address. The value written to the PCI configuration register is
489 returned. This function must guarantee that all PCI read and write operations
492 If Address > 0x0FFFFFFF, then ASSERT().
493 If Address is not aligned on a 16-bit boundary, then ASSERT().
495 @param Address Address that encodes the PCI Bus, Device, Function and
497 @param OrData The value to OR with the PCI configuration register.
499 @return The value written back to the PCI configuration register.
509 ASSERT_INVALID_PCI_ADDRESS (Address
);
510 return MmioOr16 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
514 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
517 Reads the 16-bit PCI configuration register specified by Address, performs a
518 bitwise AND between the read result and the value specified by AndData, and
519 writes the result to the 16-bit PCI configuration register specified by
520 Address. The value written to the PCI configuration register is returned.
521 This function must guarantee that all PCI read and write operations are
524 If Address > 0x0FFFFFFF, then ASSERT().
525 If Address is not aligned on a 16-bit boundary, then ASSERT().
527 @param Address Address that encodes the PCI Bus, Device, Function and
529 @param AndData The value to AND with the PCI configuration register.
531 @return The value written back to the PCI configuration register.
541 ASSERT_INVALID_PCI_ADDRESS (Address
);
542 return MmioAnd16 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
546 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
547 value, followed a bitwise inclusive OR with another 16-bit value.
549 Reads the 16-bit PCI configuration register specified by Address, performs a
550 bitwise AND between the read result and the value specified by AndData,
551 performs a bitwise inclusive OR between the result of the AND operation and
552 the value specified by OrData, and writes the result to the 16-bit PCI
553 configuration register specified by Address. The value written to the PCI
554 configuration register is returned. This function must guarantee that all PCI
555 read and write operations are serialized.
557 If Address > 0x0FFFFFFF, then ASSERT().
558 If Address is not aligned on a 16-bit boundary, then ASSERT().
560 @param Address Address that encodes the PCI Bus, Device, Function and
562 @param AndData The value to AND with the PCI configuration register.
563 @param OrData The value to OR with the result of the AND operation.
565 @return The value written back to the PCI configuration register.
570 PciExpressAndThenOr16 (
576 ASSERT_INVALID_PCI_ADDRESS (Address
);
577 return MmioAndThenOr16 (
578 (UINTN
) GetPciExpressBaseAddress () + Address
,
585 Reads a bit field of a PCI configuration register.
587 Reads the bit field in a 16-bit PCI configuration register. The bit field is
588 specified by the StartBit and the EndBit. The value of the bit field is
591 If Address > 0x0FFFFFFF, then ASSERT().
592 If Address is not aligned on a 16-bit boundary, then ASSERT().
593 If StartBit is greater than 15, then ASSERT().
594 If EndBit is greater than 15, then ASSERT().
595 If EndBit is less than StartBit, then ASSERT().
597 @param Address PCI configuration register to read.
598 @param StartBit The ordinal of the least significant bit in the bit field.
600 @param EndBit The ordinal of the most significant bit in the bit field.
603 @return The value of the bit field read from the PCI configuration register.
608 PciExpressBitFieldRead16 (
614 ASSERT_INVALID_PCI_ADDRESS (Address
);
615 return MmioBitFieldRead16 (
616 (UINTN
) GetPciExpressBaseAddress () + Address
,
623 Writes a bit field to a PCI configuration register.
625 Writes Value to the bit field of the PCI configuration register. The bit
626 field is specified by the StartBit and the EndBit. All other bits in the
627 destination PCI configuration register are preserved. The new value of the
628 16-bit register is returned.
630 If Address > 0x0FFFFFFF, then ASSERT().
631 If Address is not aligned on a 16-bit boundary, then ASSERT().
632 If StartBit is greater than 15, then ASSERT().
633 If EndBit is greater than 15, then ASSERT().
634 If EndBit is less than StartBit, then ASSERT().
636 @param Address PCI configuration register to write.
637 @param StartBit The ordinal of the least significant bit in the bit field.
639 @param EndBit The ordinal of the most significant bit in the bit field.
641 @param Value New value of the bit field.
643 @return The value written back to the PCI configuration register.
648 PciExpressBitFieldWrite16 (
655 ASSERT_INVALID_PCI_ADDRESS (Address
);
656 return MmioBitFieldWrite16 (
657 (UINTN
) GetPciExpressBaseAddress () + Address
,
665 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
666 writes the result back to the bit field in the 16-bit port.
668 Reads the 16-bit PCI configuration register specified by Address, performs a
669 bitwise inclusive OR between the read result and the value specified by
670 OrData, and writes the result to the 16-bit PCI configuration register
671 specified by Address. The value written to the PCI configuration register is
672 returned. This function must guarantee that all PCI read and write operations
673 are serialized. Extra left bits in OrData are stripped.
675 If Address > 0x0FFFFFFF, then ASSERT().
676 If Address is not aligned on a 16-bit boundary, then ASSERT().
677 If StartBit is greater than 15, then ASSERT().
678 If EndBit is greater than 15, then ASSERT().
679 If EndBit is less than StartBit, then ASSERT().
681 @param Address PCI configuration register to write.
682 @param StartBit The ordinal of the least significant bit in the bit field.
684 @param EndBit The ordinal of the most significant bit in the bit field.
686 @param OrData The value to OR with the PCI configuration register.
688 @return The value written back to the PCI configuration register.
693 PciExpressBitFieldOr16 (
700 ASSERT_INVALID_PCI_ADDRESS (Address
);
701 return MmioBitFieldOr16 (
702 (UINTN
) GetPciExpressBaseAddress () + Address
,
710 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
711 AND, and writes the result back to the bit field in the 16-bit register.
713 Reads the 16-bit PCI configuration register specified by Address, performs a
714 bitwise AND between the read result and the value specified by AndData, and
715 writes the result to the 16-bit PCI configuration register specified by
716 Address. The value written to the PCI configuration register is returned.
717 This function must guarantee that all PCI read and write operations are
718 serialized. Extra left bits in AndData are stripped.
720 If Address > 0x0FFFFFFF, then ASSERT().
721 If Address is not aligned on a 16-bit boundary, then ASSERT().
722 If StartBit is greater than 15, then ASSERT().
723 If EndBit is greater than 15, then ASSERT().
724 If EndBit is less than StartBit, then ASSERT().
726 @param Address PCI configuration register to write.
727 @param StartBit The ordinal of the least significant bit in the bit field.
729 @param EndBit The ordinal of the most significant bit in the bit field.
731 @param AndData The value to AND with the PCI configuration register.
733 @return The value written back to the PCI configuration register.
738 PciExpressBitFieldAnd16 (
745 ASSERT_INVALID_PCI_ADDRESS (Address
);
746 return MmioBitFieldAnd16 (
747 (UINTN
) GetPciExpressBaseAddress () + Address
,
755 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
756 bitwise inclusive OR, and writes the result back to the bit field in the
759 Reads the 16-bit PCI configuration register specified by Address, performs a
760 bitwise AND followed by a bitwise inclusive OR between the read result and
761 the value specified by AndData, and writes the result to the 16-bit PCI
762 configuration register specified by Address. The value written to the PCI
763 configuration register is returned. This function must guarantee that all PCI
764 read and write operations are serialized. Extra left bits in both AndData and
767 If Address > 0x0FFFFFFF, then ASSERT().
768 If Address is not aligned on a 16-bit boundary, then ASSERT().
769 If StartBit is greater than 15, then ASSERT().
770 If EndBit is greater than 15, then ASSERT().
771 If EndBit is less than StartBit, then ASSERT().
773 @param Address PCI configuration register to write.
774 @param StartBit The ordinal of the least significant bit in the bit field.
776 @param EndBit The ordinal of the most significant bit in the bit field.
778 @param AndData The value to AND with the PCI configuration register.
779 @param OrData The value to OR with the result of the AND operation.
781 @return The value written back to the PCI configuration register.
786 PciExpressBitFieldAndThenOr16 (
794 ASSERT_INVALID_PCI_ADDRESS (Address
);
795 return MmioBitFieldAndThenOr16 (
796 (UINTN
) GetPciExpressBaseAddress () + Address
,
805 Reads a 32-bit PCI configuration register.
807 Reads and returns the 32-bit PCI configuration register specified by Address.
808 This function must guarantee that all PCI read and write operations are
811 If Address > 0x0FFFFFFF, then ASSERT().
812 If Address is not aligned on a 32-bit boundary, then ASSERT().
814 @param Address Address that encodes the PCI Bus, Device, Function and
817 @return The read value from the PCI configuration register.
826 ASSERT_INVALID_PCI_ADDRESS (Address
);
827 return MmioRead32 ((UINTN
) GetPciExpressBaseAddress () + Address
);
831 Writes a 32-bit PCI configuration register.
833 Writes the 32-bit PCI configuration register specified by Address with the
834 value specified by Value. Value is returned. This function must guarantee
835 that all PCI read and write operations are serialized.
837 If Address > 0x0FFFFFFF, then ASSERT().
838 If Address is not aligned on a 32-bit boundary, then ASSERT().
840 @param Address Address that encodes the PCI Bus, Device, Function and
842 @param Value The value to write.
844 @return The value written to the PCI configuration register.
854 ASSERT_INVALID_PCI_ADDRESS (Address
);
855 return MmioWrite32 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
859 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
862 Reads the 32-bit PCI configuration register specified by Address, performs a
863 bitwise inclusive OR between the read result and the value specified by
864 OrData, and writes the result to the 32-bit PCI configuration register
865 specified by Address. The value written to the PCI configuration register is
866 returned. This function must guarantee that all PCI read and write operations
869 If Address > 0x0FFFFFFF, then ASSERT().
870 If Address is not aligned on a 32-bit boundary, then ASSERT().
872 @param Address Address that encodes the PCI Bus, Device, Function and
874 @param OrData The value to OR with the PCI configuration register.
876 @return The value written back to the PCI configuration register.
886 ASSERT_INVALID_PCI_ADDRESS (Address
);
887 return MmioOr32 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
891 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
894 Reads the 32-bit PCI configuration register specified by Address, performs a
895 bitwise AND between the read result and the value specified by AndData, and
896 writes the result to the 32-bit PCI configuration register specified by
897 Address. The value written to the PCI configuration register is returned.
898 This function must guarantee that all PCI read and write operations are
901 If Address > 0x0FFFFFFF, then ASSERT().
902 If Address is not aligned on a 32-bit boundary, then ASSERT().
904 @param Address Address that encodes the PCI Bus, Device, Function and
906 @param AndData The value to AND with the PCI configuration register.
908 @return The value written back to the PCI configuration register.
918 ASSERT_INVALID_PCI_ADDRESS (Address
);
919 return MmioAnd32 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
923 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
924 value, followed a bitwise inclusive OR with another 32-bit value.
926 Reads the 32-bit PCI configuration register specified by Address, performs a
927 bitwise AND between the read result and the value specified by AndData,
928 performs a bitwise inclusive OR between the result of the AND operation and
929 the value specified by OrData, and writes the result to the 32-bit PCI
930 configuration register specified by Address. The value written to the PCI
931 configuration register is returned. This function must guarantee that all PCI
932 read and write operations are serialized.
934 If Address > 0x0FFFFFFF, then ASSERT().
935 If Address is not aligned on a 32-bit boundary, then ASSERT().
937 @param Address Address that encodes the PCI Bus, Device, Function and
939 @param AndData The value to AND with the PCI configuration register.
940 @param OrData The value to OR with the result of the AND operation.
942 @return The value written back to the PCI configuration register.
947 PciExpressAndThenOr32 (
953 ASSERT_INVALID_PCI_ADDRESS (Address
);
954 return MmioAndThenOr32 (
955 (UINTN
) GetPciExpressBaseAddress () + Address
,
962 Reads a bit field of a PCI configuration register.
964 Reads the bit field in a 32-bit PCI configuration register. The bit field is
965 specified by the StartBit and the EndBit. The value of the bit field is
968 If Address > 0x0FFFFFFF, then ASSERT().
969 If Address is not aligned on a 32-bit boundary, then ASSERT().
970 If StartBit is greater than 31, then ASSERT().
971 If EndBit is greater than 31, then ASSERT().
972 If EndBit is less than StartBit, then ASSERT().
974 @param Address PCI configuration register to read.
975 @param StartBit The ordinal of the least significant bit in the bit field.
977 @param EndBit The ordinal of the most significant bit in the bit field.
980 @return The value of the bit field read from the PCI configuration register.
985 PciExpressBitFieldRead32 (
991 ASSERT_INVALID_PCI_ADDRESS (Address
);
992 return MmioBitFieldRead32 (
993 (UINTN
) GetPciExpressBaseAddress () + Address
,
1000 Writes a bit field to a PCI configuration register.
1002 Writes Value to the bit field of the PCI configuration register. The bit
1003 field is specified by the StartBit and the EndBit. All other bits in the
1004 destination PCI configuration register are preserved. The new value of the
1005 32-bit register is returned.
1007 If Address > 0x0FFFFFFF, then ASSERT().
1008 If Address is not aligned on a 32-bit boundary, then ASSERT().
1009 If StartBit is greater than 31, then ASSERT().
1010 If EndBit is greater than 31, then ASSERT().
1011 If EndBit is less than StartBit, then ASSERT().
1013 @param Address PCI configuration register to write.
1014 @param StartBit The ordinal of the least significant bit in the bit field.
1016 @param EndBit The ordinal of the most significant bit in the bit field.
1018 @param Value New value of the bit field.
1020 @return The value written back to the PCI configuration register.
1025 PciExpressBitFieldWrite32 (
1032 ASSERT_INVALID_PCI_ADDRESS (Address
);
1033 return MmioBitFieldWrite32 (
1034 (UINTN
) GetPciExpressBaseAddress () + Address
,
1042 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1043 writes the result back to the bit field in the 32-bit port.
1045 Reads the 32-bit PCI configuration register specified by Address, performs a
1046 bitwise inclusive OR between the read result and the value specified by
1047 OrData, and writes the result to the 32-bit PCI configuration register
1048 specified by Address. The value written to the PCI configuration register is
1049 returned. This function must guarantee that all PCI read and write operations
1050 are serialized. Extra left bits in OrData are stripped.
1052 If Address > 0x0FFFFFFF, then ASSERT().
1053 If Address is not aligned on a 32-bit boundary, then ASSERT().
1054 If StartBit is greater than 31, then ASSERT().
1055 If EndBit is greater than 31, then ASSERT().
1056 If EndBit is less than StartBit, then ASSERT().
1058 @param Address PCI configuration register to write.
1059 @param StartBit The ordinal of the least significant bit in the bit field.
1061 @param EndBit The ordinal of the most significant bit in the bit field.
1063 @param OrData The value to OR with the PCI configuration register.
1065 @return The value written back to the PCI configuration register.
1070 PciExpressBitFieldOr32 (
1077 ASSERT_INVALID_PCI_ADDRESS (Address
);
1078 return MmioBitFieldOr32 (
1079 (UINTN
) GetPciExpressBaseAddress () + Address
,
1087 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1088 AND, and writes the result back to the bit field in the 32-bit register.
1090 Reads the 32-bit PCI configuration register specified by Address, performs a
1091 bitwise AND between the read result and the value specified by AndData, and
1092 writes the result to the 32-bit PCI configuration register specified by
1093 Address. The value written to the PCI configuration register is returned.
1094 This function must guarantee that all PCI read and write operations are
1095 serialized. Extra left bits in AndData are stripped.
1097 If Address > 0x0FFFFFFF, then ASSERT().
1098 If Address is not aligned on a 32-bit boundary, then ASSERT().
1099 If StartBit is greater than 31, then ASSERT().
1100 If EndBit is greater than 31, then ASSERT().
1101 If EndBit is less than StartBit, then ASSERT().
1103 @param Address PCI configuration register to write.
1104 @param StartBit The ordinal of the least significant bit in the bit field.
1106 @param EndBit The ordinal of the most significant bit in the bit field.
1108 @param AndData The value to AND with the PCI configuration register.
1110 @return The value written back to the PCI configuration register.
1115 PciExpressBitFieldAnd32 (
1122 ASSERT_INVALID_PCI_ADDRESS (Address
);
1123 return MmioBitFieldAnd32 (
1124 (UINTN
) GetPciExpressBaseAddress () + Address
,
1132 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1133 bitwise inclusive OR, and writes the result back to the bit field in the
1136 Reads the 32-bit PCI configuration register specified by Address, performs a
1137 bitwise AND followed by a bitwise inclusive OR between the read result and
1138 the value specified by AndData, and writes the result to the 32-bit PCI
1139 configuration register specified by Address. The value written to the PCI
1140 configuration register is returned. This function must guarantee that all PCI
1141 read and write operations are serialized. Extra left bits in both AndData and
1142 OrData are stripped.
1144 If Address > 0x0FFFFFFF, then ASSERT().
1145 If Address is not aligned on a 32-bit boundary, then ASSERT().
1146 If StartBit is greater than 31, then ASSERT().
1147 If EndBit is greater than 31, then ASSERT().
1148 If EndBit is less than StartBit, then ASSERT().
1150 @param Address PCI configuration register to write.
1151 @param StartBit The ordinal of the least significant bit in the bit field.
1153 @param EndBit The ordinal of the most significant bit in the bit field.
1155 @param AndData The value to AND with the PCI configuration register.
1156 @param OrData The value to OR with the result of the AND operation.
1158 @return The value written back to the PCI configuration register.
1163 PciExpressBitFieldAndThenOr32 (
1171 ASSERT_INVALID_PCI_ADDRESS (Address
);
1172 return MmioBitFieldAndThenOr32 (
1173 (UINTN
) GetPciExpressBaseAddress () + Address
,
1182 Reads a range of PCI configuration registers into a caller supplied buffer.
1184 Reads the range of PCI configuration registers specified by StartAddress and
1185 Size into the buffer specified by Buffer. This function only allows the PCI
1186 configuration registers from a single PCI function to be read. Size is
1187 returned. When possible 32-bit PCI configuration read cycles are used to read
1188 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1189 and 16-bit PCI configuration read cycles may be used at the beginning and the
1192 If StartAddress > 0x0FFFFFFF, then ASSERT().
1193 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1194 If Size > 0 and Buffer is NULL, then ASSERT().
1196 @param StartAddress Starting address that encodes the PCI Bus, Device,
1197 Function and Register.
1198 @param Size Size in bytes of the transfer.
1199 @param Buffer Pointer to a buffer receiving the data read.
1206 PciExpressReadBuffer (
1207 IN UINTN StartAddress
,
1214 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1215 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1221 ASSERT (Buffer
!= NULL
);
1224 // Save Size for return
1228 if ((StartAddress
& 1) != 0) {
1230 // Read a byte if StartAddress is byte aligned
1232 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1233 StartAddress
+= sizeof (UINT8
);
1234 Size
-= sizeof (UINT8
);
1235 Buffer
= (UINT8
*)Buffer
+ 1;
1238 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1240 // Read a word if StartAddress is word aligned
1242 *(volatile UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1243 StartAddress
+= sizeof (UINT16
);
1244 Size
-= sizeof (UINT16
);
1245 Buffer
= (UINT16
*)Buffer
+ 1;
1248 while (Size
>= sizeof (UINT32
)) {
1250 // Read as many double words as possible
1252 *(volatile UINT32
*)Buffer
= PciExpressRead32 (StartAddress
);
1253 StartAddress
+= sizeof (UINT32
);
1254 Size
-= sizeof (UINT32
);
1255 Buffer
= (UINT32
*)Buffer
+ 1;
1258 if (Size
>= sizeof (UINT16
)) {
1260 // Read the last remaining word if exist
1262 *(volatile UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1263 StartAddress
+= sizeof (UINT16
);
1264 Size
-= sizeof (UINT16
);
1265 Buffer
= (UINT16
*)Buffer
+ 1;
1268 if (Size
>= sizeof (UINT8
)) {
1270 // Read the last remaining byte if exist
1272 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1279 Copies the data in a caller supplied buffer to a specified range of PCI
1280 configuration space.
1282 Writes the range of PCI configuration registers specified by StartAddress and
1283 Size from the buffer specified by Buffer. This function only allows the PCI
1284 configuration registers from a single PCI function to be written. Size is
1285 returned. When possible 32-bit PCI configuration write cycles are used to
1286 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1287 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1288 and the end of the range.
1290 If StartAddress > 0x0FFFFFFF, then ASSERT().
1291 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1292 If Size > 0 and Buffer is NULL, then ASSERT().
1294 @param StartAddress Starting address that encodes the PCI Bus, Device,
1295 Function and Register.
1296 @param Size Size in bytes of the transfer.
1297 @param Buffer Pointer to a buffer containing the data to write.
1304 PciExpressWriteBuffer (
1305 IN UINTN StartAddress
,
1312 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1313 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1319 ASSERT (Buffer
!= NULL
);
1322 // Save Size for return
1326 if ((StartAddress
& 1) != 0) {
1328 // Write a byte if StartAddress is byte aligned
1330 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1331 StartAddress
+= sizeof (UINT8
);
1332 Size
-= sizeof (UINT8
);
1333 Buffer
= (UINT8
*)Buffer
+ 1;
1336 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1338 // Write a word if StartAddress is word aligned
1340 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1341 StartAddress
+= sizeof (UINT16
);
1342 Size
-= sizeof (UINT16
);
1343 Buffer
= (UINT16
*)Buffer
+ 1;
1346 while (Size
>= sizeof (UINT32
)) {
1348 // Write as many double words as possible
1350 PciExpressWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1351 StartAddress
+= sizeof (UINT32
);
1352 Size
-= sizeof (UINT32
);
1353 Buffer
= (UINT32
*)Buffer
+ 1;
1356 if (Size
>= sizeof (UINT16
)) {
1358 // Write the last remaining word if exist
1360 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1361 StartAddress
+= sizeof (UINT16
);
1362 Size
-= sizeof (UINT16
);
1363 Buffer
= (UINT16
*)Buffer
+ 1;
1366 if (Size
>= sizeof (UINT8
)) {
1368 // Write the last remaining byte if exist
1370 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);