MdePkg/Library/BasePciLibPciExpress/PciLib.c

   1 /** @file
   2   PCI Library using PC Express access.
   3
   4   Copyright (c) 2006, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13   Module Name:  PciLib.c
  14
  15 **/
  16
  17 //
  18 // Include common header file for this module.
  19 //
  20 #include "CommonHeader.h"
  21
  22 /**
  23   Reads an 8-bit PCI configuration register.
  24
  25   Reads and returns the 8-bit PCI configuration register specified by Address.
  26   This function must guarantee that all PCI read and write operations are
  27   serialized.
  28
  29   If Address > 0x0FFFFFFF, then ASSERT().
  30
  31   @param  Address Address that encodes the PCI Bus, Device, Function and
  32                   Register.
  33
  34   @return The read value from the PCI configuration register.
  35
  36 **/
  37 UINT8
  38 EFIAPI
  39 PciRead8 (
  40   IN      UINTN                     Address
  41   )
  42 {
  43   return PciExpressRead8 (Address);
  44 }
  45
  46 /**
  47   Writes an 8-bit PCI configuration register.
  48
  49   Writes the 8-bit PCI configuration register specified by Address with the
  50   value specified by Value. Value is returned. This function must guarantee
  51   that all PCI read and write operations are serialized.
  52
  53   If Address > 0x0FFFFFFF, then ASSERT().
  54
  55   @param  Address Address that encodes the PCI Bus, Device, Function and
  56                   Register.
  57   @param  Value   The value to write.
  58
  59   @return The value written to the PCI configuration register.
  60
  61 **/
  62 UINT8
  63 EFIAPI
  64 PciWrite8 (
  65   IN      UINTN                     Address,
  66   IN      UINT8                     Data
  67   )
  68 {
  69   return PciExpressWrite8 (Address, Data);
  70 }
  71
  72 /**
  73   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
  74   an 8-bit value.
  75
  76   Reads the 8-bit PCI configuration register specified by Address, performs a
  77   bitwise inclusive OR between the read result and the value specified by
  78   OrData, and writes the result to the 8-bit PCI configuration register
  79   specified by Address. The value written to the PCI configuration register is
  80   returned. This function must guarantee that all PCI read and write operations
  81   are serialized.
  82
  83   If Address > 0x0FFFFFFF, then ASSERT().
  84
  85   @param  Address Address that encodes the PCI Bus, Device, Function and
  86                   Register.
  87   @param  OrData  The value to OR with the PCI configuration register.
  88
  89   @return The value written back to the PCI configuration register.
  90
  91 **/
  92 UINT8
  93 EFIAPI
  94 PciOr8 (
  95   IN      UINTN                     Address,
  96   IN      UINT8                     OrData
  97   )
  98 {
  99   return PciExpressOr8 (Address, OrData);
 100 }
 101
 102 /**
 103   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 104   value.
 105
 106   Reads the 8-bit PCI configuration register specified by Address, performs a
 107   bitwise AND between the read result and the value specified by AndData, and
 108   writes the result to the 8-bit PCI configuration register specified by
 109   Address. The value written to the PCI configuration register is returned.
 110   This function must guarantee that all PCI read and write operations are
 111   serialized.
 112
 113   If Address > 0x0FFFFFFF, then ASSERT().
 114
 115   @param  Address Address that encodes the PCI Bus, Device, Function and
 116                   Register.
 117   @param  AndData The value to AND with the PCI configuration register.
 118
 119   @return The value written back to the PCI configuration register.
 120
 121 **/
 122 UINT8
 123 EFIAPI
 124 PciAnd8 (
 125   IN      UINTN                     Address,
 126   IN      UINT8                     AndData
 127   )
 128 {
 129   return PciExpressAnd8 (Address, AndData);
 130 }
 131
 132 /**
 133   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 134   value, followed a  bitwise inclusive OR with another 8-bit value.
 135
 136   Reads the 8-bit PCI configuration register specified by Address, performs a
 137   bitwise AND between the read result and the value specified by AndData,
 138   performs a bitwise inclusive OR between the result of the AND operation and
 139   the value specified by OrData, and writes the result to the 8-bit PCI
 140   configuration register specified by Address. The value written to the PCI
 141   configuration register is returned. This function must guarantee that all PCI
 142   read and write operations are serialized.
 143
 144   If Address > 0x0FFFFFFF, then ASSERT().
 145
 146   @param  Address Address that encodes the PCI Bus, Device, Function and
 147                   Register.
 148   @param  AndData The value to AND with the PCI configuration register.
 149   @param  OrData  The value to OR with the result of the AND operation.
 150
 151   @return The value written back to the PCI configuration register.
 152
 153 **/
 154 UINT8
 155 EFIAPI
 156 PciAndThenOr8 (
 157   IN      UINTN                     Address,
 158   IN      UINT8                     AndData,
 159   IN      UINT8                     OrData
 160   )
 161 {
 162   return PciExpressAndThenOr8 (Address, AndData, OrData);
 163 }
 164
 165 /**
 166   Reads a bit field of a PCI configuration register.
 167
 168   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 169   specified by the StartBit and the EndBit. The value of the bit field is
 170   returned.
 171
 172   If Address > 0x0FFFFFFF, then ASSERT().
 173   If StartBit is greater than 7, then ASSERT().
 174   If EndBit is greater than 7, then ASSERT().
 175   If EndBit is less than StartBit, then ASSERT().
 176
 177   @param  Address   PCI configuration register to read.
 178   @param  StartBit  The ordinal of the least significant bit in the bit field.
 179                     Range 0..7.
 180   @param  EndBit    The ordinal of the most significant bit in the bit field.
 181                     Range 0..7.
 182
 183   @return The value of the bit field read from the PCI configuration register.
 184
 185 **/
 186 UINT8
 187 EFIAPI
 188 PciBitFieldRead8 (
 189   IN      UINTN                     Address,
 190   IN      UINTN                     StartBit,
 191   IN      UINTN                     EndBit
 192   )
 193 {
 194   return PciExpressBitFieldRead8 (Address, StartBit, EndBit);
 195 }
 196
 197 /**
 198   Writes a bit field to a PCI configuration register.
 199
 200   Writes Value to the bit field of the PCI configuration register. The bit
 201   field is specified by the StartBit and the EndBit. All other bits in the
 202   destination PCI configuration register are preserved. The new value of the
 203   8-bit register is returned.
 204
 205   If Address > 0x0FFFFFFF, then ASSERT().
 206   If StartBit is greater than 7, then ASSERT().
 207   If EndBit is greater than 7, then ASSERT().
 208   If EndBit is less than StartBit, then ASSERT().
 209
 210   @param  Address   PCI configuration register to write.
 211   @param  StartBit  The ordinal of the least significant bit in the bit field.
 212                     Range 0..7.
 213   @param  EndBit    The ordinal of the most significant bit in the bit field.
 214                     Range 0..7.
 215   @param  Value     New value of the bit field.
 216
 217   @return The value written back to the PCI configuration register.
 218
 219 **/
 220 UINT8
 221 EFIAPI
 222 PciBitFieldWrite8 (
 223   IN      UINTN                     Address,
 224   IN      UINTN                     StartBit,
 225   IN      UINTN                     EndBit,
 226   IN      UINT8                     Value
 227   )
 228 {
 229   return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);
 230 }
 231
 232 /**
 233   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 234   writes the result back to the bit field in the 8-bit port.
 235
 236   Reads the 8-bit PCI configuration register specified by Address, performs a
 237   bitwise inclusive OR between the read result and the value specified by
 238   OrData, and writes the result to the 8-bit PCI configuration register
 239   specified by Address. The value written to the PCI configuration register is
 240   returned. This function must guarantee that all PCI read and write operations
 241   are serialized. Extra left bits in OrData are stripped.
 242
 243   If Address > 0x0FFFFFFF, then ASSERT().
 244   If StartBit is greater than 7, then ASSERT().
 245   If EndBit is greater than 7, then ASSERT().
 246   If EndBit is less than StartBit, then ASSERT().
 247
 248   @param  Address   PCI configuration register to write.
 249   @param  StartBit  The ordinal of the least significant bit in the bit field.
 250                     Range 0..7.
 251   @param  EndBit    The ordinal of the most significant bit in the bit field.
 252                     Range 0..7.
 253   @param  OrData    The value to OR with the PCI configuration register.
 254
 255   @return The value written back to the PCI configuration register.
 256
 257 **/
 258 UINT8
 259 EFIAPI
 260 PciBitFieldOr8 (
 261   IN      UINTN                     Address,
 262   IN      UINTN                     StartBit,
 263   IN      UINTN                     EndBit,
 264   IN      UINT8                     OrData
 265   )
 266 {
 267   return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);
 268 }
 269
 270 /**
 271   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 272   AND, and writes the result back to the bit field in the 8-bit register.
 273
 274   Reads the 8-bit PCI configuration register specified by Address, performs a
 275   bitwise AND between the read result and the value specified by AndData, and
 276   writes the result to the 8-bit PCI configuration register specified by
 277   Address. The value written to the PCI configuration register is returned.
 278   This function must guarantee that all PCI read and write operations are
 279   serialized. Extra left bits in AndData are stripped.
 280
 281   If Address > 0x0FFFFFFF, then ASSERT().
 282   If StartBit is greater than 7, then ASSERT().
 283   If EndBit is greater than 7, then ASSERT().
 284   If EndBit is less than StartBit, then ASSERT().
 285
 286   @param  Address   PCI configuration register to write.
 287   @param  StartBit  The ordinal of the least significant bit in the bit field.
 288                     Range 0..7.
 289   @param  EndBit    The ordinal of the most significant bit in the bit field.
 290                     Range 0..7.
 291   @param  AndData   The value to AND with the PCI configuration register.
 292
 293   @return The value written back to the PCI configuration register.
 294
 295 **/
 296 UINT8
 297 EFIAPI
 298 PciBitFieldAnd8 (
 299   IN      UINTN                     Address,
 300   IN      UINTN                     StartBit,
 301   IN      UINTN                     EndBit,
 302   IN      UINT8                     AndData
 303   )
 304 {
 305   return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);
 306 }
 307
 308 /**
 309   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 310   bitwise inclusive OR, and writes the result back to the bit field in the
 311   8-bit port.
 312
 313   Reads the 8-bit PCI configuration register specified by Address, performs a
 314   bitwise AND followed by a bitwise inclusive OR between the read result and
 315   the value specified by AndData, and writes the result to the 8-bit PCI
 316   configuration register specified by Address. The value written to the PCI
 317   configuration register is returned. This function must guarantee that all PCI
 318   read and write operations are serialized. Extra left bits in both AndData and
 319   OrData are stripped.
 320
 321   If Address > 0x0FFFFFFF, then ASSERT().
 322   If StartBit is greater than 7, then ASSERT().
 323   If EndBit is greater than 7, then ASSERT().
 324   If EndBit is less than StartBit, then ASSERT().
 325
 326   @param  Address   PCI configuration register to write.
 327   @param  StartBit  The ordinal of the least significant bit in the bit field.
 328                     Range 0..7.
 329   @param  EndBit    The ordinal of the most significant bit in the bit field.
 330                     Range 0..7.
 331   @param  AndData   The value to AND with the PCI configuration register.
 332   @param  OrData    The value to OR with the result of the AND operation.
 333
 334   @return The value written back to the PCI configuration register.
 335
 336 **/
 337 UINT8
 338 EFIAPI
 339 PciBitFieldAndThenOr8 (
 340   IN      UINTN                     Address,
 341   IN      UINTN                     StartBit,
 342   IN      UINTN                     EndBit,
 343   IN      UINT8                     AndData,
 344   IN      UINT8                     OrData
 345   )
 346 {
 347   return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);
 348 }
 349
 350 /**
 351   Reads a 16-bit PCI configuration register.
 352
 353   Reads and returns the 16-bit PCI configuration register specified by Address.
 354   This function must guarantee that all PCI read and write operations are
 355   serialized.
 356
 357   If Address > 0x0FFFFFFF, then ASSERT().
 358
 359   @param  Address Address that encodes the PCI Bus, Device, Function and
 360                   Register.
 361
 362   @return The read value from the PCI configuration register.
 363
 364 **/
 365 UINT16
 366 EFIAPI
 367 PciRead16 (
 368   IN      UINTN                     Address
 369   )
 370 {
 371   return PciExpressRead16 (Address);
 372 }
 373
 374 /**
 375   Writes a 16-bit PCI configuration register.
 376
 377   Writes the 16-bit PCI configuration register specified by Address with the
 378   value specified by Value. Value is returned. This function must guarantee
 379   that all PCI read and write operations are serialized.
 380
 381   If Address > 0x0FFFFFFF, then ASSERT().
 382
 383   @param  Address Address that encodes the PCI Bus, Device, Function and
 384                   Register.
 385   @param  Value   The value to write.
 386
 387   @return The value written to the PCI configuration register.
 388
 389 **/
 390 UINT16
 391 EFIAPI
 392 PciWrite16 (
 393   IN      UINTN                     Address,
 394   IN      UINT16                    Data
 395   )
 396 {
 397   return PciExpressWrite16 (Address, Data);
 398 }
 399
 400 /**
 401   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 402   a 16-bit value.
 403
 404   Reads the 16-bit PCI configuration register specified by Address, performs a
 405   bitwise inclusive OR between the read result and the value specified by
 406   OrData, and writes the result to the 16-bit PCI configuration register
 407   specified by Address. The value written to the PCI configuration register is
 408   returned. This function must guarantee that all PCI read and write operations
 409   are serialized.
 410
 411   If Address > 0x0FFFFFFF, then ASSERT().
 412
 413   @param  Address Address that encodes the PCI Bus, Device, Function and
 414                   Register.
 415   @param  OrData  The value to OR with the PCI configuration register.
 416
 417   @return The value written back to the PCI configuration register.
 418
 419 **/
 420 UINT16
 421 EFIAPI
 422 PciOr16 (
 423   IN      UINTN                     Address,
 424   IN      UINT16                    OrData
 425   )
 426 {
 427   return PciExpressOr16 (Address, OrData);
 428 }
 429
 430 /**
 431   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 432   value.
 433
 434   Reads the 16-bit PCI configuration register specified by Address, performs a
 435   bitwise AND between the read result and the value specified by AndData, and
 436   writes the result to the 16-bit PCI configuration register specified by
 437   Address. The value written to the PCI configuration register is returned.
 438   This function must guarantee that all PCI read and write operations are
 439   serialized.
 440
 441   If Address > 0x0FFFFFFF, then ASSERT().
 442
 443   @param  Address Address that encodes the PCI Bus, Device, Function and
 444                   Register.
 445   @param  AndData The value to AND with the PCI configuration register.
 446
 447   @return The value written back to the PCI configuration register.
 448
 449 **/
 450 UINT16
 451 EFIAPI
 452 PciAnd16 (
 453   IN      UINTN                     Address,
 454   IN      UINT16                    AndData
 455   )
 456 {
 457   return PciExpressAnd16 (Address, AndData);
 458 }
 459
 460 /**
 461   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 462   value, followed a  bitwise inclusive OR with another 16-bit value.
 463
 464   Reads the 16-bit PCI configuration register specified by Address, performs a
 465   bitwise AND between the read result and the value specified by AndData,
 466   performs a bitwise inclusive OR between the result of the AND operation and
 467   the value specified by OrData, and writes the result to the 16-bit PCI
 468   configuration register specified by Address. The value written to the PCI
 469   configuration register is returned. This function must guarantee that all PCI
 470   read and write operations are serialized.
 471
 472   If Address > 0x0FFFFFFF, then ASSERT().
 473
 474   @param  Address Address that encodes the PCI Bus, Device, Function and
 475                   Register.
 476   @param  AndData The value to AND with the PCI configuration register.
 477   @param  OrData  The value to OR with the result of the AND operation.
 478
 479   @return The value written back to the PCI configuration register.
 480
 481 **/
 482 UINT16
 483 EFIAPI
 484 PciAndThenOr16 (
 485   IN      UINTN                     Address,
 486   IN      UINT16                    AndData,
 487   IN      UINT16                    OrData
 488   )
 489 {
 490   return PciExpressAndThenOr16 (Address, AndData, OrData);
 491 }
 492
 493 /**
 494   Reads a bit field of a PCI configuration register.
 495
 496   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 497   specified by the StartBit and the EndBit. The value of the bit field is
 498   returned.
 499
 500   If Address > 0x0FFFFFFF, then ASSERT().
 501   If StartBit is greater than 15, then ASSERT().
 502   If EndBit is greater than 15, then ASSERT().
 503   If EndBit is less than StartBit, then ASSERT().
 504
 505   @param  Address   PCI configuration register to read.
 506   @param  StartBit  The ordinal of the least significant bit in the bit field.
 507                     Range 0..15.
 508   @param  EndBit    The ordinal of the most significant bit in the bit field.
 509                     Range 0..15.
 510
 511   @return The value of the bit field read from the PCI configuration register.
 512
 513 **/
 514 UINT16
 515 EFIAPI
 516 PciBitFieldRead16 (
 517   IN      UINTN                     Address,
 518   IN      UINTN                     StartBit,
 519   IN      UINTN                     EndBit
 520   )
 521 {
 522   return PciExpressBitFieldRead16 (Address, StartBit, EndBit);
 523 }
 524
 525 /**
 526   Writes a bit field to a PCI configuration register.
 527
 528   Writes Value to the bit field of the PCI configuration register. The bit
 529   field is specified by the StartBit and the EndBit. All other bits in the
 530   destination PCI configuration register are preserved. The new value of the
 531   16-bit register is returned.
 532
 533   If Address > 0x0FFFFFFF, then ASSERT().
 534   If StartBit is greater than 15, then ASSERT().
 535   If EndBit is greater than 15, then ASSERT().
 536   If EndBit is less than StartBit, then ASSERT().
 537
 538   @param  Address   PCI configuration register to write.
 539   @param  StartBit  The ordinal of the least significant bit in the bit field.
 540                     Range 0..15.
 541   @param  EndBit    The ordinal of the most significant bit in the bit field.
 542                     Range 0..15.
 543   @param  Value     New value of the bit field.
 544
 545   @return The value written back to the PCI configuration register.
 546
 547 **/
 548 UINT16
 549 EFIAPI
 550 PciBitFieldWrite16 (
 551   IN      UINTN                     Address,
 552   IN      UINTN                     StartBit,
 553   IN      UINTN                     EndBit,
 554   IN      UINT16                    Value
 555   )
 556 {
 557   return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);
 558 }
 559
 560 /**
 561   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 562   writes the result back to the bit field in the 16-bit port.
 563
 564   Reads the 16-bit PCI configuration register specified by Address, performs a
 565   bitwise inclusive OR between the read result and the value specified by
 566   OrData, and writes the result to the 16-bit PCI configuration register
 567   specified by Address. The value written to the PCI configuration register is
 568   returned. This function must guarantee that all PCI read and write operations
 569   are serialized. Extra left bits in OrData are stripped.
 570
 571   If Address > 0x0FFFFFFF, then ASSERT().
 572   If StartBit is greater than 15, then ASSERT().
 573   If EndBit is greater than 15, then ASSERT().
 574   If EndBit is less than StartBit, then ASSERT().
 575
 576   @param  Address   PCI configuration register to write.
 577   @param  StartBit  The ordinal of the least significant bit in the bit field.
 578                     Range 0..15.
 579   @param  EndBit    The ordinal of the most significant bit in the bit field.
 580                     Range 0..15.
 581   @param  OrData    The value to OR with the PCI configuration register.
 582
 583   @return The value written back to the PCI configuration register.
 584
 585 **/
 586 UINT16
 587 EFIAPI
 588 PciBitFieldOr16 (
 589   IN      UINTN                     Address,
 590   IN      UINTN                     StartBit,
 591   IN      UINTN                     EndBit,
 592   IN      UINT16                    OrData
 593   )
 594 {
 595   return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);
 596 }
 597
 598 /**
 599   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 600   AND, and writes the result back to the bit field in the 16-bit register.
 601
 602   Reads the 16-bit PCI configuration register specified by Address, performs a
 603   bitwise AND between the read result and the value specified by AndData, and
 604   writes the result to the 16-bit PCI configuration register specified by
 605   Address. The value written to the PCI configuration register is returned.
 606   This function must guarantee that all PCI read and write operations are
 607   serialized. Extra left bits in AndData are stripped.
 608
 609   If Address > 0x0FFFFFFF, then ASSERT().
 610   If StartBit is greater than 15, then ASSERT().
 611   If EndBit is greater than 15, then ASSERT().
 612   If EndBit is less than StartBit, then ASSERT().
 613
 614   @param  Address   PCI configuration register to write.
 615   @param  StartBit  The ordinal of the least significant bit in the bit field.
 616                     Range 0..15.
 617   @param  EndBit    The ordinal of the most significant bit in the bit field.
 618                     Range 0..15.
 619   @param  AndData   The value to AND with the PCI configuration register.
 620
 621   @return The value written back to the PCI configuration register.
 622
 623 **/
 624 UINT16
 625 EFIAPI
 626 PciBitFieldAnd16 (
 627   IN      UINTN                     Address,
 628   IN      UINTN                     StartBit,
 629   IN      UINTN                     EndBit,
 630   IN      UINT16                    AndData
 631   )
 632 {
 633   return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);
 634 }
 635
 636 /**
 637   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 638   bitwise inclusive OR, and writes the result back to the bit field in the
 639   16-bit port.
 640
 641   Reads the 16-bit PCI configuration register specified by Address, performs a
 642   bitwise AND followed by a bitwise inclusive OR between the read result and
 643   the value specified by AndData, and writes the result to the 16-bit PCI
 644   configuration register specified by Address. The value written to the PCI
 645   configuration register is returned. This function must guarantee that all PCI
 646   read and write operations are serialized. Extra left bits in both AndData and
 647   OrData are stripped.
 648
 649   If Address > 0x0FFFFFFF, then ASSERT().
 650   If StartBit is greater than 15, then ASSERT().
 651   If EndBit is greater than 15, then ASSERT().
 652   If EndBit is less than StartBit, then ASSERT().
 653
 654   @param  Address   PCI configuration register to write.
 655   @param  StartBit  The ordinal of the least significant bit in the bit field.
 656                     Range 0..15.
 657   @param  EndBit    The ordinal of the most significant bit in the bit field.
 658                     Range 0..15.
 659   @param  AndData   The value to AND with the PCI configuration register.
 660   @param  OrData    The value to OR with the result of the AND operation.
 661
 662   @return The value written back to the PCI configuration register.
 663
 664 **/
 665 UINT16
 666 EFIAPI
 667 PciBitFieldAndThenOr16 (
 668   IN      UINTN                     Address,
 669   IN      UINTN                     StartBit,
 670   IN      UINTN                     EndBit,
 671   IN      UINT16                    AndData,
 672   IN      UINT16                    OrData
 673   )
 674 {
 675   return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);
 676 }
 677
 678 /**
 679   Reads a 32-bit PCI configuration register.
 680
 681   Reads and returns the 32-bit PCI configuration register specified by Address.
 682   This function must guarantee that all PCI read and write operations are
 683   serialized.
 684
 685   If Address > 0x0FFFFFFF, then ASSERT().
 686
 687   @param  Address Address that encodes the PCI Bus, Device, Function and
 688                   Register.
 689
 690   @return The read value from the PCI configuration register.
 691
 692 **/
 693 UINT32
 694 EFIAPI
 695 PciRead32 (
 696   IN      UINTN                     Address
 697   )
 698 {
 699   return PciExpressRead32 (Address);
 700 }
 701
 702 /**
 703   Writes a 32-bit PCI configuration register.
 704
 705   Writes the 32-bit PCI configuration register specified by Address with the
 706   value specified by Value. Value is returned. This function must guarantee
 707   that all PCI read and write operations are serialized.
 708
 709   If Address > 0x0FFFFFFF, then ASSERT().
 710
 711   @param  Address Address that encodes the PCI Bus, Device, Function and
 712                   Register.
 713   @param  Value   The value to write.
 714
 715   @return The value written to the PCI configuration register.
 716
 717 **/
 718 UINT32
 719 EFIAPI
 720 PciWrite32 (
 721   IN      UINTN                     Address,
 722   IN      UINT32                    Data
 723   )
 724 {
 725   return PciExpressWrite32 (Address, Data);
 726 }
 727
 728 /**
 729   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 730   a 32-bit value.
 731
 732   Reads the 32-bit PCI configuration register specified by Address, performs a
 733   bitwise inclusive OR between the read result and the value specified by
 734   OrData, and writes the result to the 32-bit PCI configuration register
 735   specified by Address. The value written to the PCI configuration register is
 736   returned. This function must guarantee that all PCI read and write operations
 737   are serialized.
 738
 739   If Address > 0x0FFFFFFF, then ASSERT().
 740
 741   @param  Address Address that encodes the PCI Bus, Device, Function and
 742                   Register.
 743   @param  OrData  The value to OR with the PCI configuration register.
 744
 745   @return The value written back to the PCI configuration register.
 746
 747 **/
 748 UINT32
 749 EFIAPI
 750 PciOr32 (
 751   IN      UINTN                     Address,
 752   IN      UINT32                    OrData
 753   )
 754 {
 755   return PciExpressOr32 (Address, OrData);
 756 }
 757
 758 /**
 759   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 760   value.
 761
 762   Reads the 32-bit PCI configuration register specified by Address, performs a
 763   bitwise AND between the read result and the value specified by AndData, and
 764   writes the result to the 32-bit PCI configuration register specified by
 765   Address. The value written to the PCI configuration register is returned.
 766   This function must guarantee that all PCI read and write operations are
 767   serialized.
 768
 769   If Address > 0x0FFFFFFF, then ASSERT().
 770
 771   @param  Address Address that encodes the PCI Bus, Device, Function and
 772                   Register.
 773   @param  AndData The value to AND with the PCI configuration register.
 774
 775   @return The value written back to the PCI configuration register.
 776
 777 **/
 778 UINT32
 779 EFIAPI
 780 PciAnd32 (
 781   IN      UINTN                     Address,
 782   IN      UINT32                    AndData
 783   )
 784 {
 785   return PciExpressAnd32 (Address, AndData);
 786 }
 787
 788 /**
 789   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 790   value, followed a  bitwise inclusive OR with another 32-bit value.
 791
 792   Reads the 32-bit PCI configuration register specified by Address, performs a
 793   bitwise AND between the read result and the value specified by AndData,
 794   performs a bitwise inclusive OR between the result of the AND operation and
 795   the value specified by OrData, and writes the result to the 32-bit PCI
 796   configuration register specified by Address. The value written to the PCI
 797   configuration register is returned. This function must guarantee that all PCI
 798   read and write operations are serialized.
 799
 800   If Address > 0x0FFFFFFF, then ASSERT().
 801
 802   @param  Address Address that encodes the PCI Bus, Device, Function and
 803                   Register.
 804   @param  AndData The value to AND with the PCI configuration register.
 805   @param  OrData  The value to OR with the result of the AND operation.
 806
 807   @return The value written back to the PCI configuration register.
 808
 809 **/
 810 UINT32
 811 EFIAPI
 812 PciAndThenOr32 (
 813   IN      UINTN                     Address,
 814   IN      UINT32                    AndData,
 815   IN      UINT32                    OrData
 816   )
 817 {
 818   return PciExpressAndThenOr32 (Address, AndData, OrData);
 819 }
 820
 821 /**
 822   Reads a bit field of a PCI configuration register.
 823
 824   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 825   specified by the StartBit and the EndBit. The value of the bit field is
 826   returned.
 827
 828   If Address > 0x0FFFFFFF, then ASSERT().
 829   If StartBit is greater than 31, then ASSERT().
 830   If EndBit is greater than 31, then ASSERT().
 831   If EndBit is less than StartBit, then ASSERT().
 832
 833   @param  Address   PCI configuration register to read.
 834   @param  StartBit  The ordinal of the least significant bit in the bit field.
 835                     Range 0..31.
 836   @param  EndBit    The ordinal of the most significant bit in the bit field.
 837                     Range 0..31.
 838
 839   @return The value of the bit field read from the PCI configuration register.
 840
 841 **/
 842 UINT32
 843 EFIAPI
 844 PciBitFieldRead32 (
 845   IN      UINTN                     Address,
 846   IN      UINTN                     StartBit,
 847   IN      UINTN                     EndBit
 848   )
 849 {
 850   return PciExpressBitFieldRead32 (Address, StartBit, EndBit);
 851 }
 852
 853 /**
 854   Writes a bit field to a PCI configuration register.
 855
 856   Writes Value to the bit field of the PCI configuration register. The bit
 857   field is specified by the StartBit and the EndBit. All other bits in the
 858   destination PCI configuration register are preserved. The new value of the
 859   32-bit register is returned.
 860
 861   If Address > 0x0FFFFFFF, then ASSERT().
 862   If StartBit is greater than 31, then ASSERT().
 863   If EndBit is greater than 31, then ASSERT().
 864   If EndBit is less than StartBit, then ASSERT().
 865
 866   @param  Address   PCI configuration register to write.
 867   @param  StartBit  The ordinal of the least significant bit in the bit field.
 868                     Range 0..31.
 869   @param  EndBit    The ordinal of the most significant bit in the bit field.
 870                     Range 0..31.
 871   @param  Value     New value of the bit field.
 872
 873   @return The value written back to the PCI configuration register.
 874
 875 **/
 876 UINT32
 877 EFIAPI
 878 PciBitFieldWrite32 (
 879   IN      UINTN                     Address,
 880   IN      UINTN                     StartBit,
 881   IN      UINTN                     EndBit,
 882   IN      UINT32                    Value
 883   )
 884 {
 885   return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);
 886 }
 887
 888 /**
 889   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 890   writes the result back to the bit field in the 32-bit port.
 891
 892   Reads the 32-bit PCI configuration register specified by Address, performs a
 893   bitwise inclusive OR between the read result and the value specified by
 894   OrData, and writes the result to the 32-bit PCI configuration register
 895   specified by Address. The value written to the PCI configuration register is
 896   returned. This function must guarantee that all PCI read and write operations
 897   are serialized. Extra left bits in OrData are stripped.
 898
 899   If Address > 0x0FFFFFFF, then ASSERT().
 900   If StartBit is greater than 31, then ASSERT().
 901   If EndBit is greater than 31, then ASSERT().
 902   If EndBit is less than StartBit, then ASSERT().
 903
 904   @param  Address   PCI configuration register to write.
 905   @param  StartBit  The ordinal of the least significant bit in the bit field.
 906                     Range 0..31.
 907   @param  EndBit    The ordinal of the most significant bit in the bit field.
 908                     Range 0..31.
 909   @param  OrData    The value to OR with the PCI configuration register.
 910
 911   @return The value written back to the PCI configuration register.
 912
 913 **/
 914 UINT32
 915 EFIAPI
 916 PciBitFieldOr32 (
 917   IN      UINTN                     Address,
 918   IN      UINTN                     StartBit,
 919   IN      UINTN                     EndBit,
 920   IN      UINT32                    OrData
 921   )
 922 {
 923   return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);
 924 }
 925
 926 /**
 927   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 928   AND, and writes the result back to the bit field in the 32-bit register.
 929
 930   Reads the 32-bit PCI configuration register specified by Address, performs a
 931   bitwise AND between the read result and the value specified by AndData, and
 932   writes the result to the 32-bit PCI configuration register specified by
 933   Address. The value written to the PCI configuration register is returned.
 934   This function must guarantee that all PCI read and write operations are
 935   serialized. Extra left bits in AndData are stripped.
 936
 937   If Address > 0x0FFFFFFF, then ASSERT().
 938   If StartBit is greater than 31, then ASSERT().
 939   If EndBit is greater than 31, then ASSERT().
 940   If EndBit is less than StartBit, then ASSERT().
 941
 942   @param  Address   PCI configuration register to write.
 943   @param  StartBit  The ordinal of the least significant bit in the bit field.
 944                     Range 0..31.
 945   @param  EndBit    The ordinal of the most significant bit in the bit field.
 946                     Range 0..31.
 947   @param  AndData   The value to AND with the PCI configuration register.
 948
 949   @return The value written back to the PCI configuration register.
 950
 951 **/
 952 UINT32
 953 EFIAPI
 954 PciBitFieldAnd32 (
 955   IN      UINTN                     Address,
 956   IN      UINTN                     StartBit,
 957   IN      UINTN                     EndBit,
 958   IN      UINT32                    AndData
 959   )
 960 {
 961   return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);
 962 }
 963
 964 /**
 965   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 966   bitwise inclusive OR, and writes the result back to the bit field in the
 967   32-bit port.
 968
 969   Reads the 32-bit PCI configuration register specified by Address, performs a
 970   bitwise AND followed by a bitwise inclusive OR between the read result and
 971   the value specified by AndData, and writes the result to the 32-bit PCI
 972   configuration register specified by Address. The value written to the PCI
 973   configuration register is returned. This function must guarantee that all PCI
 974   read and write operations are serialized. Extra left bits in both AndData and
 975   OrData are stripped.
 976
 977   If Address > 0x0FFFFFFF, then ASSERT().
 978   If StartBit is greater than 31, then ASSERT().
 979   If EndBit is greater than 31, then ASSERT().
 980   If EndBit is less than StartBit, then ASSERT().
 981
 982   @param  Address   PCI configuration register to write.
 983   @param  StartBit  The ordinal of the least significant bit in the bit field.
 984                     Range 0..31.
 985   @param  EndBit    The ordinal of the most significant bit in the bit field.
 986                     Range 0..31.
 987   @param  AndData   The value to AND with the PCI configuration register.
 988   @param  OrData    The value to OR with the result of the AND operation.
 989
 990   @return The value written back to the PCI configuration register.
 991
 992 **/
 993 UINT32
 994 EFIAPI
 995 PciBitFieldAndThenOr32 (
 996   IN      UINTN                     Address,
 997   IN      UINTN                     StartBit,
 998   IN      UINTN                     EndBit,
 999   IN      UINT32                    AndData,
1000   IN      UINT32                    OrData
1001   )
1002 {
1003   return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);
1004 }
1005
1006 /**
1007   Reads a range of PCI configuration registers into a caller supplied buffer.
1008
1009   Reads the range of PCI configuration registers specified by StartAddress and
1010   Size into the buffer specified by Buffer. This function only allows the PCI
1011   configuration registers from a single PCI function to be read. Size is
1012   returned. When possible 32-bit PCI configuration read cycles are used to read
1013   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1014   and 16-bit PCI configuration read cycles may be used at the beginning and the
1015   end of the range.
1016
1017   If StartAddress > 0x0FFFFFFF, then ASSERT().
1018   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1019   If Size > 0 and Buffer is NULL, then ASSERT().
1020
1021   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1022                         Function and Register.
1023   @param  Size          Size in bytes of the transfer.
1024   @param  Buffer        Pointer to a buffer receiving the data read.
1025
1026   @return Size
1027
1028 **/
1029 UINTN
1030 EFIAPI
1031 PciReadBuffer (
1032   IN      UINTN                     StartAddress,
1033   IN      UINTN                     Size,
1034   OUT     VOID                      *Buffer
1035   )
1036 {
1037   return PciExpressReadBuffer (StartAddress, Size, Buffer);
1038 }
1039
1040 /**
1041   Copies the data in a caller supplied buffer to a specified range of PCI
1042   configuration space.
1043
1044   Writes the range of PCI configuration registers specified by StartAddress and
1045   Size from the buffer specified by Buffer. This function only allows the PCI
1046   configuration registers from a single PCI function to be written. Size is
1047   returned. When possible 32-bit PCI configuration write cycles are used to
1048   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1049   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1050   and the end of the range.
1051
1052   If StartAddress > 0x0FFFFFFF, then ASSERT().
1053   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1054   If Size > 0 and Buffer is NULL, then ASSERT().
1055
1056   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1057                         Function and Register.
1058   @param  Size          Size in bytes of the transfer.
1059   @param  Buffer        Pointer to a buffer containing the data to write.
1060
1061   @return Size
1062
1063 **/
1064 UINTN
1065 EFIAPI
1066 PciWriteBuffer (
1067   IN      UINTN                     StartAddress,
1068   IN      UINTN                     Size,
1069   IN      VOID                      *Buffer
1070   )
1071 {
1072   return PciExpressWriteBuffer (StartAddress, Size, Buffer);
1073 }