MdePkg/Library/BasePciLibPciExpress/PciLib.c

   1 /** @file
   2   PCI Library using PC Express access.
   3
   4   Copyright (c) 2006, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13   Module Name:  PciLib.c
  14
  15 **/
  16
  17 /**
  18   Reads an 8-bit PCI configuration register.
  19
  20   Reads and returns the 8-bit PCI configuration register specified by Address.
  21   This function must guarantee that all PCI read and write operations are
  22   serialized.
  23
  24   If Address > 0x0FFFFFFF, then ASSERT().
  25
  26   @param  Address Address that encodes the PCI Bus, Device, Function and
  27                   Register.
  28
  29   @return The read value from the PCI configuration register.
  30
  31 **/
  32 UINT8
  33 EFIAPI
  34 PciRead8 (
  35   IN      UINTN                     Address
  36   )
  37 {
  38   return PciExpressRead8 (Address);
  39 }
  40
  41 /**
  42   Writes an 8-bit PCI configuration register.
  43
  44   Writes the 8-bit PCI configuration register specified by Address with the
  45   value specified by Value. Value is returned. This function must guarantee
  46   that all PCI read and write operations are serialized.
  47
  48   If Address > 0x0FFFFFFF, then ASSERT().
  49
  50   @param  Address Address that encodes the PCI Bus, Device, Function and
  51                   Register.
  52   @param  Value   The value to write.
  53
  54   @return The value written to the PCI configuration register.
  55
  56 **/
  57 UINT8
  58 EFIAPI
  59 PciWrite8 (
  60   IN      UINTN                     Address,
  61   IN      UINT8                     Data
  62   )
  63 {
  64   return PciExpressWrite8 (Address, Data);
  65 }
  66
  67 /**
  68   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
  69   an 8-bit value.
  70
  71   Reads the 8-bit PCI configuration register specified by Address, performs a
  72   bitwise inclusive OR between the read result and the value specified by
  73   OrData, and writes the result to the 8-bit PCI configuration register
  74   specified by Address. The value written to the PCI configuration register is
  75   returned. This function must guarantee that all PCI read and write operations
  76   are serialized.
  77
  78   If Address > 0x0FFFFFFF, then ASSERT().
  79
  80   @param  Address Address that encodes the PCI Bus, Device, Function and
  81                   Register.
  82   @param  OrData  The value to OR with the PCI configuration register.
  83
  84   @return The value written back to the PCI configuration register.
  85
  86 **/
  87 UINT8
  88 EFIAPI
  89 PciOr8 (
  90   IN      UINTN                     Address,
  91   IN      UINT8                     OrData
  92   )
  93 {
  94   return PciExpressOr8 (Address, OrData);
  95 }
  96
  97 /**
  98   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
  99   value.
 100
 101   Reads the 8-bit PCI configuration register specified by Address, performs a
 102   bitwise AND between the read result and the value specified by AndData, and
 103   writes the result to the 8-bit PCI configuration register specified by
 104   Address. The value written to the PCI configuration register is returned.
 105   This function must guarantee that all PCI read and write operations are
 106   serialized.
 107
 108   If Address > 0x0FFFFFFF, then ASSERT().
 109
 110   @param  Address Address that encodes the PCI Bus, Device, Function and
 111                   Register.
 112   @param  AndData The value to AND with the PCI configuration register.
 113
 114   @return The value written back to the PCI configuration register.
 115
 116 **/
 117 UINT8
 118 EFIAPI
 119 PciAnd8 (
 120   IN      UINTN                     Address,
 121   IN      UINT8                     AndData
 122   )
 123 {
 124   return PciExpressAnd8 (Address, AndData);
 125 }
 126
 127 /**
 128   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 129   value, followed a  bitwise inclusive OR with another 8-bit value.
 130
 131   Reads the 8-bit PCI configuration register specified by Address, performs a
 132   bitwise AND between the read result and the value specified by AndData,
 133   performs a bitwise inclusive OR between the result of the AND operation and
 134   the value specified by OrData, and writes the result to the 8-bit PCI
 135   configuration register specified by Address. The value written to the PCI
 136   configuration register is returned. This function must guarantee that all PCI
 137   read and write operations are serialized.
 138
 139   If Address > 0x0FFFFFFF, then ASSERT().
 140
 141   @param  Address Address that encodes the PCI Bus, Device, Function and
 142                   Register.
 143   @param  AndData The value to AND with the PCI configuration register.
 144   @param  OrData  The value to OR with the result of the AND operation.
 145
 146   @return The value written back to the PCI configuration register.
 147
 148 **/
 149 UINT8
 150 EFIAPI
 151 PciAndThenOr8 (
 152   IN      UINTN                     Address,
 153   IN      UINT8                     AndData,
 154   IN      UINT8                     OrData
 155   )
 156 {
 157   return PciExpressAndThenOr8 (Address, AndData, OrData);
 158 }
 159
 160 /**
 161   Reads a bit field of a PCI configuration register.
 162
 163   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 164   specified by the StartBit and the EndBit. The value of the bit field is
 165   returned.
 166
 167   If Address > 0x0FFFFFFF, then ASSERT().
 168   If StartBit is greater than 7, then ASSERT().
 169   If EndBit is greater than 7, then ASSERT().
 170   If EndBit is less than or equal to StartBit, then ASSERT().
 171
 172   @param  Address   PCI configuration register to read.
 173   @param  StartBit  The ordinal of the least significant bit in the bit field.
 174                     Range 0..7.
 175   @param  EndBit    The ordinal of the most significant bit in the bit field.
 176                     Range 0..7.
 177
 178   @return The value of the bit field read from the PCI configuration register.
 179
 180 **/
 181 UINT8
 182 EFIAPI
 183 PciBitFieldRead8 (
 184   IN      UINTN                     Address,
 185   IN      UINTN                     StartBit,
 186   IN      UINTN                     EndBit
 187   )
 188 {
 189   return PciExpressBitFieldRead8 (Address, StartBit, EndBit);
 190 }
 191
 192 /**
 193   Writes a bit field to a PCI configuration register.
 194
 195   Writes Value to the bit field of the PCI configuration register. The bit
 196   field is specified by the StartBit and the EndBit. All other bits in the
 197   destination PCI configuration register are preserved. The new value of the
 198   8-bit register is returned.
 199
 200   If Address > 0x0FFFFFFF, then ASSERT().
 201   If StartBit is greater than 7, then ASSERT().
 202   If EndBit is greater than 7, then ASSERT().
 203   If EndBit is less than or equal to StartBit, then ASSERT().
 204
 205   @param  Address   PCI configuration register to write.
 206   @param  StartBit  The ordinal of the least significant bit in the bit field.
 207                     Range 0..7.
 208   @param  EndBit    The ordinal of the most significant bit in the bit field.
 209                     Range 0..7.
 210   @param  Value     New value of the bit field.
 211
 212   @return The value written back to the PCI configuration register.
 213
 214 **/
 215 UINT8
 216 EFIAPI
 217 PciBitFieldWrite8 (
 218   IN      UINTN                     Address,
 219   IN      UINTN                     StartBit,
 220   IN      UINTN                     EndBit,
 221   IN      UINT8                     Value
 222   )
 223 {
 224   return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);
 225 }
 226
 227 /**
 228   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 229   writes the result back to the bit field in the 8-bit port.
 230
 231   Reads the 8-bit PCI configuration register specified by Address, performs a
 232   bitwise inclusive OR between the read result and the value specified by
 233   OrData, and writes the result to the 8-bit PCI configuration register
 234   specified by Address. The value written to the PCI configuration register is
 235   returned. This function must guarantee that all PCI read and write operations
 236   are serialized. Extra left bits in OrData are stripped.
 237
 238   If Address > 0x0FFFFFFF, then ASSERT().
 239   If StartBit is greater than 7, then ASSERT().
 240   If EndBit is greater than 7, then ASSERT().
 241   If EndBit is less than or equal to StartBit, then ASSERT().
 242
 243   @param  Address   PCI configuration register to write.
 244   @param  StartBit  The ordinal of the least significant bit in the bit field.
 245                     Range 0..7.
 246   @param  EndBit    The ordinal of the most significant bit in the bit field.
 247                     Range 0..7.
 248   @param  OrData    The value to OR with the PCI configuration register.
 249
 250   @return The value written back to the PCI configuration register.
 251
 252 **/
 253 UINT8
 254 EFIAPI
 255 PciBitFieldOr8 (
 256   IN      UINTN                     Address,
 257   IN      UINTN                     StartBit,
 258   IN      UINTN                     EndBit,
 259   IN      UINT8                     OrData
 260   )
 261 {
 262   return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);
 263 }
 264
 265 /**
 266   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 267   AND, and writes the result back to the bit field in the 8-bit register.
 268
 269   Reads the 8-bit PCI configuration register specified by Address, performs a
 270   bitwise AND between the read result and the value specified by AndData, and
 271   writes the result to the 8-bit PCI configuration register specified by
 272   Address. The value written to the PCI configuration register is returned.
 273   This function must guarantee that all PCI read and write operations are
 274   serialized. Extra left bits in AndData are stripped.
 275
 276   If Address > 0x0FFFFFFF, then ASSERT().
 277   If StartBit is greater than 7, then ASSERT().
 278   If EndBit is greater than 7, then ASSERT().
 279   If EndBit is less than or equal to StartBit, then ASSERT().
 280
 281   @param  Address   PCI configuration register to write.
 282   @param  StartBit  The ordinal of the least significant bit in the bit field.
 283                     Range 0..7.
 284   @param  EndBit    The ordinal of the most significant bit in the bit field.
 285                     Range 0..7.
 286   @param  AndData   The value to AND with the PCI configuration register.
 287
 288   @return The value written back to the PCI configuration register.
 289
 290 **/
 291 UINT8
 292 EFIAPI
 293 PciBitFieldAnd8 (
 294   IN      UINTN                     Address,
 295   IN      UINTN                     StartBit,
 296   IN      UINTN                     EndBit,
 297   IN      UINT8                     AndData
 298   )
 299 {
 300   return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);
 301 }
 302
 303 /**
 304   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 305   bitwise inclusive OR, and writes the result back to the bit field in the
 306   8-bit port.
 307
 308   Reads the 8-bit PCI configuration register specified by Address, performs a
 309   bitwise AND followed by a bitwise inclusive OR between the read result and
 310   the value specified by AndData, and writes the result to the 8-bit PCI
 311   configuration register specified by Address. The value written to the PCI
 312   configuration register is returned. This function must guarantee that all PCI
 313   read and write operations are serialized. Extra left bits in both AndData and
 314   OrData are stripped.
 315
 316   If Address > 0x0FFFFFFF, then ASSERT().
 317   If StartBit is greater than 7, then ASSERT().
 318   If EndBit is greater than 7, then ASSERT().
 319   If EndBit is less than or equal to StartBit, then ASSERT().
 320
 321   @param  Address   PCI configuration register to write.
 322   @param  StartBit  The ordinal of the least significant bit in the bit field.
 323                     Range 0..7.
 324   @param  EndBit    The ordinal of the most significant bit in the bit field.
 325                     Range 0..7.
 326   @param  AndData   The value to AND with the PCI configuration register.
 327   @param  OrData    The value to OR with the result of the AND operation.
 328
 329   @return The value written back to the PCI configuration register.
 330
 331 **/
 332 UINT8
 333 EFIAPI
 334 PciBitFieldAndThenOr8 (
 335   IN      UINTN                     Address,
 336   IN      UINTN                     StartBit,
 337   IN      UINTN                     EndBit,
 338   IN      UINT8                     AndData,
 339   IN      UINT8                     OrData
 340   )
 341 {
 342   return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);
 343 }
 344
 345 /**
 346   Reads a 16-bit PCI configuration register.
 347
 348   Reads and returns the 16-bit PCI configuration register specified by Address.
 349   This function must guarantee that all PCI read and write operations are
 350   serialized.
 351
 352   If Address > 0x0FFFFFFF, then ASSERT().
 353
 354   @param  Address Address that encodes the PCI Bus, Device, Function and
 355                   Register.
 356
 357   @return The read value from the PCI configuration register.
 358
 359 **/
 360 UINT16
 361 EFIAPI
 362 PciRead16 (
 363   IN      UINTN                     Address
 364   )
 365 {
 366   return PciExpressRead16 (Address);
 367 }
 368
 369 /**
 370   Writes a 16-bit PCI configuration register.
 371
 372   Writes the 16-bit PCI configuration register specified by Address with the
 373   value specified by Value. Value is returned. This function must guarantee
 374   that all PCI read and write operations are serialized.
 375
 376   If Address > 0x0FFFFFFF, then ASSERT().
 377
 378   @param  Address Address that encodes the PCI Bus, Device, Function and
 379                   Register.
 380   @param  Value   The value to write.
 381
 382   @return The value written to the PCI configuration register.
 383
 384 **/
 385 UINT16
 386 EFIAPI
 387 PciWrite16 (
 388   IN      UINTN                     Address,
 389   IN      UINT16                    Data
 390   )
 391 {
 392   return PciExpressWrite16 (Address, Data);
 393 }
 394
 395 /**
 396   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 397   a 16-bit value.
 398
 399   Reads the 16-bit PCI configuration register specified by Address, performs a
 400   bitwise inclusive OR between the read result and the value specified by
 401   OrData, and writes the result to the 16-bit PCI configuration register
 402   specified by Address. The value written to the PCI configuration register is
 403   returned. This function must guarantee that all PCI read and write operations
 404   are serialized.
 405
 406   If Address > 0x0FFFFFFF, then ASSERT().
 407
 408   @param  Address Address that encodes the PCI Bus, Device, Function and
 409                   Register.
 410   @param  OrData  The value to OR with the PCI configuration register.
 411
 412   @return The value written back to the PCI configuration register.
 413
 414 **/
 415 UINT16
 416 EFIAPI
 417 PciOr16 (
 418   IN      UINTN                     Address,
 419   IN      UINT16                    OrData
 420   )
 421 {
 422   return PciExpressOr16 (Address, OrData);
 423 }
 424
 425 /**
 426   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 427   value.
 428
 429   Reads the 16-bit PCI configuration register specified by Address, performs a
 430   bitwise AND between the read result and the value specified by AndData, and
 431   writes the result to the 16-bit PCI configuration register specified by
 432   Address. The value written to the PCI configuration register is returned.
 433   This function must guarantee that all PCI read and write operations are
 434   serialized.
 435
 436   If Address > 0x0FFFFFFF, then ASSERT().
 437
 438   @param  Address Address that encodes the PCI Bus, Device, Function and
 439                   Register.
 440   @param  AndData The value to AND with the PCI configuration register.
 441
 442   @return The value written back to the PCI configuration register.
 443
 444 **/
 445 UINT16
 446 EFIAPI
 447 PciAnd16 (
 448   IN      UINTN                     Address,
 449   IN      UINT16                    AndData
 450   )
 451 {
 452   return PciExpressAnd16 (Address, AndData);
 453 }
 454
 455 /**
 456   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 457   value, followed a  bitwise inclusive OR with another 16-bit value.
 458
 459   Reads the 16-bit PCI configuration register specified by Address, performs a
 460   bitwise AND between the read result and the value specified by AndData,
 461   performs a bitwise inclusive OR between the result of the AND operation and
 462   the value specified by OrData, and writes the result to the 16-bit PCI
 463   configuration register specified by Address. The value written to the PCI
 464   configuration register is returned. This function must guarantee that all PCI
 465   read and write operations are serialized.
 466
 467   If Address > 0x0FFFFFFF, then ASSERT().
 468
 469   @param  Address Address that encodes the PCI Bus, Device, Function and
 470                   Register.
 471   @param  AndData The value to AND with the PCI configuration register.
 472   @param  OrData  The value to OR with the result of the AND operation.
 473
 474   @return The value written back to the PCI configuration register.
 475
 476 **/
 477 UINT16
 478 EFIAPI
 479 PciAndThenOr16 (
 480   IN      UINTN                     Address,
 481   IN      UINT16                    AndData,
 482   IN      UINT16                    OrData
 483   )
 484 {
 485   return PciExpressAndThenOr16 (Address, AndData, OrData);
 486 }
 487
 488 /**
 489   Reads a bit field of a PCI configuration register.
 490
 491   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 492   specified by the StartBit and the EndBit. The value of the bit field is
 493   returned.
 494
 495   If Address > 0x0FFFFFFF, then ASSERT().
 496   If StartBit is greater than 15, then ASSERT().
 497   If EndBit is greater than 15, then ASSERT().
 498   If EndBit is less than or equal to StartBit, then ASSERT().
 499
 500   @param  Address   PCI configuration register to read.
 501   @param  StartBit  The ordinal of the least significant bit in the bit field.
 502                     Range 0..15.
 503   @param  EndBit    The ordinal of the most significant bit in the bit field.
 504                     Range 0..15.
 505
 506   @return The value of the bit field read from the PCI configuration register.
 507
 508 **/
 509 UINT16
 510 EFIAPI
 511 PciBitFieldRead16 (
 512   IN      UINTN                     Address,
 513   IN      UINTN                     StartBit,
 514   IN      UINTN                     EndBit
 515   )
 516 {
 517   return PciExpressBitFieldRead16 (Address, StartBit, EndBit);
 518 }
 519
 520 /**
 521   Writes a bit field to a PCI configuration register.
 522
 523   Writes Value to the bit field of the PCI configuration register. The bit
 524   field is specified by the StartBit and the EndBit. All other bits in the
 525   destination PCI configuration register are preserved. The new value of the
 526   16-bit register is returned.
 527
 528   If Address > 0x0FFFFFFF, then ASSERT().
 529   If StartBit is greater than 15, then ASSERT().
 530   If EndBit is greater than 15, then ASSERT().
 531   If EndBit is less than or equal to StartBit, then ASSERT().
 532
 533   @param  Address   PCI configuration register to write.
 534   @param  StartBit  The ordinal of the least significant bit in the bit field.
 535                     Range 0..15.
 536   @param  EndBit    The ordinal of the most significant bit in the bit field.
 537                     Range 0..15.
 538   @param  Value     New value of the bit field.
 539
 540   @return The value written back to the PCI configuration register.
 541
 542 **/
 543 UINT16
 544 EFIAPI
 545 PciBitFieldWrite16 (
 546   IN      UINTN                     Address,
 547   IN      UINTN                     StartBit,
 548   IN      UINTN                     EndBit,
 549   IN      UINT16                    Value
 550   )
 551 {
 552   return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);
 553 }
 554
 555 /**
 556   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 557   writes the result back to the bit field in the 16-bit port.
 558
 559   Reads the 16-bit PCI configuration register specified by Address, performs a
 560   bitwise inclusive OR between the read result and the value specified by
 561   OrData, and writes the result to the 16-bit PCI configuration register
 562   specified by Address. The value written to the PCI configuration register is
 563   returned. This function must guarantee that all PCI read and write operations
 564   are serialized. Extra left bits in OrData are stripped.
 565
 566   If Address > 0x0FFFFFFF, then ASSERT().
 567   If StartBit is greater than 15, then ASSERT().
 568   If EndBit is greater than 15, then ASSERT().
 569   If EndBit is less than or equal to StartBit, then ASSERT().
 570
 571   @param  Address   PCI configuration register to write.
 572   @param  StartBit  The ordinal of the least significant bit in the bit field.
 573                     Range 0..15.
 574   @param  EndBit    The ordinal of the most significant bit in the bit field.
 575                     Range 0..15.
 576   @param  OrData    The value to OR with the PCI configuration register.
 577
 578   @return The value written back to the PCI configuration register.
 579
 580 **/
 581 UINT16
 582 EFIAPI
 583 PciBitFieldOr16 (
 584   IN      UINTN                     Address,
 585   IN      UINTN                     StartBit,
 586   IN      UINTN                     EndBit,
 587   IN      UINT16                    OrData
 588   )
 589 {
 590   return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);
 591 }
 592
 593 /**
 594   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 595   AND, and writes the result back to the bit field in the 16-bit register.
 596
 597   Reads the 16-bit PCI configuration register specified by Address, performs a
 598   bitwise AND between the read result and the value specified by AndData, and
 599   writes the result to the 16-bit PCI configuration register specified by
 600   Address. The value written to the PCI configuration register is returned.
 601   This function must guarantee that all PCI read and write operations are
 602   serialized. Extra left bits in AndData are stripped.
 603
 604   If Address > 0x0FFFFFFF, then ASSERT().
 605   If StartBit is greater than 15, then ASSERT().
 606   If EndBit is greater than 15, then ASSERT().
 607   If EndBit is less than or equal to StartBit, then ASSERT().
 608
 609   @param  Address   PCI configuration register to write.
 610   @param  StartBit  The ordinal of the least significant bit in the bit field.
 611                     Range 0..15.
 612   @param  EndBit    The ordinal of the most significant bit in the bit field.
 613                     Range 0..15.
 614   @param  AndData   The value to AND with the PCI configuration register.
 615
 616   @return The value written back to the PCI configuration register.
 617
 618 **/
 619 UINT16
 620 EFIAPI
 621 PciBitFieldAnd16 (
 622   IN      UINTN                     Address,
 623   IN      UINTN                     StartBit,
 624   IN      UINTN                     EndBit,
 625   IN      UINT16                    AndData
 626   )
 627 {
 628   return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);
 629 }
 630
 631 /**
 632   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 633   bitwise inclusive OR, and writes the result back to the bit field in the
 634   16-bit port.
 635
 636   Reads the 16-bit PCI configuration register specified by Address, performs a
 637   bitwise AND followed by a bitwise inclusive OR between the read result and
 638   the value specified by AndData, and writes the result to the 16-bit PCI
 639   configuration register specified by Address. The value written to the PCI
 640   configuration register is returned. This function must guarantee that all PCI
 641   read and write operations are serialized. Extra left bits in both AndData and
 642   OrData are stripped.
 643
 644   If Address > 0x0FFFFFFF, then ASSERT().
 645   If StartBit is greater than 15, then ASSERT().
 646   If EndBit is greater than 15, then ASSERT().
 647   If EndBit is less than or equal to StartBit, then ASSERT().
 648
 649   @param  Address   PCI configuration register to write.
 650   @param  StartBit  The ordinal of the least significant bit in the bit field.
 651                     Range 0..15.
 652   @param  EndBit    The ordinal of the most significant bit in the bit field.
 653                     Range 0..15.
 654   @param  AndData   The value to AND with the PCI configuration register.
 655   @param  OrData    The value to OR with the result of the AND operation.
 656
 657   @return The value written back to the PCI configuration register.
 658
 659 **/
 660 UINT16
 661 EFIAPI
 662 PciBitFieldAndThenOr16 (
 663   IN      UINTN                     Address,
 664   IN      UINTN                     StartBit,
 665   IN      UINTN                     EndBit,
 666   IN      UINT16                    AndData,
 667   IN      UINT16                    OrData
 668   )
 669 {
 670   return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);
 671 }
 672
 673 /**
 674   Reads a 32-bit PCI configuration register.
 675
 676   Reads and returns the 32-bit PCI configuration register specified by Address.
 677   This function must guarantee that all PCI read and write operations are
 678   serialized.
 679
 680   If Address > 0x0FFFFFFF, then ASSERT().
 681
 682   @param  Address Address that encodes the PCI Bus, Device, Function and
 683                   Register.
 684
 685   @return The read value from the PCI configuration register.
 686
 687 **/
 688 UINT32
 689 EFIAPI
 690 PciRead32 (
 691   IN      UINTN                     Address
 692   )
 693 {
 694   return PciExpressRead32 (Address);
 695 }
 696
 697 /**
 698   Writes a 32-bit PCI configuration register.
 699
 700   Writes the 32-bit PCI configuration register specified by Address with the
 701   value specified by Value. Value is returned. This function must guarantee
 702   that all PCI read and write operations are serialized.
 703
 704   If Address > 0x0FFFFFFF, then ASSERT().
 705
 706   @param  Address Address that encodes the PCI Bus, Device, Function and
 707                   Register.
 708   @param  Value   The value to write.
 709
 710   @return The value written to the PCI configuration register.
 711
 712 **/
 713 UINT32
 714 EFIAPI
 715 PciWrite32 (
 716   IN      UINTN                     Address,
 717   IN      UINT32                    Data
 718   )
 719 {
 720   return PciExpressWrite32 (Address, Data);
 721 }
 722
 723 /**
 724   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 725   a 32-bit value.
 726
 727   Reads the 32-bit PCI configuration register specified by Address, performs a
 728   bitwise inclusive OR between the read result and the value specified by
 729   OrData, and writes the result to the 32-bit PCI configuration register
 730   specified by Address. The value written to the PCI configuration register is
 731   returned. This function must guarantee that all PCI read and write operations
 732   are serialized.
 733
 734   If Address > 0x0FFFFFFF, then ASSERT().
 735
 736   @param  Address Address that encodes the PCI Bus, Device, Function and
 737                   Register.
 738   @param  OrData  The value to OR with the PCI configuration register.
 739
 740   @return The value written back to the PCI configuration register.
 741
 742 **/
 743 UINT32
 744 EFIAPI
 745 PciOr32 (
 746   IN      UINTN                     Address,
 747   IN      UINT32                    OrData
 748   )
 749 {
 750   return PciExpressOr32 (Address, OrData);
 751 }
 752
 753 /**
 754   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 755   value.
 756
 757   Reads the 32-bit PCI configuration register specified by Address, performs a
 758   bitwise AND between the read result and the value specified by AndData, and
 759   writes the result to the 32-bit PCI configuration register specified by
 760   Address. The value written to the PCI configuration register is returned.
 761   This function must guarantee that all PCI read and write operations are
 762   serialized.
 763
 764   If Address > 0x0FFFFFFF, then ASSERT().
 765
 766   @param  Address Address that encodes the PCI Bus, Device, Function and
 767                   Register.
 768   @param  AndData The value to AND with the PCI configuration register.
 769
 770   @return The value written back to the PCI configuration register.
 771
 772 **/
 773 UINT32
 774 EFIAPI
 775 PciAnd32 (
 776   IN      UINTN                     Address,
 777   IN      UINT32                    AndData
 778   )
 779 {
 780   return PciExpressAnd32 (Address, AndData);
 781 }
 782
 783 /**
 784   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 785   value, followed a  bitwise inclusive OR with another 32-bit value.
 786
 787   Reads the 32-bit PCI configuration register specified by Address, performs a
 788   bitwise AND between the read result and the value specified by AndData,
 789   performs a bitwise inclusive OR between the result of the AND operation and
 790   the value specified by OrData, and writes the result to the 32-bit PCI
 791   configuration register specified by Address. The value written to the PCI
 792   configuration register is returned. This function must guarantee that all PCI
 793   read and write operations are serialized.
 794
 795   If Address > 0x0FFFFFFF, then ASSERT().
 796
 797   @param  Address Address that encodes the PCI Bus, Device, Function and
 798                   Register.
 799   @param  AndData The value to AND with the PCI configuration register.
 800   @param  OrData  The value to OR with the result of the AND operation.
 801
 802   @return The value written back to the PCI configuration register.
 803
 804 **/
 805 UINT32
 806 EFIAPI
 807 PciAndThenOr32 (
 808   IN      UINTN                     Address,
 809   IN      UINT32                    AndData,
 810   IN      UINT32                    OrData
 811   )
 812 {
 813   return PciExpressAndThenOr32 (Address, AndData, OrData);
 814 }
 815
 816 /**
 817   Reads a bit field of a PCI configuration register.
 818
 819   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 820   specified by the StartBit and the EndBit. The value of the bit field is
 821   returned.
 822
 823   If Address > 0x0FFFFFFF, then ASSERT().
 824   If StartBit is greater than 31, then ASSERT().
 825   If EndBit is greater than 31, then ASSERT().
 826   If EndBit is less than or equal to StartBit, then ASSERT().
 827
 828   @param  Address   PCI configuration register to read.
 829   @param  StartBit  The ordinal of the least significant bit in the bit field.
 830                     Range 0..31.
 831   @param  EndBit    The ordinal of the most significant bit in the bit field.
 832                     Range 0..31.
 833
 834   @return The value of the bit field read from the PCI configuration register.
 835
 836 **/
 837 UINT32
 838 EFIAPI
 839 PciBitFieldRead32 (
 840   IN      UINTN                     Address,
 841   IN      UINTN                     StartBit,
 842   IN      UINTN                     EndBit
 843   )
 844 {
 845   return PciExpressBitFieldRead32 (Address, StartBit, EndBit);
 846 }
 847
 848 /**
 849   Writes a bit field to a PCI configuration register.
 850
 851   Writes Value to the bit field of the PCI configuration register. The bit
 852   field is specified by the StartBit and the EndBit. All other bits in the
 853   destination PCI configuration register are preserved. The new value of the
 854   32-bit register is returned.
 855
 856   If Address > 0x0FFFFFFF, then ASSERT().
 857   If StartBit is greater than 31, then ASSERT().
 858   If EndBit is greater than 31, then ASSERT().
 859   If EndBit is less than or equal to StartBit, then ASSERT().
 860
 861   @param  Address   PCI configuration register to write.
 862   @param  StartBit  The ordinal of the least significant bit in the bit field.
 863                     Range 0..31.
 864   @param  EndBit    The ordinal of the most significant bit in the bit field.
 865                     Range 0..31.
 866   @param  Value     New value of the bit field.
 867
 868   @return The value written back to the PCI configuration register.
 869
 870 **/
 871 UINT32
 872 EFIAPI
 873 PciBitFieldWrite32 (
 874   IN      UINTN                     Address,
 875   IN      UINTN                     StartBit,
 876   IN      UINTN                     EndBit,
 877   IN      UINT32                    Value
 878   )
 879 {
 880   return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);
 881 }
 882
 883 /**
 884   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 885   writes the result back to the bit field in the 32-bit port.
 886
 887   Reads the 32-bit PCI configuration register specified by Address, performs a
 888   bitwise inclusive OR between the read result and the value specified by
 889   OrData, and writes the result to the 32-bit PCI configuration register
 890   specified by Address. The value written to the PCI configuration register is
 891   returned. This function must guarantee that all PCI read and write operations
 892   are serialized. Extra left bits in OrData are stripped.
 893
 894   If Address > 0x0FFFFFFF, then ASSERT().
 895   If StartBit is greater than 31, then ASSERT().
 896   If EndBit is greater than 31, then ASSERT().
 897   If EndBit is less than or equal to StartBit, then ASSERT().
 898
 899   @param  Address   PCI configuration register to write.
 900   @param  StartBit  The ordinal of the least significant bit in the bit field.
 901                     Range 0..31.
 902   @param  EndBit    The ordinal of the most significant bit in the bit field.
 903                     Range 0..31.
 904   @param  OrData    The value to OR with the PCI configuration register.
 905
 906   @return The value written back to the PCI configuration register.
 907
 908 **/
 909 UINT32
 910 EFIAPI
 911 PciBitFieldOr32 (
 912   IN      UINTN                     Address,
 913   IN      UINTN                     StartBit,
 914   IN      UINTN                     EndBit,
 915   IN      UINT32                    OrData
 916   )
 917 {
 918   return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);
 919 }
 920
 921 /**
 922   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 923   AND, and writes the result back to the bit field in the 32-bit register.
 924
 925   Reads the 32-bit PCI configuration register specified by Address, performs a
 926   bitwise AND between the read result and the value specified by AndData, and
 927   writes the result to the 32-bit PCI configuration register specified by
 928   Address. The value written to the PCI configuration register is returned.
 929   This function must guarantee that all PCI read and write operations are
 930   serialized. Extra left bits in AndData are stripped.
 931
 932   If Address > 0x0FFFFFFF, then ASSERT().
 933   If StartBit is greater than 31, then ASSERT().
 934   If EndBit is greater than 31, then ASSERT().
 935   If EndBit is less than or equal to StartBit, then ASSERT().
 936
 937   @param  Address   PCI configuration register to write.
 938   @param  StartBit  The ordinal of the least significant bit in the bit field.
 939                     Range 0..31.
 940   @param  EndBit    The ordinal of the most significant bit in the bit field.
 941                     Range 0..31.
 942   @param  AndData   The value to AND with the PCI configuration register.
 943
 944   @return The value written back to the PCI configuration register.
 945
 946 **/
 947 UINT32
 948 EFIAPI
 949 PciBitFieldAnd32 (
 950   IN      UINTN                     Address,
 951   IN      UINTN                     StartBit,
 952   IN      UINTN                     EndBit,
 953   IN      UINT32                    AndData
 954   )
 955 {
 956   return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);
 957 }
 958
 959 /**
 960   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 961   bitwise inclusive OR, and writes the result back to the bit field in the
 962   32-bit port.
 963
 964   Reads the 32-bit PCI configuration register specified by Address, performs a
 965   bitwise AND followed by a bitwise inclusive OR between the read result and
 966   the value specified by AndData, and writes the result to the 32-bit PCI
 967   configuration register specified by Address. The value written to the PCI
 968   configuration register is returned. This function must guarantee that all PCI
 969   read and write operations are serialized. Extra left bits in both AndData and
 970   OrData are stripped.
 971
 972   If Address > 0x0FFFFFFF, then ASSERT().
 973   If StartBit is greater than 31, then ASSERT().
 974   If EndBit is greater than 31, then ASSERT().
 975   If EndBit is less than or equal to StartBit, then ASSERT().
 976
 977   @param  Address   PCI configuration register to write.
 978   @param  StartBit  The ordinal of the least significant bit in the bit field.
 979                     Range 0..31.
 980   @param  EndBit    The ordinal of the most significant bit in the bit field.
 981                     Range 0..31.
 982   @param  AndData   The value to AND with the PCI configuration register.
 983   @param  OrData    The value to OR with the result of the AND operation.
 984
 985   @return The value written back to the PCI configuration register.
 986
 987 **/
 988 UINT32
 989 EFIAPI
 990 PciBitFieldAndThenOr32 (
 991   IN      UINTN                     Address,
 992   IN      UINTN                     StartBit,
 993   IN      UINTN                     EndBit,
 994   IN      UINT32                    AndData,
 995   IN      UINT32                    OrData
 996   )
 997 {
 998   return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);
 999 }
1000
1001 /**
1002   Reads a range of PCI configuration registers into a caller supplied buffer.
1003
1004   Reads the range of PCI configuration registers specified by StartAddress and
1005   Size into the buffer specified by Buffer. This function only allows the PCI
1006   configuration registers from a single PCI function to be read. Size is
1007   returned. When possible 32-bit PCI configuration read cycles are used to read
1008   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1009   and 16-bit PCI configuration read cycles may be used at the beginning and the
1010   end of the range.
1011
1012   If StartAddress > 0x0FFFFFFF, then ASSERT().
1013   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1014   If (StartAddress + Size - 1)  > 0x0FFFFFFF, then ASSERT().
1015   If Buffer is NULL, then ASSERT().
1016
1017   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1018                         Function and Register.
1019   @param  Size          Size in bytes of the transfer.
1020   @param  Buffer        Pointer to a buffer receiving the data read.
1021
1022   @return Size
1023
1024 **/
1025 UINTN
1026 EFIAPI
1027 PciReadBuffer (
1028   IN      UINTN                     StartAddress,
1029   IN      UINTN                     Size,
1030   OUT     VOID                      *Buffer
1031   )
1032 {
1033   return PciExpressReadBuffer (StartAddress, Size, Buffer);
1034 }
1035
1036 /**
1037   Copies the data in a caller supplied buffer to a specified range of PCI
1038   configuration space.
1039
1040   Writes the range of PCI configuration registers specified by StartAddress and
1041   Size from the buffer specified by Buffer. This function only allows the PCI
1042   configuration registers from a single PCI function to be written. Size is
1043   returned. When possible 32-bit PCI configuration write cycles are used to
1044   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1045   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1046   and the end of the range.
1047
1048   If StartAddress > 0x0FFFFFFF, then ASSERT().
1049   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1050   If (StartAddress + Size - 1)  > 0x0FFFFFFF, then ASSERT().
1051   If Buffer is NULL, then ASSERT().
1052
1053   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1054                         Function and Register.
1055   @param  Size          Size in bytes of the transfer.
1056   @param  Buffer        Pointer to a buffer containing the data to write.
1057
1058   @return Size
1059
1060 **/
1061 UINTN
1062 EFIAPI
1063 PciWriteBuffer (
1064   IN      UINTN                     StartAddress,
1065   IN      UINTN                     Size,
1066   IN      VOID                      *Buffer
1067   )
1068 {
1069   return PciExpressWriteBuffer (StartAddress, Size, Buffer);
1070 }