MdePkg/Library/BasePciLibPciExpress/PciLib.c

   1 /** @file
   2   PCI Library using PC Express access.
   3
   4   Copyright (c) 2006, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13   Module Name:  PciLib.c
  14
  15 **/
  16
  17 //
  18 // The package level header files this module uses
  19 //
  20 #include <Base.h>
  21 //
  22 // The protocols, PPI and GUID defintions for this module
  23 //
  24 //
  25 // The Library classes this module consumes
  26 //
  27 #include <Library/PciLib.h>
  28 #include <Library/PciExpressLib.h>
  29
  30 /**
  31   Reads an 8-bit PCI configuration register.
  32
  33   Reads and returns the 8-bit PCI configuration register specified by Address.
  34   This function must guarantee that all PCI read and write operations are
  35   serialized.
  36
  37   If Address > 0x0FFFFFFF, then ASSERT().
  38
  39   @param  Address Address that encodes the PCI Bus, Device, Function and
  40                   Register.
  41
  42   @return The read value from the PCI configuration register.
  43
  44 **/
  45 UINT8
  46 EFIAPI
  47 PciRead8 (
  48   IN      UINTN                     Address
  49   )
  50 {
  51   return PciExpressRead8 (Address);
  52 }
  53
  54 /**
  55   Writes an 8-bit PCI configuration register.
  56
  57   Writes the 8-bit PCI configuration register specified by Address with the
  58   value specified by Value. Value is returned. This function must guarantee
  59   that all PCI read and write operations are serialized.
  60
  61   If Address > 0x0FFFFFFF, then ASSERT().
  62
  63   @param  Address Address that encodes the PCI Bus, Device, Function and
  64                   Register.
  65   @param  Value   The value to write.
  66
  67   @return The value written to the PCI configuration register.
  68
  69 **/
  70 UINT8
  71 EFIAPI
  72 PciWrite8 (
  73   IN      UINTN                     Address,
  74   IN      UINT8                     Data
  75   )
  76 {
  77   return PciExpressWrite8 (Address, Data);
  78 }
  79
  80 /**
  81   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
  82   an 8-bit value.
  83
  84   Reads the 8-bit PCI configuration register specified by Address, performs a
  85   bitwise inclusive OR between the read result and the value specified by
  86   OrData, and writes the result to the 8-bit PCI configuration register
  87   specified by Address. The value written to the PCI configuration register is
  88   returned. This function must guarantee that all PCI read and write operations
  89   are serialized.
  90
  91   If Address > 0x0FFFFFFF, then ASSERT().
  92
  93   @param  Address Address that encodes the PCI Bus, Device, Function and
  94                   Register.
  95   @param  OrData  The value to OR with the PCI configuration register.
  96
  97   @return The value written back to the PCI configuration register.
  98
  99 **/
 100 UINT8
 101 EFIAPI
 102 PciOr8 (
 103   IN      UINTN                     Address,
 104   IN      UINT8                     OrData
 105   )
 106 {
 107   return PciExpressOr8 (Address, OrData);
 108 }
 109
 110 /**
 111   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 112   value.
 113
 114   Reads the 8-bit PCI configuration register specified by Address, performs a
 115   bitwise AND between the read result and the value specified by AndData, and
 116   writes the result to the 8-bit PCI configuration register specified by
 117   Address. The value written to the PCI configuration register is returned.
 118   This function must guarantee that all PCI read and write operations are
 119   serialized.
 120
 121   If Address > 0x0FFFFFFF, then ASSERT().
 122
 123   @param  Address Address that encodes the PCI Bus, Device, Function and
 124                   Register.
 125   @param  AndData The value to AND with the PCI configuration register.
 126
 127   @return The value written back to the PCI configuration register.
 128
 129 **/
 130 UINT8
 131 EFIAPI
 132 PciAnd8 (
 133   IN      UINTN                     Address,
 134   IN      UINT8                     AndData
 135   )
 136 {
 137   return PciExpressAnd8 (Address, AndData);
 138 }
 139
 140 /**
 141   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 142   value, followed a  bitwise inclusive OR with another 8-bit value.
 143
 144   Reads the 8-bit PCI configuration register specified by Address, performs a
 145   bitwise AND between the read result and the value specified by AndData,
 146   performs a bitwise inclusive OR between the result of the AND operation and
 147   the value specified by OrData, and writes the result to the 8-bit PCI
 148   configuration register specified by Address. The value written to the PCI
 149   configuration register is returned. This function must guarantee that all PCI
 150   read and write operations are serialized.
 151
 152   If Address > 0x0FFFFFFF, then ASSERT().
 153
 154   @param  Address Address that encodes the PCI Bus, Device, Function and
 155                   Register.
 156   @param  AndData The value to AND with the PCI configuration register.
 157   @param  OrData  The value to OR with the result of the AND operation.
 158
 159   @return The value written back to the PCI configuration register.
 160
 161 **/
 162 UINT8
 163 EFIAPI
 164 PciAndThenOr8 (
 165   IN      UINTN                     Address,
 166   IN      UINT8                     AndData,
 167   IN      UINT8                     OrData
 168   )
 169 {
 170   return PciExpressAndThenOr8 (Address, AndData, OrData);
 171 }
 172
 173 /**
 174   Reads a bit field of a PCI configuration register.
 175
 176   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 177   specified by the StartBit and the EndBit. The value of the bit field is
 178   returned.
 179
 180   If Address > 0x0FFFFFFF, then ASSERT().
 181   If StartBit is greater than 7, then ASSERT().
 182   If EndBit is greater than 7, then ASSERT().
 183   If EndBit is less than StartBit, then ASSERT().
 184
 185   @param  Address   PCI configuration register to read.
 186   @param  StartBit  The ordinal of the least significant bit in the bit field.
 187                     Range 0..7.
 188   @param  EndBit    The ordinal of the most significant bit in the bit field.
 189                     Range 0..7.
 190
 191   @return The value of the bit field read from the PCI configuration register.
 192
 193 **/
 194 UINT8
 195 EFIAPI
 196 PciBitFieldRead8 (
 197   IN      UINTN                     Address,
 198   IN      UINTN                     StartBit,
 199   IN      UINTN                     EndBit
 200   )
 201 {
 202   return PciExpressBitFieldRead8 (Address, StartBit, EndBit);
 203 }
 204
 205 /**
 206   Writes a bit field to a PCI configuration register.
 207
 208   Writes Value to the bit field of the PCI configuration register. The bit
 209   field is specified by the StartBit and the EndBit. All other bits in the
 210   destination PCI configuration register are preserved. The new value of the
 211   8-bit register is returned.
 212
 213   If Address > 0x0FFFFFFF, then ASSERT().
 214   If StartBit is greater than 7, then ASSERT().
 215   If EndBit is greater than 7, then ASSERT().
 216   If EndBit is less than StartBit, then ASSERT().
 217
 218   @param  Address   PCI configuration register to write.
 219   @param  StartBit  The ordinal of the least significant bit in the bit field.
 220                     Range 0..7.
 221   @param  EndBit    The ordinal of the most significant bit in the bit field.
 222                     Range 0..7.
 223   @param  Value     New value of the bit field.
 224
 225   @return The value written back to the PCI configuration register.
 226
 227 **/
 228 UINT8
 229 EFIAPI
 230 PciBitFieldWrite8 (
 231   IN      UINTN                     Address,
 232   IN      UINTN                     StartBit,
 233   IN      UINTN                     EndBit,
 234   IN      UINT8                     Value
 235   )
 236 {
 237   return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);
 238 }
 239
 240 /**
 241   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 242   writes the result back to the bit field in the 8-bit port.
 243
 244   Reads the 8-bit PCI configuration register specified by Address, performs a
 245   bitwise inclusive OR between the read result and the value specified by
 246   OrData, and writes the result to the 8-bit PCI configuration register
 247   specified by Address. The value written to the PCI configuration register is
 248   returned. This function must guarantee that all PCI read and write operations
 249   are serialized. Extra left bits in OrData are stripped.
 250
 251   If Address > 0x0FFFFFFF, then ASSERT().
 252   If StartBit is greater than 7, then ASSERT().
 253   If EndBit is greater than 7, then ASSERT().
 254   If EndBit is less than StartBit, then ASSERT().
 255
 256   @param  Address   PCI configuration register to write.
 257   @param  StartBit  The ordinal of the least significant bit in the bit field.
 258                     Range 0..7.
 259   @param  EndBit    The ordinal of the most significant bit in the bit field.
 260                     Range 0..7.
 261   @param  OrData    The value to OR with the PCI configuration register.
 262
 263   @return The value written back to the PCI configuration register.
 264
 265 **/
 266 UINT8
 267 EFIAPI
 268 PciBitFieldOr8 (
 269   IN      UINTN                     Address,
 270   IN      UINTN                     StartBit,
 271   IN      UINTN                     EndBit,
 272   IN      UINT8                     OrData
 273   )
 274 {
 275   return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);
 276 }
 277
 278 /**
 279   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 280   AND, and writes the result back to the bit field in the 8-bit register.
 281
 282   Reads the 8-bit PCI configuration register specified by Address, performs a
 283   bitwise AND between the read result and the value specified by AndData, and
 284   writes the result to the 8-bit PCI configuration register specified by
 285   Address. The value written to the PCI configuration register is returned.
 286   This function must guarantee that all PCI read and write operations are
 287   serialized. Extra left bits in AndData are stripped.
 288
 289   If Address > 0x0FFFFFFF, then ASSERT().
 290   If StartBit is greater than 7, then ASSERT().
 291   If EndBit is greater than 7, then ASSERT().
 292   If EndBit is less than StartBit, then ASSERT().
 293
 294   @param  Address   PCI configuration register to write.
 295   @param  StartBit  The ordinal of the least significant bit in the bit field.
 296                     Range 0..7.
 297   @param  EndBit    The ordinal of the most significant bit in the bit field.
 298                     Range 0..7.
 299   @param  AndData   The value to AND with the PCI configuration register.
 300
 301   @return The value written back to the PCI configuration register.
 302
 303 **/
 304 UINT8
 305 EFIAPI
 306 PciBitFieldAnd8 (
 307   IN      UINTN                     Address,
 308   IN      UINTN                     StartBit,
 309   IN      UINTN                     EndBit,
 310   IN      UINT8                     AndData
 311   )
 312 {
 313   return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);
 314 }
 315
 316 /**
 317   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 318   bitwise inclusive OR, and writes the result back to the bit field in the
 319   8-bit port.
 320
 321   Reads the 8-bit PCI configuration register specified by Address, performs a
 322   bitwise AND followed by a bitwise inclusive OR between the read result and
 323   the value specified by AndData, and writes the result to the 8-bit PCI
 324   configuration register specified by Address. The value written to the PCI
 325   configuration register is returned. This function must guarantee that all PCI
 326   read and write operations are serialized. Extra left bits in both AndData and
 327   OrData are stripped.
 328
 329   If Address > 0x0FFFFFFF, then ASSERT().
 330   If StartBit is greater than 7, then ASSERT().
 331   If EndBit is greater than 7, then ASSERT().
 332   If EndBit is less than StartBit, then ASSERT().
 333
 334   @param  Address   PCI configuration register to write.
 335   @param  StartBit  The ordinal of the least significant bit in the bit field.
 336                     Range 0..7.
 337   @param  EndBit    The ordinal of the most significant bit in the bit field.
 338                     Range 0..7.
 339   @param  AndData   The value to AND with the PCI configuration register.
 340   @param  OrData    The value to OR with the result of the AND operation.
 341
 342   @return The value written back to the PCI configuration register.
 343
 344 **/
 345 UINT8
 346 EFIAPI
 347 PciBitFieldAndThenOr8 (
 348   IN      UINTN                     Address,
 349   IN      UINTN                     StartBit,
 350   IN      UINTN                     EndBit,
 351   IN      UINT8                     AndData,
 352   IN      UINT8                     OrData
 353   )
 354 {
 355   return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);
 356 }
 357
 358 /**
 359   Reads a 16-bit PCI configuration register.
 360
 361   Reads and returns the 16-bit PCI configuration register specified by Address.
 362   This function must guarantee that all PCI read and write operations are
 363   serialized.
 364
 365   If Address > 0x0FFFFFFF, then ASSERT().
 366
 367   @param  Address Address that encodes the PCI Bus, Device, Function and
 368                   Register.
 369
 370   @return The read value from the PCI configuration register.
 371
 372 **/
 373 UINT16
 374 EFIAPI
 375 PciRead16 (
 376   IN      UINTN                     Address
 377   )
 378 {
 379   return PciExpressRead16 (Address);
 380 }
 381
 382 /**
 383   Writes a 16-bit PCI configuration register.
 384
 385   Writes the 16-bit PCI configuration register specified by Address with the
 386   value specified by Value. Value is returned. This function must guarantee
 387   that all PCI read and write operations are serialized.
 388
 389   If Address > 0x0FFFFFFF, then ASSERT().
 390
 391   @param  Address Address that encodes the PCI Bus, Device, Function and
 392                   Register.
 393   @param  Value   The value to write.
 394
 395   @return The value written to the PCI configuration register.
 396
 397 **/
 398 UINT16
 399 EFIAPI
 400 PciWrite16 (
 401   IN      UINTN                     Address,
 402   IN      UINT16                    Data
 403   )
 404 {
 405   return PciExpressWrite16 (Address, Data);
 406 }
 407
 408 /**
 409   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 410   a 16-bit value.
 411
 412   Reads the 16-bit PCI configuration register specified by Address, performs a
 413   bitwise inclusive OR between the read result and the value specified by
 414   OrData, and writes the result to the 16-bit PCI configuration register
 415   specified by Address. The value written to the PCI configuration register is
 416   returned. This function must guarantee that all PCI read and write operations
 417   are serialized.
 418
 419   If Address > 0x0FFFFFFF, then ASSERT().
 420
 421   @param  Address Address that encodes the PCI Bus, Device, Function and
 422                   Register.
 423   @param  OrData  The value to OR with the PCI configuration register.
 424
 425   @return The value written back to the PCI configuration register.
 426
 427 **/
 428 UINT16
 429 EFIAPI
 430 PciOr16 (
 431   IN      UINTN                     Address,
 432   IN      UINT16                    OrData
 433   )
 434 {
 435   return PciExpressOr16 (Address, OrData);
 436 }
 437
 438 /**
 439   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 440   value.
 441
 442   Reads the 16-bit PCI configuration register specified by Address, performs a
 443   bitwise AND between the read result and the value specified by AndData, and
 444   writes the result to the 16-bit PCI configuration register specified by
 445   Address. The value written to the PCI configuration register is returned.
 446   This function must guarantee that all PCI read and write operations are
 447   serialized.
 448
 449   If Address > 0x0FFFFFFF, then ASSERT().
 450
 451   @param  Address Address that encodes the PCI Bus, Device, Function and
 452                   Register.
 453   @param  AndData The value to AND with the PCI configuration register.
 454
 455   @return The value written back to the PCI configuration register.
 456
 457 **/
 458 UINT16
 459 EFIAPI
 460 PciAnd16 (
 461   IN      UINTN                     Address,
 462   IN      UINT16                    AndData
 463   )
 464 {
 465   return PciExpressAnd16 (Address, AndData);
 466 }
 467
 468 /**
 469   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 470   value, followed a  bitwise inclusive OR with another 16-bit value.
 471
 472   Reads the 16-bit PCI configuration register specified by Address, performs a
 473   bitwise AND between the read result and the value specified by AndData,
 474   performs a bitwise inclusive OR between the result of the AND operation and
 475   the value specified by OrData, and writes the result to the 16-bit PCI
 476   configuration register specified by Address. The value written to the PCI
 477   configuration register is returned. This function must guarantee that all PCI
 478   read and write operations are serialized.
 479
 480   If Address > 0x0FFFFFFF, then ASSERT().
 481
 482   @param  Address Address that encodes the PCI Bus, Device, Function and
 483                   Register.
 484   @param  AndData The value to AND with the PCI configuration register.
 485   @param  OrData  The value to OR with the result of the AND operation.
 486
 487   @return The value written back to the PCI configuration register.
 488
 489 **/
 490 UINT16
 491 EFIAPI
 492 PciAndThenOr16 (
 493   IN      UINTN                     Address,
 494   IN      UINT16                    AndData,
 495   IN      UINT16                    OrData
 496   )
 497 {
 498   return PciExpressAndThenOr16 (Address, AndData, OrData);
 499 }
 500
 501 /**
 502   Reads a bit field of a PCI configuration register.
 503
 504   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 505   specified by the StartBit and the EndBit. The value of the bit field is
 506   returned.
 507
 508   If Address > 0x0FFFFFFF, then ASSERT().
 509   If StartBit is greater than 15, then ASSERT().
 510   If EndBit is greater than 15, then ASSERT().
 511   If EndBit is less than StartBit, then ASSERT().
 512
 513   @param  Address   PCI configuration register to read.
 514   @param  StartBit  The ordinal of the least significant bit in the bit field.
 515                     Range 0..15.
 516   @param  EndBit    The ordinal of the most significant bit in the bit field.
 517                     Range 0..15.
 518
 519   @return The value of the bit field read from the PCI configuration register.
 520
 521 **/
 522 UINT16
 523 EFIAPI
 524 PciBitFieldRead16 (
 525   IN      UINTN                     Address,
 526   IN      UINTN                     StartBit,
 527   IN      UINTN                     EndBit
 528   )
 529 {
 530   return PciExpressBitFieldRead16 (Address, StartBit, EndBit);
 531 }
 532
 533 /**
 534   Writes a bit field to a PCI configuration register.
 535
 536   Writes Value to the bit field of the PCI configuration register. The bit
 537   field is specified by the StartBit and the EndBit. All other bits in the
 538   destination PCI configuration register are preserved. The new value of the
 539   16-bit register is returned.
 540
 541   If Address > 0x0FFFFFFF, then ASSERT().
 542   If StartBit is greater than 15, then ASSERT().
 543   If EndBit is greater than 15, then ASSERT().
 544   If EndBit is less than StartBit, then ASSERT().
 545
 546   @param  Address   PCI configuration register to write.
 547   @param  StartBit  The ordinal of the least significant bit in the bit field.
 548                     Range 0..15.
 549   @param  EndBit    The ordinal of the most significant bit in the bit field.
 550                     Range 0..15.
 551   @param  Value     New value of the bit field.
 552
 553   @return The value written back to the PCI configuration register.
 554
 555 **/
 556 UINT16
 557 EFIAPI
 558 PciBitFieldWrite16 (
 559   IN      UINTN                     Address,
 560   IN      UINTN                     StartBit,
 561   IN      UINTN                     EndBit,
 562   IN      UINT16                    Value
 563   )
 564 {
 565   return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);
 566 }
 567
 568 /**
 569   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 570   writes the result back to the bit field in the 16-bit port.
 571
 572   Reads the 16-bit PCI configuration register specified by Address, performs a
 573   bitwise inclusive OR between the read result and the value specified by
 574   OrData, and writes the result to the 16-bit PCI configuration register
 575   specified by Address. The value written to the PCI configuration register is
 576   returned. This function must guarantee that all PCI read and write operations
 577   are serialized. Extra left bits in OrData are stripped.
 578
 579   If Address > 0x0FFFFFFF, then ASSERT().
 580   If StartBit is greater than 15, then ASSERT().
 581   If EndBit is greater than 15, then ASSERT().
 582   If EndBit is less than StartBit, then ASSERT().
 583
 584   @param  Address   PCI configuration register to write.
 585   @param  StartBit  The ordinal of the least significant bit in the bit field.
 586                     Range 0..15.
 587   @param  EndBit    The ordinal of the most significant bit in the bit field.
 588                     Range 0..15.
 589   @param  OrData    The value to OR with the PCI configuration register.
 590
 591   @return The value written back to the PCI configuration register.
 592
 593 **/
 594 UINT16
 595 EFIAPI
 596 PciBitFieldOr16 (
 597   IN      UINTN                     Address,
 598   IN      UINTN                     StartBit,
 599   IN      UINTN                     EndBit,
 600   IN      UINT16                    OrData
 601   )
 602 {
 603   return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);
 604 }
 605
 606 /**
 607   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 608   AND, and writes the result back to the bit field in the 16-bit register.
 609
 610   Reads the 16-bit PCI configuration register specified by Address, performs a
 611   bitwise AND between the read result and the value specified by AndData, and
 612   writes the result to the 16-bit PCI configuration register specified by
 613   Address. The value written to the PCI configuration register is returned.
 614   This function must guarantee that all PCI read and write operations are
 615   serialized. Extra left bits in AndData are stripped.
 616
 617   If Address > 0x0FFFFFFF, then ASSERT().
 618   If StartBit is greater than 15, then ASSERT().
 619   If EndBit is greater than 15, then ASSERT().
 620   If EndBit is less than StartBit, then ASSERT().
 621
 622   @param  Address   PCI configuration register to write.
 623   @param  StartBit  The ordinal of the least significant bit in the bit field.
 624                     Range 0..15.
 625   @param  EndBit    The ordinal of the most significant bit in the bit field.
 626                     Range 0..15.
 627   @param  AndData   The value to AND with the PCI configuration register.
 628
 629   @return The value written back to the PCI configuration register.
 630
 631 **/
 632 UINT16
 633 EFIAPI
 634 PciBitFieldAnd16 (
 635   IN      UINTN                     Address,
 636   IN      UINTN                     StartBit,
 637   IN      UINTN                     EndBit,
 638   IN      UINT16                    AndData
 639   )
 640 {
 641   return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);
 642 }
 643
 644 /**
 645   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 646   bitwise inclusive OR, and writes the result back to the bit field in the
 647   16-bit port.
 648
 649   Reads the 16-bit PCI configuration register specified by Address, performs a
 650   bitwise AND followed by a bitwise inclusive OR between the read result and
 651   the value specified by AndData, and writes the result to the 16-bit PCI
 652   configuration register specified by Address. The value written to the PCI
 653   configuration register is returned. This function must guarantee that all PCI
 654   read and write operations are serialized. Extra left bits in both AndData and
 655   OrData are stripped.
 656
 657   If Address > 0x0FFFFFFF, then ASSERT().
 658   If StartBit is greater than 15, then ASSERT().
 659   If EndBit is greater than 15, then ASSERT().
 660   If EndBit is less than StartBit, then ASSERT().
 661
 662   @param  Address   PCI configuration register to write.
 663   @param  StartBit  The ordinal of the least significant bit in the bit field.
 664                     Range 0..15.
 665   @param  EndBit    The ordinal of the most significant bit in the bit field.
 666                     Range 0..15.
 667   @param  AndData   The value to AND with the PCI configuration register.
 668   @param  OrData    The value to OR with the result of the AND operation.
 669
 670   @return The value written back to the PCI configuration register.
 671
 672 **/
 673 UINT16
 674 EFIAPI
 675 PciBitFieldAndThenOr16 (
 676   IN      UINTN                     Address,
 677   IN      UINTN                     StartBit,
 678   IN      UINTN                     EndBit,
 679   IN      UINT16                    AndData,
 680   IN      UINT16                    OrData
 681   )
 682 {
 683   return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);
 684 }
 685
 686 /**
 687   Reads a 32-bit PCI configuration register.
 688
 689   Reads and returns the 32-bit PCI configuration register specified by Address.
 690   This function must guarantee that all PCI read and write operations are
 691   serialized.
 692
 693   If Address > 0x0FFFFFFF, then ASSERT().
 694
 695   @param  Address Address that encodes the PCI Bus, Device, Function and
 696                   Register.
 697
 698   @return The read value from the PCI configuration register.
 699
 700 **/
 701 UINT32
 702 EFIAPI
 703 PciRead32 (
 704   IN      UINTN                     Address
 705   )
 706 {
 707   return PciExpressRead32 (Address);
 708 }
 709
 710 /**
 711   Writes a 32-bit PCI configuration register.
 712
 713   Writes the 32-bit PCI configuration register specified by Address with the
 714   value specified by Value. Value is returned. This function must guarantee
 715   that all PCI read and write operations are serialized.
 716
 717   If Address > 0x0FFFFFFF, then ASSERT().
 718
 719   @param  Address Address that encodes the PCI Bus, Device, Function and
 720                   Register.
 721   @param  Value   The value to write.
 722
 723   @return The value written to the PCI configuration register.
 724
 725 **/
 726 UINT32
 727 EFIAPI
 728 PciWrite32 (
 729   IN      UINTN                     Address,
 730   IN      UINT32                    Data
 731   )
 732 {
 733   return PciExpressWrite32 (Address, Data);
 734 }
 735
 736 /**
 737   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 738   a 32-bit value.
 739
 740   Reads the 32-bit PCI configuration register specified by Address, performs a
 741   bitwise inclusive OR between the read result and the value specified by
 742   OrData, and writes the result to the 32-bit PCI configuration register
 743   specified by Address. The value written to the PCI configuration register is
 744   returned. This function must guarantee that all PCI read and write operations
 745   are serialized.
 746
 747   If Address > 0x0FFFFFFF, then ASSERT().
 748
 749   @param  Address Address that encodes the PCI Bus, Device, Function and
 750                   Register.
 751   @param  OrData  The value to OR with the PCI configuration register.
 752
 753   @return The value written back to the PCI configuration register.
 754
 755 **/
 756 UINT32
 757 EFIAPI
 758 PciOr32 (
 759   IN      UINTN                     Address,
 760   IN      UINT32                    OrData
 761   )
 762 {
 763   return PciExpressOr32 (Address, OrData);
 764 }
 765
 766 /**
 767   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 768   value.
 769
 770   Reads the 32-bit PCI configuration register specified by Address, performs a
 771   bitwise AND between the read result and the value specified by AndData, and
 772   writes the result to the 32-bit PCI configuration register specified by
 773   Address. The value written to the PCI configuration register is returned.
 774   This function must guarantee that all PCI read and write operations are
 775   serialized.
 776
 777   If Address > 0x0FFFFFFF, then ASSERT().
 778
 779   @param  Address Address that encodes the PCI Bus, Device, Function and
 780                   Register.
 781   @param  AndData The value to AND with the PCI configuration register.
 782
 783   @return The value written back to the PCI configuration register.
 784
 785 **/
 786 UINT32
 787 EFIAPI
 788 PciAnd32 (
 789   IN      UINTN                     Address,
 790   IN      UINT32                    AndData
 791   )
 792 {
 793   return PciExpressAnd32 (Address, AndData);
 794 }
 795
 796 /**
 797   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 798   value, followed a  bitwise inclusive OR with another 32-bit value.
 799
 800   Reads the 32-bit PCI configuration register specified by Address, performs a
 801   bitwise AND between the read result and the value specified by AndData,
 802   performs a bitwise inclusive OR between the result of the AND operation and
 803   the value specified by OrData, and writes the result to the 32-bit PCI
 804   configuration register specified by Address. The value written to the PCI
 805   configuration register is returned. This function must guarantee that all PCI
 806   read and write operations are serialized.
 807
 808   If Address > 0x0FFFFFFF, then ASSERT().
 809
 810   @param  Address Address that encodes the PCI Bus, Device, Function and
 811                   Register.
 812   @param  AndData The value to AND with the PCI configuration register.
 813   @param  OrData  The value to OR with the result of the AND operation.
 814
 815   @return The value written back to the PCI configuration register.
 816
 817 **/
 818 UINT32
 819 EFIAPI
 820 PciAndThenOr32 (
 821   IN      UINTN                     Address,
 822   IN      UINT32                    AndData,
 823   IN      UINT32                    OrData
 824   )
 825 {
 826   return PciExpressAndThenOr32 (Address, AndData, OrData);
 827 }
 828
 829 /**
 830   Reads a bit field of a PCI configuration register.
 831
 832   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 833   specified by the StartBit and the EndBit. The value of the bit field is
 834   returned.
 835
 836   If Address > 0x0FFFFFFF, then ASSERT().
 837   If StartBit is greater than 31, then ASSERT().
 838   If EndBit is greater than 31, then ASSERT().
 839   If EndBit is less than StartBit, then ASSERT().
 840
 841   @param  Address   PCI configuration register to read.
 842   @param  StartBit  The ordinal of the least significant bit in the bit field.
 843                     Range 0..31.
 844   @param  EndBit    The ordinal of the most significant bit in the bit field.
 845                     Range 0..31.
 846
 847   @return The value of the bit field read from the PCI configuration register.
 848
 849 **/
 850 UINT32
 851 EFIAPI
 852 PciBitFieldRead32 (
 853   IN      UINTN                     Address,
 854   IN      UINTN                     StartBit,
 855   IN      UINTN                     EndBit
 856   )
 857 {
 858   return PciExpressBitFieldRead32 (Address, StartBit, EndBit);
 859 }
 860
 861 /**
 862   Writes a bit field to a PCI configuration register.
 863
 864   Writes Value to the bit field of the PCI configuration register. The bit
 865   field is specified by the StartBit and the EndBit. All other bits in the
 866   destination PCI configuration register are preserved. The new value of the
 867   32-bit register is returned.
 868
 869   If Address > 0x0FFFFFFF, then ASSERT().
 870   If StartBit is greater than 31, then ASSERT().
 871   If EndBit is greater than 31, then ASSERT().
 872   If EndBit is less than StartBit, then ASSERT().
 873
 874   @param  Address   PCI configuration register to write.
 875   @param  StartBit  The ordinal of the least significant bit in the bit field.
 876                     Range 0..31.
 877   @param  EndBit    The ordinal of the most significant bit in the bit field.
 878                     Range 0..31.
 879   @param  Value     New value of the bit field.
 880
 881   @return The value written back to the PCI configuration register.
 882
 883 **/
 884 UINT32
 885 EFIAPI
 886 PciBitFieldWrite32 (
 887   IN      UINTN                     Address,
 888   IN      UINTN                     StartBit,
 889   IN      UINTN                     EndBit,
 890   IN      UINT32                    Value
 891   )
 892 {
 893   return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);
 894 }
 895
 896 /**
 897   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 898   writes the result back to the bit field in the 32-bit port.
 899
 900   Reads the 32-bit PCI configuration register specified by Address, performs a
 901   bitwise inclusive OR between the read result and the value specified by
 902   OrData, and writes the result to the 32-bit PCI configuration register
 903   specified by Address. The value written to the PCI configuration register is
 904   returned. This function must guarantee that all PCI read and write operations
 905   are serialized. Extra left bits in OrData are stripped.
 906
 907   If Address > 0x0FFFFFFF, then ASSERT().
 908   If StartBit is greater than 31, then ASSERT().
 909   If EndBit is greater than 31, then ASSERT().
 910   If EndBit is less than StartBit, then ASSERT().
 911
 912   @param  Address   PCI configuration register to write.
 913   @param  StartBit  The ordinal of the least significant bit in the bit field.
 914                     Range 0..31.
 915   @param  EndBit    The ordinal of the most significant bit in the bit field.
 916                     Range 0..31.
 917   @param  OrData    The value to OR with the PCI configuration register.
 918
 919   @return The value written back to the PCI configuration register.
 920
 921 **/
 922 UINT32
 923 EFIAPI
 924 PciBitFieldOr32 (
 925   IN      UINTN                     Address,
 926   IN      UINTN                     StartBit,
 927   IN      UINTN                     EndBit,
 928   IN      UINT32                    OrData
 929   )
 930 {
 931   return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);
 932 }
 933
 934 /**
 935   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 936   AND, and writes the result back to the bit field in the 32-bit register.
 937
 938   Reads the 32-bit PCI configuration register specified by Address, performs a
 939   bitwise AND between the read result and the value specified by AndData, and
 940   writes the result to the 32-bit PCI configuration register specified by
 941   Address. The value written to the PCI configuration register is returned.
 942   This function must guarantee that all PCI read and write operations are
 943   serialized. Extra left bits in AndData are stripped.
 944
 945   If Address > 0x0FFFFFFF, then ASSERT().
 946   If StartBit is greater than 31, then ASSERT().
 947   If EndBit is greater than 31, then ASSERT().
 948   If EndBit is less than StartBit, then ASSERT().
 949
 950   @param  Address   PCI configuration register to write.
 951   @param  StartBit  The ordinal of the least significant bit in the bit field.
 952                     Range 0..31.
 953   @param  EndBit    The ordinal of the most significant bit in the bit field.
 954                     Range 0..31.
 955   @param  AndData   The value to AND with the PCI configuration register.
 956
 957   @return The value written back to the PCI configuration register.
 958
 959 **/
 960 UINT32
 961 EFIAPI
 962 PciBitFieldAnd32 (
 963   IN      UINTN                     Address,
 964   IN      UINTN                     StartBit,
 965   IN      UINTN                     EndBit,
 966   IN      UINT32                    AndData
 967   )
 968 {
 969   return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);
 970 }
 971
 972 /**
 973   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 974   bitwise inclusive OR, and writes the result back to the bit field in the
 975   32-bit port.
 976
 977   Reads the 32-bit PCI configuration register specified by Address, performs a
 978   bitwise AND followed by a bitwise inclusive OR between the read result and
 979   the value specified by AndData, and writes the result to the 32-bit PCI
 980   configuration register specified by Address. The value written to the PCI
 981   configuration register is returned. This function must guarantee that all PCI
 982   read and write operations are serialized. Extra left bits in both AndData and
 983   OrData are stripped.
 984
 985   If Address > 0x0FFFFFFF, then ASSERT().
 986   If StartBit is greater than 31, then ASSERT().
 987   If EndBit is greater than 31, then ASSERT().
 988   If EndBit is less than StartBit, then ASSERT().
 989
 990   @param  Address   PCI configuration register to write.
 991   @param  StartBit  The ordinal of the least significant bit in the bit field.
 992                     Range 0..31.
 993   @param  EndBit    The ordinal of the most significant bit in the bit field.
 994                     Range 0..31.
 995   @param  AndData   The value to AND with the PCI configuration register.
 996   @param  OrData    The value to OR with the result of the AND operation.
 997
 998   @return The value written back to the PCI configuration register.
 999
1000 **/
1001 UINT32
1002 EFIAPI
1003 PciBitFieldAndThenOr32 (
1004   IN      UINTN                     Address,
1005   IN      UINTN                     StartBit,
1006   IN      UINTN                     EndBit,
1007   IN      UINT32                    AndData,
1008   IN      UINT32                    OrData
1009   )
1010 {
1011   return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);
1012 }
1013
1014 /**
1015   Reads a range of PCI configuration registers into a caller supplied buffer.
1016
1017   Reads the range of PCI configuration registers specified by StartAddress and
1018   Size into the buffer specified by Buffer. This function only allows the PCI
1019   configuration registers from a single PCI function to be read. Size is
1020   returned. When possible 32-bit PCI configuration read cycles are used to read
1021   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1022   and 16-bit PCI configuration read cycles may be used at the beginning and the
1023   end of the range.
1024
1025   If StartAddress > 0x0FFFFFFF, then ASSERT().
1026   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1027   If Size > 0 and Buffer is NULL, then ASSERT().
1028
1029   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1030                         Function and Register.
1031   @param  Size          Size in bytes of the transfer.
1032   @param  Buffer        Pointer to a buffer receiving the data read.
1033
1034   @return Size
1035
1036 **/
1037 UINTN
1038 EFIAPI
1039 PciReadBuffer (
1040   IN      UINTN                     StartAddress,
1041   IN      UINTN                     Size,
1042   OUT     VOID                      *Buffer
1043   )
1044 {
1045   return PciExpressReadBuffer (StartAddress, Size, Buffer);
1046 }
1047
1048 /**
1049   Copies the data in a caller supplied buffer to a specified range of PCI
1050   configuration space.
1051
1052   Writes the range of PCI configuration registers specified by StartAddress and
1053   Size from the buffer specified by Buffer. This function only allows the PCI
1054   configuration registers from a single PCI function to be written. Size is
1055   returned. When possible 32-bit PCI configuration write cycles are used to
1056   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1057   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1058   and the end of the range.
1059
1060   If StartAddress > 0x0FFFFFFF, then ASSERT().
1061   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1062   If Size > 0 and Buffer is NULL, then ASSERT().
1063
1064   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1065                         Function and Register.
1066   @param  Size          Size in bytes of the transfer.
1067   @param  Buffer        Pointer to a buffer containing the data to write.
1068
1069   @return Size
1070
1071 **/
1072 UINTN
1073 EFIAPI
1074 PciWriteBuffer (
1075   IN      UINTN                     StartAddress,
1076   IN      UINTN                     Size,
1077   IN      VOID                      *Buffer
1078   )
1079 {
1080   return PciExpressWriteBuffer (StartAddress, Size, Buffer);
1081 }