MdePkg/Library/BaseSmbusLib/SmbusLibRegisters.h

   1 /** @file
   2   Base SMBUS library implementation built upon I/O library.
   3
   4   Copyright (c) 2006, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13   Module Name:  SmbusLib.h
  14
  15 **/
  16
  17 #ifndef __SMBUS_LIB_REGISTER_H
  18 #define __SMBUS_LIB_REGISTER_H
  19
  20 #define SMBUS_R_HST_STS               0x00  // Host Status Register
  21 #define SMBUS_B_HOST_BUSY             0x01  // RO
  22 #define SMBUS_B_INTR                  0x02  // R/WC
  23 #define SMBUS_B_DEV_ERR               0x04  // R/WC
  24 #define SMBUS_B_BUS_ERR               0x08  // R/WC
  25 #define SMBUS_B_FAILED                0x10  // R/WC
  26 #define SMBUS_B_SMBALERT_STS          0x20  // R/WC
  27 #define SMBUS_B_INUSE_STS             0x40  // R/WC
  28 #define SMBUS_B_BYTE_DONE_STS         0x80  // R/WC
  29 #define SMBUS_B_ERROR                 (SMBUS_B_DEV_ERR | SMBUS_B_BUS_ERR | SMBUS_B_FAILED)
  30 #define SMBUS_B_HSTS_ALL              0xFF  // R/WC
  31
  32
  33 #define SMBUS_R_HST_CTL               0x02  // Host Control Register R/W
  34 #define SMBUS_B_INTREN                0x01  // RW
  35 #define SMBUS_B_KILL                  0x02  // RW
  36 #define SMBUS_B_CMD                   (7 << 2) // RW
  37 #define SMBUS_V_SMB_CMD_QUICK         (0 << 2)
  38 #define SMBUS_V_SMB_CMD_BYTE          (1 << 2)
  39 #define SMBUS_V_SMB_CMD_BYTE_DATA     (2 << 2)
  40 #define SMBUS_V_SMB_CMD_WORD_DATA     (3 << 2)
  41 #define SMBUS_V_SMB_CMD_PROCESS_CALL  (4 << 2)
  42 #define SMBUS_V_SMB_CMD_BLOCK         (5 << 2)
  43 #define SMBUS_V_SMB_CMD_IIC_READ      (6 << 2)
  44 #define SMBUS_V_SMB_CMD_BLOCK_PROCESS (7 << 2)
  45 #define SMBUS_B_LAST_BYTE             0x20  // WO
  46 #define SMBUS_B_START                 0x40  // WO
  47 #define SMBUS_B_PEC_EN                0x80  // RW
  48
  49
  50 #define SMBUS_R_HST_CMD               0x03  // Host Command Register R/W
  51
  52
  53 #define SMBUS_R_XMIT_SLVA             0x04  // Transmit Slave Address Register R/W
  54 #define SMBUS_B_RW                    0x01  // RW
  55 #define SMBUS_B_READ                  0x01  // RW
  56 #define SMBUS_B_WRITE                 0x00  // RW
  57 #define SMBUS_B_ADDRESS               0xFE  // RW
  58
  59
  60 #define SMBUS_R_HST_D0                0x05  // Data 0 Register R/W
  61
  62
  63 #define SMBUS_R_HST_D1                0x06  // Data 1 Register R/W
  64
  65
  66 #define SMBUS_R_HOST_BLOCK_DB         0x07  // Host Block Data Register R/W
  67
  68
  69 #define SMBUS_R_PEC                   0x08  // Packet Error Check Data Register R/W
  70
  71
  72 #define SMBUS_R_RCV_SLVA              0x09  // Receive Slave Address Register R/W
  73 #define SMBUS_B_SLAVE_ADDR            0x7F  // RW
  74
  75
  76 #define SMBUS_R_SLV_DATA              0x0A  // Receive Slave Data Register R/W
  77
  78
  79 #define SMBUS_R_AUX_STS               0x0C  // Auxiliary Status Register R/WC
  80 #define SMBUS_B_CRCE                  0x01  // R/WC
  81
  82
  83 #define SMBUS_R_AUX_CTL               0x0D  // Auxiliary Control Register R/W
  84 #define SMBUS_B_AAC                   0x01  // R/W
  85 #define SMBUS_B_E32B                  0x02  // R/W
  86
  87
  88 #define SMBUS_R_SMLINK_PIN_CTL        0x0E  // SMLINK Pin Control Register R/W
  89 #define SMBUS_B_SMLINK0_CUR_STS       0x01  // RO
  90 #define SMBUS_B_SMLINK1_CUR_STS       0x02  // RO
  91 #define SMBUS_B_SMLINK_CLK_CTL        0x04  // RW
  92
  93
  94 #define SMBUS_R_SMBUS_PIN_CTL         0x0F  // SMBus Pin Control Register R/W
  95 #define SMBUS_B_SMBCLK_CUR_STS        0x01  // RO
  96 #define SMBUS_B_SMBDATA_CUR_STS       0x02  // RO
  97 #define SMBUS_B_SMBCLK_CTL            0x04  // RW
  98
  99
 100 #define SMBUS_R_SLV_STS               0x10  // Slave Status Register R/WC
 101 #define SMBUS_B_HOST_NOTIFY_STS       0x01  // R/WC
 102
 103
 104 #define SMBUS_R_SLV_CMD               0x11  // Slave Command Register R/W
 105 #define SMBUS_B_HOST_NOTIFY_INTREN    0x01  // R/W
 106 #define SMBUS_B_HOST_NOTIFY_WKEN      0x02  // R/W
 107 #define SMBUS_B_SMBALERT_DIS          0x04  // R/W
 108
 109
 110 #define SMBUS_R_NOTIFY_DADDR          0x14  // Notify Device Address Register RO
 111 #define SMBUS_B_DEVICE_ADDRESS        0xFE  // RO
 112
 113
 114 #define SMBUS_R_NOTIFY_DLOW           0x16  // Notify Data Low Byte Register RO
 115
 116
 117 #define SMBUS_R_NOTIFY_DHIGH          0x17  // Notify Data High Byte Register RO
 118
 119
 120 #endif