2 PCI Segment Library implementation using PCI CFG2 PPI.
4 Copyright (c) 2007 - 2008, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Ppi/PciCfg2.h>
20 #include <Library/PciSegmentLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/PeiServicesTablePointerLib.h>
23 #include <Library/DebugLib.h>
24 #include <Library/PeiServicesLib.h>
27 Assert the validity of a PCI Segment address.
28 A valid PCI Segment address should not contain 1's in bits 31:28
30 @param A The address to validate.
31 @param M Additional bits to assert to be zero.
34 #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
35 ASSERT (((A) & (0xf0000000 | (M))) == 0)
38 Translate PCI Lib address into format of PCI CFG2 PPI.
40 @param A Address that encodes the PCI Bus, Device, Function and
44 #define PCI_TO_PCICFG2_ADDRESS(A) \
45 ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
50 This internal function retrieves PCI CFG2 PPI from PPI database.
52 @param Address Address that encodes the PCI Segment, Bus, Device, Function and Register.
54 @return The pointer to PCI CFG2 PPI.
57 EFI_PEI_PCI_CFG2_PPI
*
58 InternalGetPciCfg2Ppi (
64 EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
69 SegmentNumber
= BitFieldRead64 (Address
, 32, 63);
72 // Loop through all instances of the PPI and match segment number
75 Status
= PeiServicesLocatePpi(
81 ASSERT_EFI_ERROR (Status
);
83 } while (PciCfg2Ppi
->Segment
!= SegmentNumber
);
89 Internal worker function to read a PCI configuration register.
91 This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.
92 It reads and returns the PCI configuration register specified by Address,
93 the width of data is specified by Width.
95 @param Address Address that encodes the PCI Bus, Device, Function and
97 @param Width Width of data to read
99 @return The value read from the PCI configuration register.
103 PeiPciSegmentLibPciCfg2ReadWorker (
105 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
109 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
111 PciCfg2Ppi
= InternalGetPciCfg2Ppi (Address
);
114 GetPeiServicesTablePointer (),
117 PCI_TO_PCICFG2_ADDRESS (Address
),
125 Internal worker function to writes a PCI configuration register.
127 This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.
128 It writes the PCI configuration register specified by Address with the
129 value specified by Data. The width of data is specifed by Width.
132 @param Address Address that encodes the PCI Bus, Device, Function and
134 @param Width Width of data to write
135 @param Data The value to write.
137 @return The value written to the PCI configuration register.
141 PeiPciSegmentLibPciCfg2WriteWorker (
143 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
,
147 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
149 PciCfg2Ppi
= InternalGetPciCfg2Ppi (Address
);
152 GetPeiServicesTablePointer (),
155 PCI_TO_PCICFG2_ADDRESS (Address
),
163 Register a PCI device so PCI configuration registers may be accessed after
164 SetVirtualAddressMap().
166 If Address > 0x0FFFFFFF, then ASSERT().
168 @param Address Address that encodes the PCI Bus, Device, Function and
171 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
172 @retval RETURN_UNSUPPORTED An attempt was made to call this function
173 after ExitBootServices().
174 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
175 at runtime could not be mapped.
176 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
177 complete the registration.
182 PciSegmentRegisterForRuntimeAccess (
186 return RETURN_UNSUPPORTED
;
190 Reads an 8-bit PCI configuration register.
192 Reads and returns the 8-bit PCI configuration register specified by Address.
193 This function must guarantee that all PCI read and write operations are
196 If any reserved bits in Address are set, then ASSERT().
198 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
201 @return The value read from the PCI configuration register.
210 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 0);
212 return (UINT8
) PeiPciSegmentLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint8
);
216 Writes an 8-bit PCI configuration register.
218 Writes the 8-bit PCI configuration register specified by Address with the
219 value specified by Value. Value is returned. This function must guarantee
220 that all PCI read and write operations are serialized.
222 If any reserved bits in Address are set, then ASSERT().
224 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
226 @param Data The value to write.
228 @return The value written to the PCI configuration register.
238 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 0);
240 return (UINT8
) PeiPciSegmentLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint8
, Data
);
244 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
247 Reads the 8-bit PCI configuration register specified by Address, performs a
248 bitwise inclusive OR between the read result and the value specified by
249 OrData, and writes the result to the 8-bit PCI configuration register
250 specified by Address. The value written to the PCI configuration register is
251 returned. This function must guarantee that all PCI read and write operations
254 If any reserved bits in Address are set, then ASSERT().
256 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
258 @param OrData The value to OR with the PCI configuration register.
260 @return The value written back to the PCI configuration register.
270 return PciSegmentWrite8 (Address
, (UINT8
) (PciSegmentRead8 (Address
) | OrData
));
274 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
277 Reads the 8-bit PCI configuration register specified by Address, performs a
278 bitwise AND between the read result and the value specified by AndData, and
279 writes the result to the 8-bit PCI configuration register specified by
280 Address. The value written to the PCI configuration register is returned.
281 This function must guarantee that all PCI read and write operations are
284 If any reserved bits in Address are set, then ASSERT().
286 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
288 @param AndData The value to AND with the PCI configuration register.
290 @return The value written back to the PCI configuration register.
300 return PciSegmentWrite8 (Address
, (UINT8
) (PciSegmentRead8 (Address
) & AndData
));
304 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
305 value, followed a bitwise inclusive OR with another 8-bit value.
307 Reads the 8-bit PCI configuration register specified by Address, performs a
308 bitwise AND between the read result and the value specified by AndData,
309 performs a bitwise inclusive OR between the result of the AND operation and
310 the value specified by OrData, and writes the result to the 8-bit PCI
311 configuration register specified by Address. The value written to the PCI
312 configuration register is returned. This function must guarantee that all PCI
313 read and write operations are serialized.
315 If any reserved bits in Address are set, then ASSERT().
317 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
319 @param AndData The value to AND with the PCI configuration register.
320 @param OrData The value to OR with the result of the AND operation.
322 @return The value written back to the PCI configuration register.
327 PciSegmentAndThenOr8 (
333 return PciSegmentWrite8 (Address
, (UINT8
) ((PciSegmentRead8 (Address
) & AndData
) | OrData
));
337 Reads a bit field of a PCI configuration register.
339 Reads the bit field in an 8-bit PCI configuration register. The bit field is
340 specified by the StartBit and the EndBit. The value of the bit field is
343 If any reserved bits in Address are set, then ASSERT().
344 If StartBit is greater than 7, then ASSERT().
345 If EndBit is greater than 7, then ASSERT().
346 If EndBit is less than StartBit, then ASSERT().
348 @param Address PCI configuration register to read.
349 @param StartBit The ordinal of the least significant bit in the bit field.
351 @param EndBit The ordinal of the most significant bit in the bit field.
354 @return The value of the bit field read from the PCI configuration register.
359 PciSegmentBitFieldRead8 (
365 return BitFieldRead8 (PciSegmentRead8 (Address
), StartBit
, EndBit
);
369 Writes a bit field to a PCI configuration register.
371 Writes Value to the bit field of the PCI configuration register. The bit
372 field is specified by the StartBit and the EndBit. All other bits in the
373 destination PCI configuration register are preserved. The new value of the
374 8-bit register is returned.
376 If any reserved bits in Address are set, then ASSERT().
377 If StartBit is greater than 7, then ASSERT().
378 If EndBit is greater than 7, then ASSERT().
379 If EndBit is less than StartBit, then ASSERT().
381 @param Address PCI configuration register to write.
382 @param StartBit The ordinal of the least significant bit in the bit field.
384 @param EndBit The ordinal of the most significant bit in the bit field.
386 @param Value New value of the bit field.
388 @return The value written back to the PCI configuration register.
393 PciSegmentBitFieldWrite8 (
400 return PciSegmentWrite8 (
402 BitFieldWrite8 (PciSegmentRead8 (Address
), StartBit
, EndBit
, Value
)
407 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
408 writes the result back to the bit field in the 8-bit port.
410 Reads the 8-bit PCI configuration register specified by Address, performs a
411 bitwise inclusive OR between the read result and the value specified by
412 OrData, and writes the result to the 8-bit PCI configuration register
413 specified by Address. The value written to the PCI configuration register is
414 returned. This function must guarantee that all PCI read and write operations
415 are serialized. Extra left bits in OrData are stripped.
417 If any reserved bits in Address are set, then ASSERT().
418 If StartBit is greater than 7, then ASSERT().
419 If EndBit is greater than 7, then ASSERT().
420 If EndBit is less than StartBit, then ASSERT().
422 @param Address PCI configuration register to write.
423 @param StartBit The ordinal of the least significant bit in the bit field.
425 @param EndBit The ordinal of the most significant bit in the bit field.
427 @param OrData The value to OR with the PCI configuration register.
429 @return The value written back to the PCI configuration register.
434 PciSegmentBitFieldOr8 (
441 return PciSegmentWrite8 (
443 BitFieldOr8 (PciSegmentRead8 (Address
), StartBit
, EndBit
, OrData
)
448 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
449 AND, and writes the result back to the bit field in the 8-bit register.
451 Reads the 8-bit PCI configuration register specified by Address, performs a
452 bitwise AND between the read result and the value specified by AndData, and
453 writes the result to the 8-bit PCI configuration register specified by
454 Address. The value written to the PCI configuration register is returned.
455 This function must guarantee that all PCI read and write operations are
456 serialized. Extra left bits in AndData are stripped.
458 If any reserved bits in Address are set, then ASSERT().
459 If StartBit is greater than 7, then ASSERT().
460 If EndBit is greater than 7, then ASSERT().
461 If EndBit is less than StartBit, then ASSERT().
463 @param Address PCI configuration register to write.
464 @param StartBit The ordinal of the least significant bit in the bit field.
466 @param EndBit The ordinal of the most significant bit in the bit field.
468 @param AndData The value to AND with the PCI configuration register.
470 @return The value written back to the PCI configuration register.
475 PciSegmentBitFieldAnd8 (
482 return PciSegmentWrite8 (
484 BitFieldAnd8 (PciSegmentRead8 (Address
), StartBit
, EndBit
, AndData
)
489 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
490 bitwise inclusive OR, and writes the result back to the bit field in the
493 Reads the 8-bit PCI configuration register specified by Address, performs a
494 bitwise AND followed by a bitwise inclusive OR between the read result and
495 the value specified by AndData, and writes the result to the 8-bit PCI
496 configuration register specified by Address. The value written to the PCI
497 configuration register is returned. This function must guarantee that all PCI
498 read and write operations are serialized. Extra left bits in both AndData and
501 If any reserved bits in Address are set, then ASSERT().
502 If StartBit is greater than 7, then ASSERT().
503 If EndBit is greater than 7, then ASSERT().
504 If EndBit is less than StartBit, then ASSERT().
506 @param Address PCI configuration register to write.
507 @param StartBit The ordinal of the least significant bit in the bit field.
509 @param EndBit The ordinal of the most significant bit in the bit field.
511 @param AndData The value to AND with the PCI configuration register.
512 @param OrData The value to OR with the result of the AND operation.
514 @return The value written back to the PCI configuration register.
519 PciSegmentBitFieldAndThenOr8 (
527 return PciSegmentWrite8 (
529 BitFieldAndThenOr8 (PciSegmentRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
534 Reads a 16-bit PCI configuration register.
536 Reads and returns the 16-bit PCI configuration register specified by Address.
537 This function must guarantee that all PCI read and write operations are
540 If any reserved bits in Address are set, then ASSERT().
542 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
545 @return The value read from the PCI configuration register.
554 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 1);
556 return (UINT16
) PeiPciSegmentLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint16
);
560 Writes a 16-bit PCI configuration register.
562 Writes the 16-bit PCI configuration register specified by Address with the
563 value specified by Value. Value is returned. This function must guarantee
564 that all PCI read and write operations are serialized.
566 If any reserved bits in Address are set, then ASSERT().
568 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
570 @param Data The value to write.
572 @return The value written to the PCI configuration register.
582 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 1);
584 return (UINT16
) PeiPciSegmentLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint16
, Data
);
588 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
591 Reads the 16-bit PCI configuration register specified by Address, performs a
592 bitwise inclusive OR between the read result and the value specified by
593 OrData, and writes the result to the 16-bit PCI configuration register
594 specified by Address. The value written to the PCI configuration register is
595 returned. This function must guarantee that all PCI read and write operations
598 If any reserved bits in Address are set, then ASSERT().
600 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
602 @param OrData The value to OR with the PCI configuration register.
604 @return The value written back to the PCI configuration register.
614 return PciSegmentWrite16 (Address
, (UINT16
) (PciSegmentRead16 (Address
) | OrData
));
618 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
621 Reads the 16-bit PCI configuration register specified by Address, performs a
622 bitwise AND between the read result and the value specified by AndData, and
623 writes the result to the 16-bit PCI configuration register specified by
624 Address. The value written to the PCI configuration register is returned.
625 This function must guarantee that all PCI read and write operations are
628 If any reserved bits in Address are set, then ASSERT().
630 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
632 @param AndData The value to AND with the PCI configuration register.
634 @return The value written back to the PCI configuration register.
644 return PciSegmentWrite16 (Address
, (UINT16
) (PciSegmentRead16 (Address
) & AndData
));
648 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
649 value, followed a bitwise inclusive OR with another 16-bit value.
651 Reads the 16-bit PCI configuration register specified by Address, performs a
652 bitwise AND between the read result and the value specified by AndData,
653 performs a bitwise inclusive OR between the result of the AND operation and
654 the value specified by OrData, and writes the result to the 16-bit PCI
655 configuration register specified by Address. The value written to the PCI
656 configuration register is returned. This function must guarantee that all PCI
657 read and write operations are serialized.
659 If any reserved bits in Address are set, then ASSERT().
661 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
663 @param AndData The value to AND with the PCI configuration register.
664 @param OrData The value to OR with the result of the AND operation.
666 @return The value written back to the PCI configuration register.
671 PciSegmentAndThenOr16 (
677 return PciSegmentWrite16 (Address
, (UINT16
) ((PciSegmentRead16 (Address
) & AndData
) | OrData
));
681 Reads a bit field of a PCI configuration register.
683 Reads the bit field in a 16-bit PCI configuration register. The bit field is
684 specified by the StartBit and the EndBit. The value of the bit field is
687 If any reserved bits in Address are set, then ASSERT().
688 If StartBit is greater than 15, then ASSERT().
689 If EndBit is greater than 15, then ASSERT().
690 If EndBit is less than StartBit, then ASSERT().
692 @param Address PCI configuration register to read.
693 @param StartBit The ordinal of the least significant bit in the bit field.
695 @param EndBit The ordinal of the most significant bit in the bit field.
698 @return The value of the bit field read from the PCI configuration register.
703 PciSegmentBitFieldRead16 (
709 return BitFieldRead16 (PciSegmentRead16 (Address
), StartBit
, EndBit
);
713 Writes a bit field to a PCI configuration register.
715 Writes Value to the bit field of the PCI configuration register. The bit
716 field is specified by the StartBit and the EndBit. All other bits in the
717 destination PCI configuration register are preserved. The new value of the
718 16-bit register is returned.
720 If any reserved bits in Address are set, then ASSERT().
721 If StartBit is greater than 15, then ASSERT().
722 If EndBit is greater than 15, then ASSERT().
723 If EndBit is less than StartBit, then ASSERT().
725 @param Address PCI configuration register to write.
726 @param StartBit The ordinal of the least significant bit in the bit field.
728 @param EndBit The ordinal of the most significant bit in the bit field.
730 @param Value New value of the bit field.
732 @return The value written back to the PCI configuration register.
737 PciSegmentBitFieldWrite16 (
744 return PciSegmentWrite16 (
746 BitFieldWrite16 (PciSegmentRead16 (Address
), StartBit
, EndBit
, Value
)
751 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
752 writes the result back to the bit field in the 16-bit port.
754 Reads the 16-bit PCI configuration register specified by Address, performs a
755 bitwise inclusive OR between the read result and the value specified by
756 OrData, and writes the result to the 16-bit PCI configuration register
757 specified by Address. The value written to the PCI configuration register is
758 returned. This function must guarantee that all PCI read and write operations
759 are serialized. Extra left bits in OrData are stripped.
761 If any reserved bits in Address are set, then ASSERT().
762 If StartBit is greater than 15, then ASSERT().
763 If EndBit is greater than 15, then ASSERT().
764 If EndBit is less than StartBit, then ASSERT().
766 @param Address PCI configuration register to write.
767 @param StartBit The ordinal of the least significant bit in the bit field.
769 @param EndBit The ordinal of the most significant bit in the bit field.
771 @param OrData The value to OR with the PCI configuration register.
773 @return The value written back to the PCI configuration register.
778 PciSegmentBitFieldOr16 (
785 return PciSegmentWrite16 (
787 BitFieldOr16 (PciSegmentRead16 (Address
), StartBit
, EndBit
, OrData
)
792 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
793 AND, and writes the result back to the bit field in the 16-bit register.
795 Reads the 16-bit PCI configuration register specified by Address, performs a
796 bitwise AND between the read result and the value specified by AndData, and
797 writes the result to the 16-bit PCI configuration register specified by
798 Address. The value written to the PCI configuration register is returned.
799 This function must guarantee that all PCI read and write operations are
800 serialized. Extra left bits in AndData are stripped.
802 If any reserved bits in Address are set, then ASSERT().
803 If StartBit is greater than 15, then ASSERT().
804 If EndBit is greater than 15, then ASSERT().
805 If EndBit is less than StartBit, then ASSERT().
807 @param Address PCI configuration register to write.
808 @param StartBit The ordinal of the least significant bit in the bit field.
810 @param EndBit The ordinal of the most significant bit in the bit field.
812 @param AndData The value to AND with the PCI configuration register.
814 @return The value written back to the PCI configuration register.
819 PciSegmentBitFieldAnd16 (
826 return PciSegmentWrite16 (
828 BitFieldAnd16 (PciSegmentRead16 (Address
), StartBit
, EndBit
, AndData
)
833 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
834 bitwise inclusive OR, and writes the result back to the bit field in the
837 Reads the 16-bit PCI configuration register specified by Address, performs a
838 bitwise AND followed by a bitwise inclusive OR between the read result and
839 the value specified by AndData, and writes the result to the 16-bit PCI
840 configuration register specified by Address. The value written to the PCI
841 configuration register is returned. This function must guarantee that all PCI
842 read and write operations are serialized. Extra left bits in both AndData and
845 If any reserved bits in Address are set, then ASSERT().
846 If StartBit is greater than 15, then ASSERT().
847 If EndBit is greater than 15, then ASSERT().
848 If EndBit is less than StartBit, then ASSERT().
850 @param Address PCI configuration register to write.
851 @param StartBit The ordinal of the least significant bit in the bit field.
853 @param EndBit The ordinal of the most significant bit in the bit field.
855 @param AndData The value to AND with the PCI configuration register.
856 @param OrData The value to OR with the result of the AND operation.
858 @return The value written back to the PCI configuration register.
863 PciSegmentBitFieldAndThenOr16 (
871 return PciSegmentWrite16 (
873 BitFieldAndThenOr16 (PciSegmentRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
878 Reads a 32-bit PCI configuration register.
880 Reads and returns the 32-bit PCI configuration register specified by Address.
881 This function must guarantee that all PCI read and write operations are
884 If any reserved bits in Address are set, then ASSERT().
886 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
889 @return The value read from the PCI configuration register.
898 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 3);
900 return PeiPciSegmentLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint32
);
904 Writes a 32-bit PCI configuration register.
906 Writes the 32-bit PCI configuration register specified by Address with the
907 value specified by Value. Value is returned. This function must guarantee
908 that all PCI read and write operations are serialized.
910 If any reserved bits in Address are set, then ASSERT().
912 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
914 @param Data The value to write.
916 @return The value written to the PCI configuration register.
926 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 3);
928 return PeiPciSegmentLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint32
, Data
);
932 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
935 Reads the 32-bit PCI configuration register specified by Address, performs a
936 bitwise inclusive OR between the read result and the value specified by
937 OrData, and writes the result to the 32-bit PCI configuration register
938 specified by Address. The value written to the PCI configuration register is
939 returned. This function must guarantee that all PCI read and write operations
942 If any reserved bits in Address are set, then ASSERT().
944 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
946 @param OrData The value to OR with the PCI configuration register.
948 @return The value written back to the PCI configuration register.
958 return PciSegmentWrite32 (Address
, PciSegmentRead32 (Address
) | OrData
);
962 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
965 Reads the 32-bit PCI configuration register specified by Address, performs a
966 bitwise AND between the read result and the value specified by AndData, and
967 writes the result to the 32-bit PCI configuration register specified by
968 Address. The value written to the PCI configuration register is returned.
969 This function must guarantee that all PCI read and write operations are
972 If any reserved bits in Address are set, then ASSERT().
974 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
976 @param AndData The value to AND with the PCI configuration register.
978 @return The value written back to the PCI configuration register.
988 return PciSegmentWrite32 (Address
, PciSegmentRead32 (Address
) & AndData
);
992 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
993 value, followed a bitwise inclusive OR with another 32-bit value.
995 Reads the 32-bit PCI configuration register specified by Address, performs a
996 bitwise AND between the read result and the value specified by AndData,
997 performs a bitwise inclusive OR between the result of the AND operation and
998 the value specified by OrData, and writes the result to the 32-bit PCI
999 configuration register specified by Address. The value written to the PCI
1000 configuration register is returned. This function must guarantee that all PCI
1001 read and write operations are serialized.
1003 If any reserved bits in Address are set, then ASSERT().
1005 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
1007 @param AndData The value to AND with the PCI configuration register.
1008 @param OrData The value to OR with the result of the AND operation.
1010 @return The value written back to the PCI configuration register.
1015 PciSegmentAndThenOr32 (
1021 return PciSegmentWrite32 (Address
, (PciSegmentRead32 (Address
) & AndData
) | OrData
);
1025 Reads a bit field of a PCI configuration register.
1027 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1028 specified by the StartBit and the EndBit. The value of the bit field is
1031 If any reserved bits in Address are set, then ASSERT().
1032 If StartBit is greater than 31, then ASSERT().
1033 If EndBit is greater than 31, then ASSERT().
1034 If EndBit is less than StartBit, then ASSERT().
1036 @param Address PCI configuration register to read.
1037 @param StartBit The ordinal of the least significant bit in the bit field.
1039 @param EndBit The ordinal of the most significant bit in the bit field.
1042 @return The value of the bit field read from the PCI configuration register.
1047 PciSegmentBitFieldRead32 (
1053 return BitFieldRead32 (PciSegmentRead32 (Address
), StartBit
, EndBit
);
1057 Writes a bit field to a PCI configuration register.
1059 Writes Value to the bit field of the PCI configuration register. The bit
1060 field is specified by the StartBit and the EndBit. All other bits in the
1061 destination PCI configuration register are preserved. The new value of the
1062 32-bit register is returned.
1064 If any reserved bits in Address are set, then ASSERT().
1065 If StartBit is greater than 31, then ASSERT().
1066 If EndBit is greater than 31, then ASSERT().
1067 If EndBit is less than StartBit, then ASSERT().
1069 @param Address PCI configuration register to write.
1070 @param StartBit The ordinal of the least significant bit in the bit field.
1072 @param EndBit The ordinal of the most significant bit in the bit field.
1074 @param Value New value of the bit field.
1076 @return The value written back to the PCI configuration register.
1081 PciSegmentBitFieldWrite32 (
1088 return PciSegmentWrite32 (
1090 BitFieldWrite32 (PciSegmentRead32 (Address
), StartBit
, EndBit
, Value
)
1095 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1096 writes the result back to the bit field in the 32-bit port.
1098 Reads the 32-bit PCI configuration register specified by Address, performs a
1099 bitwise inclusive OR between the read result and the value specified by
1100 OrData, and writes the result to the 32-bit PCI configuration register
1101 specified by Address. The value written to the PCI configuration register is
1102 returned. This function must guarantee that all PCI read and write operations
1103 are serialized. Extra left bits in OrData are stripped.
1105 If any reserved bits in Address are set, then ASSERT().
1106 If StartBit is greater than 31, then ASSERT().
1107 If EndBit is greater than 31, then ASSERT().
1108 If EndBit is less than StartBit, then ASSERT().
1110 @param Address PCI configuration register to write.
1111 @param StartBit The ordinal of the least significant bit in the bit field.
1113 @param EndBit The ordinal of the most significant bit in the bit field.
1115 @param OrData The value to OR with the PCI configuration register.
1117 @return The value written back to the PCI configuration register.
1122 PciSegmentBitFieldOr32 (
1129 return PciSegmentWrite32 (
1131 BitFieldOr32 (PciSegmentRead32 (Address
), StartBit
, EndBit
, OrData
)
1136 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1137 AND, and writes the result back to the bit field in the 32-bit register.
1139 Reads the 32-bit PCI configuration register specified by Address, performs a
1140 bitwise AND between the read result and the value specified by AndData, and
1141 writes the result to the 32-bit PCI configuration register specified by
1142 Address. The value written to the PCI configuration register is returned.
1143 This function must guarantee that all PCI read and write operations are
1144 serialized. Extra left bits in AndData are stripped.
1146 If any reserved bits in Address are set, then ASSERT().
1147 If StartBit is greater than 31, then ASSERT().
1148 If EndBit is greater than 31, then ASSERT().
1149 If EndBit is less than StartBit, then ASSERT().
1151 @param Address PCI configuration register to write.
1152 @param StartBit The ordinal of the least significant bit in the bit field.
1154 @param EndBit The ordinal of the most significant bit in the bit field.
1156 @param AndData The value to AND with the PCI configuration register.
1158 @return The value written back to the PCI configuration register.
1163 PciSegmentBitFieldAnd32 (
1170 return PciSegmentWrite32 (
1172 BitFieldAnd32 (PciSegmentRead32 (Address
), StartBit
, EndBit
, AndData
)
1177 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1178 bitwise inclusive OR, and writes the result back to the bit field in the
1181 Reads the 32-bit PCI configuration register specified by Address, performs a
1182 bitwise AND followed by a bitwise inclusive OR between the read result and
1183 the value specified by AndData, and writes the result to the 32-bit PCI
1184 configuration register specified by Address. The value written to the PCI
1185 configuration register is returned. This function must guarantee that all PCI
1186 read and write operations are serialized. Extra left bits in both AndData and
1187 OrData are stripped.
1189 If any reserved bits in Address are set, then ASSERT().
1190 If StartBit is greater than 31, then ASSERT().
1191 If EndBit is greater than 31, then ASSERT().
1192 If EndBit is less than StartBit, then ASSERT().
1194 @param Address PCI configuration register to write.
1195 @param StartBit The ordinal of the least significant bit in the bit field.
1197 @param EndBit The ordinal of the most significant bit in the bit field.
1199 @param AndData The value to AND with the PCI configuration register.
1200 @param OrData The value to OR with the result of the AND operation.
1202 @return The value written back to the PCI configuration register.
1207 PciSegmentBitFieldAndThenOr32 (
1215 return PciSegmentWrite32 (
1217 BitFieldAndThenOr32 (PciSegmentRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1222 Reads a range of PCI configuration registers into a caller supplied buffer.
1224 Reads the range of PCI configuration registers specified by StartAddress and
1225 Size into the buffer specified by Buffer. This function only allows the PCI
1226 configuration registers from a single PCI function to be read. Size is
1227 returned. When possible 32-bit PCI configuration read cycles are used to read
1228 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1229 and 16-bit PCI configuration read cycles may be used at the beginning and the
1232 If StartAddress > 0x0FFFFFFF, then ASSERT().
1233 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1234 If Size > 0 and Buffer is NULL, then ASSERT().
1236 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
1237 Function and Register.
1238 @param Size Size in bytes of the transfer.
1239 @param Buffer Pointer to a buffer receiving the data read.
1246 PciSegmentReadBuffer (
1247 IN UINT64 StartAddress
,
1254 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress
, 0);
1255 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1261 ASSERT (Buffer
!= NULL
);
1264 // Save Size for return
1268 if ((StartAddress
& BIT0
) != 0) {
1270 // Read a byte if StartAddress is byte aligned
1272 *(volatile UINT8
*)Buffer
= PciSegmentRead8 (StartAddress
);
1273 StartAddress
+= sizeof (UINT8
);
1274 Size
-= sizeof (UINT8
);
1275 Buffer
= (UINT8
*)Buffer
+ 1;
1278 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1280 // Read a word if StartAddress is word aligned
1282 *(volatile UINT16
*)Buffer
= PciSegmentRead16 (StartAddress
);
1283 StartAddress
+= sizeof (UINT16
);
1284 Size
-= sizeof (UINT16
);
1285 Buffer
= (UINT16
*)Buffer
+ 1;
1288 while (Size
>= sizeof (UINT32
)) {
1290 // Read as many double words as possible
1292 *(volatile UINT32
*)Buffer
= PciSegmentRead32 (StartAddress
);
1293 StartAddress
+= sizeof (UINT32
);
1294 Size
-= sizeof (UINT32
);
1295 Buffer
= (UINT32
*)Buffer
+ 1;
1298 if (Size
>= sizeof (UINT16
)) {
1300 // Read the last remaining word if exist
1302 *(volatile UINT16
*)Buffer
= PciSegmentRead16 (StartAddress
);
1303 StartAddress
+= sizeof (UINT16
);
1304 Size
-= sizeof (UINT16
);
1305 Buffer
= (UINT16
*)Buffer
+ 1;
1308 if (Size
>= sizeof (UINT8
)) {
1310 // Read the last remaining byte if exist
1312 *(volatile UINT8
*)Buffer
= PciSegmentRead8 (StartAddress
);
1319 Copies the data in a caller supplied buffer to a specified range of PCI
1320 configuration space.
1322 Writes the range of PCI configuration registers specified by StartAddress and
1323 Size from the buffer specified by Buffer. This function only allows the PCI
1324 configuration registers from a single PCI function to be written. Size is
1325 returned. When possible 32-bit PCI configuration write cycles are used to
1326 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1327 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1328 and the end of the range.
1330 If StartAddress > 0x0FFFFFFF, then ASSERT().
1331 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1332 If Size > 0 and Buffer is NULL, then ASSERT().
1334 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
1335 Function and Register.
1336 @param Size Size in bytes of the transfer.
1337 @param Buffer Pointer to a buffer containing the data to write.
1344 PciSegmentWriteBuffer (
1345 IN UINT64 StartAddress
,
1352 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress
, 0);
1353 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1359 ASSERT (Buffer
!= NULL
);
1362 // Save Size for return
1366 if ((StartAddress
& BIT0
) != 0) {
1368 // Write a byte if StartAddress is byte aligned
1370 PciSegmentWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1371 StartAddress
+= sizeof (UINT8
);
1372 Size
-= sizeof (UINT8
);
1373 Buffer
= (UINT8
*)Buffer
+ 1;
1376 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1378 // Write a word if StartAddress is word aligned
1380 PciSegmentWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1381 StartAddress
+= sizeof (UINT16
);
1382 Size
-= sizeof (UINT16
);
1383 Buffer
= (UINT16
*)Buffer
+ 1;
1386 while (Size
>= sizeof (UINT32
)) {
1388 // Write as many double words as possible
1390 PciSegmentWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1391 StartAddress
+= sizeof (UINT32
);
1392 Size
-= sizeof (UINT32
);
1393 Buffer
= (UINT32
*)Buffer
+ 1;
1396 if (Size
>= sizeof (UINT16
)) {
1398 // Write the last remaining word if exist
1400 PciSegmentWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1401 StartAddress
+= sizeof (UINT16
);
1402 Size
-= sizeof (UINT16
);
1403 Buffer
= (UINT16
*)Buffer
+ 1;
1406 if (Size
>= sizeof (UINT8
)) {
1408 // Write the last remaining byte if exist
1410 PciSegmentWrite8 (StartAddress
, *(UINT8
*)Buffer
);