2 PCI Library using PCI Root Bridge I/O Protocol.
4 Copyright (c) 2007 - 2008, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Protocol/PciRootBridgeIo.h>
20 #include <Library/PciLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/UefiBootServicesTableLib.h>
23 #include <Library/DebugLib.h>
26 Assert the validity of a PCI address. A valid PCI address should contain 1's
27 only in the low 28 bits.
29 @param A The address to validate.
30 @param M Additional bits to assert to be zero.
33 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
34 ASSERT (((A) & (~0xfffffff | (M))) == 0)
37 Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.
39 @param A Address that encodes the PCI Bus, Device, Function and
43 #define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \
44 ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
47 // Global varible to cache pointer to PCI Root Bridge I/O protocol.
49 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*mPciRootBridgeIo
= NULL
;
52 The constructor function caches the pointer to PCI Root Bridge I/O protocol.
54 The constructor function locates PCI Root Bridge I/O protocol from protocol database.
55 It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.
57 @param ImageHandle The firmware allocated handle for the EFI image.
58 @param SystemTable A pointer to the EFI System Table.
60 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
66 IN EFI_HANDLE ImageHandle
,
67 IN EFI_SYSTEM_TABLE
*SystemTable
72 Status
= gBS
->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid
, NULL
, (VOID
**) &mPciRootBridgeIo
);
73 ASSERT_EFI_ERROR (Status
);
74 ASSERT (mPciRootBridgeIo
!= NULL
);
80 Internal worker function to read a PCI configuration register.
82 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service.
83 It reads and returns the PCI configuration register specified by Address,
84 the width of data is specified by Width.
86 @param Address Address that encodes the PCI Bus, Device, Function and
88 @param Width Width of data to read
90 @return The value read from the PCI configuration register.
94 DxePciLibPciRootBridgeIoReadWorker (
96 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
101 mPciRootBridgeIo
->Pci
.Read (
104 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
113 Internal worker function to writes a PCI configuration register.
115 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.
116 It writes the PCI configuration register specified by Address with the
117 value specified by Data. The width of data is specifed by Width.
120 @param Address Address that encodes the PCI Bus, Device, Function and
122 @param Width Width of data to write
123 @param Data The value to write.
125 @return The value written to the PCI configuration register.
129 DxePciLibPciRootBridgeIoWriteWorker (
131 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
135 mPciRootBridgeIo
->Pci
.Write (
138 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
146 Reads an 8-bit PCI configuration register.
148 Reads and returns the 8-bit PCI configuration register specified by Address.
149 This function must guarantee that all PCI read and write operations are
152 If Address > 0x0FFFFFFF, then ASSERT().
154 @param Address Address that encodes the PCI Bus, Device, Function and
157 @return The value read from the PCI configuration register.
166 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
168 return (UINT8
) DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint8
);
172 Writes an 8-bit PCI configuration register.
174 Writes the 8-bit PCI configuration register specified by Address with the
175 value specified by Value. Value is returned. This function must guarantee
176 that all PCI read and write operations are serialized.
178 If Address > 0x0FFFFFFF, then ASSERT().
180 @param Address Address that encodes the PCI Bus, Device, Function and
182 @param Data The value to write.
184 @return The value written to the PCI configuration register.
194 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
196 return (UINT8
) DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint8
, Data
);
200 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
203 Reads the 8-bit PCI configuration register specified by Address, performs a
204 bitwise inclusive OR between the read result and the value specified by
205 OrData, and writes the result to the 8-bit PCI configuration register
206 specified by Address. The value written to the PCI configuration register is
207 returned. This function must guarantee that all PCI read and write operations
210 If Address > 0x0FFFFFFF, then ASSERT().
212 @param Address Address that encodes the PCI Bus, Device, Function and
214 @param OrData The value to OR with the PCI configuration register.
216 @return The value written back to the PCI configuration register.
226 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) | OrData
));
230 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
233 Reads the 8-bit PCI configuration register specified by Address, performs a
234 bitwise AND between the read result and the value specified by AndData, and
235 writes the result to the 8-bit PCI configuration register specified by
236 Address. The value written to the PCI configuration register is returned.
237 This function must guarantee that all PCI read and write operations are
240 If Address > 0x0FFFFFFF, then ASSERT().
242 @param Address Address that encodes the PCI Bus, Device, Function and
244 @param AndData The value to AND with the PCI configuration register.
246 @return The value written back to the PCI configuration register.
256 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) & AndData
));
260 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
261 value, followed a bitwise inclusive OR with another 8-bit value.
263 Reads the 8-bit PCI configuration register specified by Address, performs a
264 bitwise AND between the read result and the value specified by AndData,
265 performs a bitwise inclusive OR between the result of the AND operation and
266 the value specified by OrData, and writes the result to the 8-bit PCI
267 configuration register specified by Address. The value written to the PCI
268 configuration register is returned. This function must guarantee that all PCI
269 read and write operations are serialized.
271 If Address > 0x0FFFFFFF, then ASSERT().
273 @param Address Address that encodes the PCI Bus, Device, Function and
275 @param AndData The value to AND with the PCI configuration register.
276 @param OrData The value to OR with the result of the AND operation.
278 @return The value written back to the PCI configuration register.
289 return PciWrite8 (Address
, (UINT8
) ((PciRead8 (Address
) & AndData
) | OrData
));
293 Reads a bit field of a PCI configuration register.
295 Reads the bit field in an 8-bit PCI configuration register. The bit field is
296 specified by the StartBit and the EndBit. The value of the bit field is
299 If Address > 0x0FFFFFFF, then ASSERT().
300 If StartBit is greater than 7, then ASSERT().
301 If EndBit is greater than 7, then ASSERT().
302 If EndBit is less than StartBit, then ASSERT().
304 @param Address PCI configuration register to read.
305 @param StartBit The ordinal of the least significant bit in the bit field.
307 @param EndBit The ordinal of the most significant bit in the bit field.
310 @return The value of the bit field read from the PCI configuration register.
321 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
325 Writes a bit field to a PCI configuration register.
327 Writes Value to the bit field of the PCI configuration register. The bit
328 field is specified by the StartBit and the EndBit. All other bits in the
329 destination PCI configuration register are preserved. The new value of the
330 8-bit register is returned.
332 If Address > 0x0FFFFFFF, then ASSERT().
333 If StartBit is greater than 7, then ASSERT().
334 If EndBit is greater than 7, then ASSERT().
335 If EndBit is less than StartBit, then ASSERT().
337 @param Address PCI configuration register to write.
338 @param StartBit The ordinal of the least significant bit in the bit field.
340 @param EndBit The ordinal of the most significant bit in the bit field.
342 @param Value New value of the bit field.
344 @return The value written back to the PCI configuration register.
358 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
363 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
364 writes the result back to the bit field in the 8-bit port.
366 Reads the 8-bit PCI configuration register specified by Address, performs a
367 bitwise inclusive OR between the read result and the value specified by
368 OrData, and writes the result to the 8-bit PCI configuration register
369 specified by Address. The value written to the PCI configuration register is
370 returned. This function must guarantee that all PCI read and write operations
371 are serialized. Extra left bits in OrData are stripped.
373 If Address > 0x0FFFFFFF, then ASSERT().
374 If StartBit is greater than 7, then ASSERT().
375 If EndBit is greater than 7, then ASSERT().
376 If EndBit is less than StartBit, then ASSERT().
378 @param Address PCI configuration register to write.
379 @param StartBit The ordinal of the least significant bit in the bit field.
381 @param EndBit The ordinal of the most significant bit in the bit field.
383 @param OrData The value to OR with the PCI configuration register.
385 @return The value written back to the PCI configuration register.
399 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
404 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
405 AND, and writes the result back to the bit field in the 8-bit register.
407 Reads the 8-bit PCI configuration register specified by Address, performs a
408 bitwise AND between the read result and the value specified by AndData, and
409 writes the result to the 8-bit PCI configuration register specified by
410 Address. The value written to the PCI configuration register is returned.
411 This function must guarantee that all PCI read and write operations are
412 serialized. Extra left bits in AndData are stripped.
414 If Address > 0x0FFFFFFF, then ASSERT().
415 If StartBit is greater than 7, then ASSERT().
416 If EndBit is greater than 7, then ASSERT().
417 If EndBit is less than StartBit, then ASSERT().
419 @param Address PCI configuration register to write.
420 @param StartBit The ordinal of the least significant bit in the bit field.
422 @param EndBit The ordinal of the most significant bit in the bit field.
424 @param AndData The value to AND with the PCI configuration register.
426 @return The value written back to the PCI configuration register.
440 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
445 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
446 bitwise inclusive OR, and writes the result back to the bit field in the
449 Reads the 8-bit PCI configuration register specified by Address, performs a
450 bitwise AND followed by a bitwise inclusive OR between the read result and
451 the value specified by AndData, and writes the result to the 8-bit PCI
452 configuration register specified by Address. The value written to the PCI
453 configuration register is returned. This function must guarantee that all PCI
454 read and write operations are serialized. Extra left bits in both AndData and
457 If Address > 0x0FFFFFFF, then ASSERT().
458 If StartBit is greater than 7, then ASSERT().
459 If EndBit is greater than 7, then ASSERT().
460 If EndBit is less than StartBit, then ASSERT().
462 @param Address PCI configuration register to write.
463 @param StartBit The ordinal of the least significant bit in the bit field.
465 @param EndBit The ordinal of the most significant bit in the bit field.
467 @param AndData The value to AND with the PCI configuration register.
468 @param OrData The value to OR with the result of the AND operation.
470 @return The value written back to the PCI configuration register.
475 PciBitFieldAndThenOr8 (
485 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
490 Reads a 16-bit PCI configuration register.
492 Reads and returns the 16-bit PCI configuration register specified by Address.
493 This function must guarantee that all PCI read and write operations are
496 If Address > 0x0FFFFFFF, then ASSERT().
497 If Address is not aligned on a 16-bit boundary, then ASSERT().
499 @param Address Address that encodes the PCI Bus, Device, Function and
502 @return The value read from the PCI configuration register.
511 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
513 return (UINT16
) DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint16
);
517 Writes a 16-bit PCI configuration register.
519 Writes the 16-bit PCI configuration register specified by Address with the
520 value specified by Value. Value is returned. This function must guarantee
521 that all PCI read and write operations are serialized.
523 If Address > 0x0FFFFFFF, then ASSERT().
524 If Address is not aligned on a 16-bit boundary, then ASSERT().
526 @param Address Address that encodes the PCI Bus, Device, Function and
528 @param Data The value to write.
530 @return The value written to the PCI configuration register.
540 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
542 return (UINT16
) DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint16
, Data
);
546 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
549 Reads the 16-bit PCI configuration register specified by Address, performs a
550 bitwise inclusive OR between the read result and the value specified by
551 OrData, and writes the result to the 16-bit PCI configuration register
552 specified by Address. The value written to the PCI configuration register is
553 returned. This function must guarantee that all PCI read and write operations
556 If Address > 0x0FFFFFFF, then ASSERT().
557 If Address is not aligned on a 16-bit boundary, then ASSERT().
559 @param Address Address that encodes the PCI Bus, Device, Function and
561 @param OrData The value to OR with the PCI configuration register.
563 @return The value written back to the PCI configuration register.
573 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) | OrData
));
577 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
580 Reads the 16-bit PCI configuration register specified by Address, performs a
581 bitwise AND between the read result and the value specified by AndData, and
582 writes the result to the 16-bit PCI configuration register specified by
583 Address. The value written to the PCI configuration register is returned.
584 This function must guarantee that all PCI read and write operations are
587 If Address > 0x0FFFFFFF, then ASSERT().
588 If Address is not aligned on a 16-bit boundary, then ASSERT().
590 @param Address Address that encodes the PCI Bus, Device, Function and
592 @param AndData The value to AND with the PCI configuration register.
594 @return The value written back to the PCI configuration register.
604 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) & AndData
));
608 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
609 value, followed a bitwise inclusive OR with another 16-bit value.
611 Reads the 16-bit PCI configuration register specified by Address, performs a
612 bitwise AND between the read result and the value specified by AndData,
613 performs a bitwise inclusive OR between the result of the AND operation and
614 the value specified by OrData, and writes the result to the 16-bit PCI
615 configuration register specified by Address. The value written to the PCI
616 configuration register is returned. This function must guarantee that all PCI
617 read and write operations are serialized.
619 If Address > 0x0FFFFFFF, then ASSERT().
620 If Address is not aligned on a 16-bit boundary, then ASSERT().
622 @param Address Address that encodes the PCI Bus, Device, Function and
624 @param AndData The value to AND with the PCI configuration register.
625 @param OrData The value to OR with the result of the AND operation.
627 @return The value written back to the PCI configuration register.
638 return PciWrite16 (Address
, (UINT16
) ((PciRead16 (Address
) & AndData
) | OrData
));
642 Reads a bit field of a PCI configuration register.
644 Reads the bit field in a 16-bit PCI configuration register. The bit field is
645 specified by the StartBit and the EndBit. The value of the bit field is
648 If Address > 0x0FFFFFFF, then ASSERT().
649 If Address is not aligned on a 16-bit boundary, then ASSERT().
650 If StartBit is greater than 15, then ASSERT().
651 If EndBit is greater than 15, then ASSERT().
652 If EndBit is less than StartBit, then ASSERT().
654 @param Address PCI configuration register to read.
655 @param StartBit The ordinal of the least significant bit in the bit field.
657 @param EndBit The ordinal of the most significant bit in the bit field.
660 @return The value of the bit field read from the PCI configuration register.
671 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
675 Writes a bit field to a PCI configuration register.
677 Writes Value to the bit field of the PCI configuration register. The bit
678 field is specified by the StartBit and the EndBit. All other bits in the
679 destination PCI configuration register are preserved. The new value of the
680 16-bit register is returned.
682 If Address > 0x0FFFFFFF, then ASSERT().
683 If Address is not aligned on a 16-bit boundary, then ASSERT().
684 If StartBit is greater than 15, then ASSERT().
685 If EndBit is greater than 15, then ASSERT().
686 If EndBit is less than StartBit, then ASSERT().
688 @param Address PCI configuration register to write.
689 @param StartBit The ordinal of the least significant bit in the bit field.
691 @param EndBit The ordinal of the most significant bit in the bit field.
693 @param Value New value of the bit field.
695 @return The value written back to the PCI configuration register.
709 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
714 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
715 writes the result back to the bit field in the 16-bit port.
717 Reads the 16-bit PCI configuration register specified by Address, performs a
718 bitwise inclusive OR between the read result and the value specified by
719 OrData, and writes the result to the 16-bit PCI configuration register
720 specified by Address. The value written to the PCI configuration register is
721 returned. This function must guarantee that all PCI read and write operations
722 are serialized. Extra left bits in OrData are stripped.
724 If Address > 0x0FFFFFFF, then ASSERT().
725 If Address is not aligned on a 16-bit boundary, then ASSERT().
726 If StartBit is greater than 15, then ASSERT().
727 If EndBit is greater than 15, then ASSERT().
728 If EndBit is less than StartBit, then ASSERT().
730 @param Address PCI configuration register to write.
731 @param StartBit The ordinal of the least significant bit in the bit field.
733 @param EndBit The ordinal of the most significant bit in the bit field.
735 @param OrData The value to OR with the PCI configuration register.
737 @return The value written back to the PCI configuration register.
751 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
756 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
757 AND, and writes the result back to the bit field in the 16-bit register.
759 Reads the 16-bit PCI configuration register specified by Address, performs a
760 bitwise AND between the read result and the value specified by AndData, and
761 writes the result to the 16-bit PCI configuration register specified by
762 Address. The value written to the PCI configuration register is returned.
763 This function must guarantee that all PCI read and write operations are
764 serialized. Extra left bits in AndData are stripped.
766 If Address > 0x0FFFFFFF, then ASSERT().
767 If Address is not aligned on a 16-bit boundary, then ASSERT().
768 If StartBit is greater than 15, then ASSERT().
769 If EndBit is greater than 15, then ASSERT().
770 If EndBit is less than StartBit, then ASSERT().
772 @param Address PCI configuration register to write.
773 @param StartBit The ordinal of the least significant bit in the bit field.
775 @param EndBit The ordinal of the most significant bit in the bit field.
777 @param AndData The value to AND with the PCI configuration register.
779 @return The value written back to the PCI configuration register.
793 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
798 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
799 bitwise inclusive OR, and writes the result back to the bit field in the
802 Reads the 16-bit PCI configuration register specified by Address, performs a
803 bitwise AND followed by a bitwise inclusive OR between the read result and
804 the value specified by AndData, and writes the result to the 16-bit PCI
805 configuration register specified by Address. The value written to the PCI
806 configuration register is returned. This function must guarantee that all PCI
807 read and write operations are serialized. Extra left bits in both AndData and
810 If Address > 0x0FFFFFFF, then ASSERT().
811 If Address is not aligned on a 16-bit boundary, then ASSERT().
812 If StartBit is greater than 15, then ASSERT().
813 If EndBit is greater than 15, then ASSERT().
814 If EndBit is less than StartBit, then ASSERT().
816 @param Address PCI configuration register to write.
817 @param StartBit The ordinal of the least significant bit in the bit field.
819 @param EndBit The ordinal of the most significant bit in the bit field.
821 @param AndData The value to AND with the PCI configuration register.
822 @param OrData The value to OR with the result of the AND operation.
824 @return The value written back to the PCI configuration register.
829 PciBitFieldAndThenOr16 (
839 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
844 Reads a 32-bit PCI configuration register.
846 Reads and returns the 32-bit PCI configuration register specified by Address.
847 This function must guarantee that all PCI read and write operations are
850 If Address > 0x0FFFFFFF, then ASSERT().
851 If Address is not aligned on a 32-bit boundary, then ASSERT().
853 @param Address Address that encodes the PCI Bus, Device, Function and
856 @return The value read from the PCI configuration register.
865 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
867 return DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint32
);
871 Writes a 32-bit PCI configuration register.
873 Writes the 32-bit PCI configuration register specified by Address with the
874 value specified by Value. Value is returned. This function must guarantee
875 that all PCI read and write operations are serialized.
877 If Address > 0x0FFFFFFF, then ASSERT().
878 If Address is not aligned on a 32-bit boundary, then ASSERT().
880 @param Address Address that encodes the PCI Bus, Device, Function and
882 @param Data The value to write.
884 @return The value written to the PCI configuration register.
894 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
896 return DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint32
, Data
);
900 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
903 Reads the 32-bit PCI configuration register specified by Address, performs a
904 bitwise inclusive OR between the read result and the value specified by
905 OrData, and writes the result to the 32-bit PCI configuration register
906 specified by Address. The value written to the PCI configuration register is
907 returned. This function must guarantee that all PCI read and write operations
910 If Address > 0x0FFFFFFF, then ASSERT().
911 If Address is not aligned on a 32-bit boundary, then ASSERT().
913 @param Address Address that encodes the PCI Bus, Device, Function and
915 @param OrData The value to OR with the PCI configuration register.
917 @return The value written back to the PCI configuration register.
927 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
931 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
934 Reads the 32-bit PCI configuration register specified by Address, performs a
935 bitwise AND between the read result and the value specified by AndData, and
936 writes the result to the 32-bit PCI configuration register specified by
937 Address. The value written to the PCI configuration register is returned.
938 This function must guarantee that all PCI read and write operations are
941 If Address > 0x0FFFFFFF, then ASSERT().
942 If Address is not aligned on a 32-bit boundary, then ASSERT().
944 @param Address Address that encodes the PCI Bus, Device, Function and
946 @param AndData The value to AND with the PCI configuration register.
948 @return The value written back to the PCI configuration register.
958 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
962 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
963 value, followed a bitwise inclusive OR with another 32-bit value.
965 Reads the 32-bit PCI configuration register specified by Address, performs a
966 bitwise AND between the read result and the value specified by AndData,
967 performs a bitwise inclusive OR between the result of the AND operation and
968 the value specified by OrData, and writes the result to the 32-bit PCI
969 configuration register specified by Address. The value written to the PCI
970 configuration register is returned. This function must guarantee that all PCI
971 read and write operations are serialized.
973 If Address > 0x0FFFFFFF, then ASSERT().
974 If Address is not aligned on a 32-bit boundary, then ASSERT().
976 @param Address Address that encodes the PCI Bus, Device, Function and
978 @param AndData The value to AND with the PCI configuration register.
979 @param OrData The value to OR with the result of the AND operation.
981 @return The value written back to the PCI configuration register.
992 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
996 Reads a bit field of a PCI configuration register.
998 Reads the bit field in a 32-bit PCI configuration register. The bit field is
999 specified by the StartBit and the EndBit. The value of the bit field is
1002 If Address > 0x0FFFFFFF, then ASSERT().
1003 If Address is not aligned on a 32-bit boundary, then ASSERT().
1004 If StartBit is greater than 31, then ASSERT().
1005 If EndBit is greater than 31, then ASSERT().
1006 If EndBit is less than StartBit, then ASSERT().
1008 @param Address PCI configuration register to read.
1009 @param StartBit The ordinal of the least significant bit in the bit field.
1011 @param EndBit The ordinal of the most significant bit in the bit field.
1014 @return The value of the bit field read from the PCI configuration register.
1025 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1029 Writes a bit field to a PCI configuration register.
1031 Writes Value to the bit field of the PCI configuration register. The bit
1032 field is specified by the StartBit and the EndBit. All other bits in the
1033 destination PCI configuration register are preserved. The new value of the
1034 32-bit register is returned.
1036 If Address > 0x0FFFFFFF, then ASSERT().
1037 If Address is not aligned on a 32-bit boundary, then ASSERT().
1038 If StartBit is greater than 31, then ASSERT().
1039 If EndBit is greater than 31, then ASSERT().
1040 If EndBit is less than StartBit, then ASSERT().
1042 @param Address PCI configuration register to write.
1043 @param StartBit The ordinal of the least significant bit in the bit field.
1045 @param EndBit The ordinal of the most significant bit in the bit field.
1047 @param Value New value of the bit field.
1049 @return The value written back to the PCI configuration register.
1054 PciBitFieldWrite32 (
1063 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1068 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1069 writes the result back to the bit field in the 32-bit port.
1071 Reads the 32-bit PCI configuration register specified by Address, performs a
1072 bitwise inclusive OR between the read result and the value specified by
1073 OrData, and writes the result to the 32-bit PCI configuration register
1074 specified by Address. The value written to the PCI configuration register is
1075 returned. This function must guarantee that all PCI read and write operations
1076 are serialized. Extra left bits in OrData are stripped.
1078 If Address > 0x0FFFFFFF, then ASSERT().
1079 If Address is not aligned on a 32-bit boundary, then ASSERT().
1080 If StartBit is greater than 31, then ASSERT().
1081 If EndBit is greater than 31, then ASSERT().
1082 If EndBit is less than StartBit, then ASSERT().
1084 @param Address PCI configuration register to write.
1085 @param StartBit The ordinal of the least significant bit in the bit field.
1087 @param EndBit The ordinal of the most significant bit in the bit field.
1089 @param OrData The value to OR with the PCI configuration register.
1091 @return The value written back to the PCI configuration register.
1105 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1110 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1111 AND, and writes the result back to the bit field in the 32-bit register.
1113 Reads the 32-bit PCI configuration register specified by Address, performs a
1114 bitwise AND between the read result and the value specified by AndData, and
1115 writes the result to the 32-bit PCI configuration register specified by
1116 Address. The value written to the PCI configuration register is returned.
1117 This function must guarantee that all PCI read and write operations are
1118 serialized. Extra left bits in AndData are stripped.
1120 If Address > 0x0FFFFFFF, then ASSERT().
1121 If Address is not aligned on a 32-bit boundary, then ASSERT().
1122 If StartBit is greater than 31, then ASSERT().
1123 If EndBit is greater than 31, then ASSERT().
1124 If EndBit is less than StartBit, then ASSERT().
1126 @param Address PCI configuration register to write.
1127 @param StartBit The ordinal of the least significant bit in the bit field.
1129 @param EndBit The ordinal of the most significant bit in the bit field.
1131 @param AndData The value to AND with the PCI configuration register.
1133 @return The value written back to the PCI configuration register.
1147 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1152 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1153 bitwise inclusive OR, and writes the result back to the bit field in the
1156 Reads the 32-bit PCI configuration register specified by Address, performs a
1157 bitwise AND followed by a bitwise inclusive OR between the read result and
1158 the value specified by AndData, and writes the result to the 32-bit PCI
1159 configuration register specified by Address. The value written to the PCI
1160 configuration register is returned. This function must guarantee that all PCI
1161 read and write operations are serialized. Extra left bits in both AndData and
1162 OrData are stripped.
1164 If Address > 0x0FFFFFFF, then ASSERT().
1165 If Address is not aligned on a 32-bit boundary, then ASSERT().
1166 If StartBit is greater than 31, then ASSERT().
1167 If EndBit is greater than 31, then ASSERT().
1168 If EndBit is less than StartBit, then ASSERT().
1170 @param Address PCI configuration register to write.
1171 @param StartBit The ordinal of the least significant bit in the bit field.
1173 @param EndBit The ordinal of the most significant bit in the bit field.
1175 @param AndData The value to AND with the PCI configuration register.
1176 @param OrData The value to OR with the result of the AND operation.
1178 @return The value written back to the PCI configuration register.
1183 PciBitFieldAndThenOr32 (
1193 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1198 Reads a range of PCI configuration registers into a caller supplied buffer.
1200 Reads the range of PCI configuration registers specified by StartAddress and
1201 Size into the buffer specified by Buffer. This function only allows the PCI
1202 configuration registers from a single PCI function to be read. Size is
1203 returned. When possible 32-bit PCI configuration read cycles are used to read
1204 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1205 and 16-bit PCI configuration read cycles may be used at the beginning and the
1208 If StartAddress > 0x0FFFFFFF, then ASSERT().
1209 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1210 If Size > 0 and Buffer is NULL, then ASSERT().
1212 @param StartAddress Starting address that encodes the PCI Bus, Device,
1213 Function and Register.
1214 @param Size Size in bytes of the transfer.
1215 @param Buffer Pointer to a buffer receiving the data read.
1223 IN UINTN StartAddress
,
1230 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1231 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1237 ASSERT (Buffer
!= NULL
);
1240 // Save Size for return
1244 if ((StartAddress
& BIT0
) != 0) {
1246 // Read a byte if StartAddress is byte aligned
1248 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1249 StartAddress
+= sizeof (UINT8
);
1250 Size
-= sizeof (UINT8
);
1251 Buffer
= (UINT8
*)Buffer
+ 1;
1254 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1256 // Read a word if StartAddress is word aligned
1258 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1259 StartAddress
+= sizeof (UINT16
);
1260 Size
-= sizeof (UINT16
);
1261 Buffer
= (UINT16
*)Buffer
+ 1;
1264 while (Size
>= sizeof (UINT32
)) {
1266 // Read as many double words as possible
1268 *(volatile UINT32
*)Buffer
= PciRead32 (StartAddress
);
1269 StartAddress
+= sizeof (UINT32
);
1270 Size
-= sizeof (UINT32
);
1271 Buffer
= (UINT32
*)Buffer
+ 1;
1274 if (Size
>= sizeof (UINT16
)) {
1276 // Read the last remaining word if exist
1278 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1279 StartAddress
+= sizeof (UINT16
);
1280 Size
-= sizeof (UINT16
);
1281 Buffer
= (UINT16
*)Buffer
+ 1;
1284 if (Size
>= sizeof (UINT8
)) {
1286 // Read the last remaining byte if exist
1288 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1295 Copies the data in a caller supplied buffer to a specified range of PCI
1296 configuration space.
1298 Writes the range of PCI configuration registers specified by StartAddress and
1299 Size from the buffer specified by Buffer. This function only allows the PCI
1300 configuration registers from a single PCI function to be written. Size is
1301 returned. When possible 32-bit PCI configuration write cycles are used to
1302 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1303 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1304 and the end of the range.
1306 If StartAddress > 0x0FFFFFFF, then ASSERT().
1307 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1308 If Size > 0 and Buffer is NULL, then ASSERT().
1310 @param StartAddress Starting address that encodes the PCI Bus, Device,
1311 Function and Register.
1312 @param Size Size in bytes of the transfer.
1313 @param Buffer Pointer to a buffer containing the data to write.
1321 IN UINTN StartAddress
,
1328 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1329 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1335 ASSERT (Buffer
!= NULL
);
1338 // Save Size for return
1342 if ((StartAddress
& BIT0
) != 0) {
1344 // Write a byte if StartAddress is byte aligned
1346 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1347 StartAddress
+= sizeof (UINT8
);
1348 Size
-= sizeof (UINT8
);
1349 Buffer
= (UINT8
*)Buffer
+ 1;
1352 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1354 // Write a word if StartAddress is word aligned
1356 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1357 StartAddress
+= sizeof (UINT16
);
1358 Size
-= sizeof (UINT16
);
1359 Buffer
= (UINT16
*)Buffer
+ 1;
1362 while (Size
>= sizeof (UINT32
)) {
1364 // Write as many double words as possible
1366 PciWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1367 StartAddress
+= sizeof (UINT32
);
1368 Size
-= sizeof (UINT32
);
1369 Buffer
= (UINT32
*)Buffer
+ 1;
1372 if (Size
>= sizeof (UINT16
)) {
1374 // Write the last remaining word if exist
1376 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1377 StartAddress
+= sizeof (UINT16
);
1378 Size
-= sizeof (UINT16
);
1379 Buffer
= (UINT16
*)Buffer
+ 1;
1382 if (Size
>= sizeof (UINT8
)) {
1384 // Write the last remaining byte if exist
1386 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);