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[mirror_edk2.git] / OldMdePkg / Include / Ipf / IpfDefines.h
1 ///** @file
2 // IPF Processor Defines for assembly code
3 //
4 // @note
5 // This file is included by assembly files as well. The assmber can NOT deal
6 // with /* */ commnets this is why this file is commented not following the
7 // coding standard
8 //
9 //Copyright (c) 2006, Intel Corporation
10 //All rights reserved. This program and the accompanying materials
11 //are licensed and made available under the terms and conditions of the BSD License
12 //which accompanies this distribution. The full text of the license may be found at
13 //http://opensource.org/licenses/bsd-license.php
14 //
15 //THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 //WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 //
18 //Module Name: IpfDefines.h
19 //
20 //**/
21
22 #ifndef _IPFDEFINES_H
23 #define _IPFDEFINES_H
24
25 //
26 // IPI DElivery Methods
27 //
28 #define IPI_INT_DELIVERY 0x0
29 #define IPI_PMI_DELIVERY 0x2
30 #define IPI_NMI_DELIVERY 0x4
31 #define IPI_INIT_DELIVERY 0x5
32 #define IPI_ExtINT_DELIVERY 0x7
33
34 //
35 // Define Itanium-based system registers.
36 //
37 // Define Itanium-based system register bit field offsets.
38 //
39 // Processor Status Register (PSR) Bit positions
40 //
41 // User / System mask
42 //
43 #define PSR_RV0 0
44 #define PSR_BE 1
45 #define PSR_UP 2
46 #define PSR_AC 3
47 #define PSR_MFL 4
48 #define PSR_MFH 5
49
50 //
51 // PSR bits 6-12 reserved (must be zero)
52 //
53 #define PSR_MBZ0 6
54 #define PSR_MBZ0_V 0x1ffUL L
55
56 //
57 // System only mask
58 //
59 #define PSR_IC 13
60 #define PSR_IC_MASK (1 << 13)
61 #define PSR_I 14
62 #define PSR_PK 15
63 #define PSR_MBZ1 16
64 #define PSR_MBZ1_V 0x1UL L
65 #define PSR_DT 17
66 #define PSR_DFL 18
67 #define PSR_DFH 19
68 #define PSR_SP 20
69 #define PSR_PP 21
70 #define PSR_DI 22
71 #define PSR_SI 23
72 #define PSR_DB 24
73 #define PSR_LP 25
74 #define PSR_TB 26
75 #define PSR_RT 27
76
77 //
78 // PSR bits 28-31 reserved (must be zero)
79 //
80 #define PSR_MBZ2 28
81 #define PSR_MBZ2_V 0xfUL L
82
83 //
84 // Neither mask
85 //
86 #define PSR_CPL 32
87 #define PSR_CPL_LEN 2
88 #define PSR_IS 34
89 #define PSR_MC 35
90 #define PSR_IT 36
91 #define PSR_IT_MASK 0x1000000000
92 #define PSR_ID 37
93 #define PSR_DA 38
94 #define PSR_DD 39
95 #define PSR_SS 40
96 #define PSR_RI 41
97 #define PSR_RI_LEN 2
98 #define PSR_ED 43
99 #define PSR_BN 44
100
101 //
102 // PSR bits 45-63 reserved (must be zero)
103 //
104 #define PSR_MBZ3 45
105 #define PSR_MBZ3_V 0xfffffUL L
106
107 //
108 // Floating Point Status Register (FPSR) Bit positions
109 //
110 //
111 // Traps
112 //
113 #define FPSR_VD 0
114 #define FPSR_DD 1
115 #define FPSR_ZD 2
116 #define FPSR_OD 3
117 #define FPSR_UD 4
118 #define FPSR_ID 5
119
120 //
121 // Status Field 0 - Controls
122 //
123 #define FPSR0_FTZ0 6
124 #define FPSR0_WRE0 7
125 #define FPSR0_PC0 8
126 #define FPSR0_RC0 10
127 #define FPSR0_TD0 12
128
129 //
130 // Status Field 0 - Flags
131 //
132 #define FPSR0_V0 13
133 #define FPSR0_D0 14
134 #define FPSR0_Z0 15
135 #define FPSR0_O0 16
136 #define FPSR0_U0 17
137 #define FPSR0_I0 18
138
139 //
140 // Status Field 1 - Controls
141 //
142 #define FPSR1_FTZ0 19
143 #define FPSR1_WRE0 20
144 #define FPSR1_PC0 21
145 #define FPSR1_RC0 23
146 #define FPSR1_TD0 25
147
148 //
149 // Status Field 1 - Flags
150 //
151 #define FPSR1_V0 26
152 #define FPSR1_D0 27
153 #define FPSR1_Z0 28
154 #define FPSR1_O0 29
155 #define FPSR1_U0 30
156 #define FPSR1_I0 31
157
158 //
159 // Status Field 2 - Controls
160 //
161 #define FPSR2_FTZ0 32
162 #define FPSR2_WRE0 33
163 #define FPSR2_PC0 34
164 #define FPSR2_RC0 36
165 #define FPSR2_TD0 38
166
167 //
168 // Status Field 2 - Flags
169 //
170 #define FPSR2_V0 39
171 #define FPSR2_D0 40
172 #define FPSR2_Z0 41
173 #define FPSR2_O0 42
174 #define FPSR2_U0 43
175 #define FPSR2_I0 44
176
177 //
178 // Status Field 3 - Controls
179 //
180 #define FPSR3_FTZ0 45
181 #define FPSR3_WRE0 46
182 #define FPSR3_PC0 47
183 #define FPSR3_RC0 49
184 #define FPSR3_TD0 51
185
186 //
187 // Status Field 0 - Flags
188 //
189 #define FPSR3_V0 52
190 #define FPSR3_D0 53
191 #define FPSR3_Z0 54
192 #define FPSR3_O0 55
193 #define FPSR3_U0 56
194 #define FPSR3_I0 57
195
196 //
197 // FPSR bits 58-63 Reserved -- Must be zero
198 //
199 #define FPSR_MBZ0 58
200 #define FPSR_MBZ0_V 0x3fUL L
201
202 //
203 // For setting up FPSR on kernel entry
204 // All traps are disabled.
205 //
206 #define FPSR_FOR_KERNEL 0x3f
207
208 #define FP_REG_SIZE 16 // 16 byte spill size
209 #define HIGHFP_REGS_LENGTH (96 * 16)
210
211 //
212 // Define hardware Task Priority Register (TPR)
213 //
214 //
215 // TPR bit positions
216 //
217 #define TPR_MIC 4 // Bits 0 - 3 ignored
218 #define TPR_MIC_LEN 4
219 #define TPR_MMI 16 // Mask Maskable Interrupt
220 //
221 // Define hardware Interrupt Status Register (ISR)
222 //
223 //
224 // ISR bit positions
225 //
226 #define ISR_CODE 0
227 #define ISR_CODE_LEN 16
228 #define ISR_CODE_MASK 0xFFFF
229 #define ISR_IA_VECTOR 16
230 #define ISR_IA_VECTOR_LEN 8
231 #define ISR_MBZ0 24
232 #define ISR_MBZ0_V 0xff
233 #define ISR_X 32
234 #define ISR_W 33
235 #define ISR_R 34
236 #define ISR_NA 35
237 #define ISR_SP 36
238 #define ISR_RS 37
239 #define ISR_IR 38
240 #define ISR_NI 39
241 #define ISR_MBZ1 40
242 #define ISR_EI 41
243 #define ISR_ED 43
244 #define ISR_MBZ2 44
245 #define ISR_MBZ2_V 0xfffff
246
247 //
248 // ISR codes
249 //
250 // For General exceptions: ISR{3:0}
251 //
252 #define ISR_ILLEGAL_OP 0 // Illegal operation fault
253 #define ISR_PRIV_OP 1 // Privileged operation fault
254 #define ISR_PRIV_REG 2 // Privileged register fauls
255 #define ISR_RESVD_REG 3 // Reserved register/field flt
256 #define ISR_ILLEGAL_ISA 4 // Disabled instruction set transition fault
257 //
258 // Define hardware Default Control Register (DCR)
259 //
260 //
261 // DCR bit positions
262 //
263 #define DCR_PP 0
264 #define DCR_BE 1
265 #define DCR_LC 2
266 #define DCR_MBZ0 4
267 #define DCR_MBZ0_V 0xf
268 #define DCR_DM 8
269 #define DCR_DP 9
270 #define DCR_DK 10
271 #define DCR_DX 11
272 #define DCR_DR 12
273 #define DCR_DA 13
274 #define DCR_DD 14
275 #define DCR_DEFER_ALL 0x7f00
276 #define DCR_MBZ1 2
277 #define DCR_MBZ1_V 0xffffffffffffUL L
278
279 //
280 // Define hardware RSE Configuration Register
281 //
282 // RS Configuration (RSC) bit field positions
283 //
284 #define RSC_MODE 0
285 #define RSC_PL 2
286 #define RSC_BE 4
287 #define RSC_MBZ0 5
288 #define RSC_MBZ0_V 0x3ff
289 #define RSC_LOADRS 16
290 #define RSC_LOADRS_LEN 14
291 #define RSC_MBZ1 30
292 #define RSC_MBZ1_V 0x3ffffffffUL L
293
294 //
295 // RSC modes
296 //
297 #define RSC_MODE_LY (0x0) // Lazy
298 #define RSC_MODE_SI (0x1) // Store intensive
299 #define RSC_MODE_LI (0x2) // Load intensive
300 #define RSC_MODE_EA (0x3) // Eager
301 //
302 // RSC Endian bit values
303 //
304 #define RSC_BE_LITTLE 0
305 #define RSC_BE_BIG 1
306
307 //
308 // Define Interruption Function State (IFS) Register
309 //
310 // IFS bit field positions
311 //
312 #define IFS_IFM 0
313 #define IFS_IFM_LEN 38
314 #define IFS_MBZ0 38
315 #define IFS_MBZ0_V 0x1ffffff
316 #define IFS_V 63
317 #define IFS_V_LEN 1
318
319 //
320 // IFS is valid when IFS_V = IFS_VALID
321 //
322 #define IFS_VALID 1
323
324 //
325 // Define Page Table Address (PTA)
326 //
327 #define PTA_VE 0
328 #define PTA_VF 8
329 #define PTA_SIZE 2
330 #define PTA_SIZE_LEN 6
331 #define PTA_BASE 15
332
333 //
334 // Define Region Register (RR)
335 //
336 //
337 // RR bit field positions
338 //
339 #define RR_VE 0
340 #define RR_MBZ0 1
341 #define RR_PS 2
342 #define RR_PS_LEN 6
343 #define RR_RID 8
344 #define RR_RID_LEN 24
345 #define RR_MBZ1 32
346
347 //
348 // SAL uses region register 0 and RID of 1000
349 //
350 #define SAL_RID 0x1000
351 #define SAL_RR_REG 0x0
352 #define SAL_TR 0x0
353
354 //
355 // Total number of region registers
356 //
357 #define RR_SIZE 8
358
359 //
360 // Define Protection Key Register (PKR)
361 //
362 // PKR bit field positions
363 //
364 #define PKR_V 0
365 #define PKR_WD 1
366 #define PKR_RD 2
367 #define PKR_XD 3
368 #define PKR_MBZ0 4
369 #define PKR_KEY 8
370 #define PKR_KEY_LEN 24
371 #define PKR_MBZ1 32
372
373 #define PKR_VALID (1 << PKR_V)
374
375 //
376 // Number of protection key registers
377 //
378 #define PKRNUM 8
379
380 //
381 // Define Interruption TLB Insertion register (ITIR)
382 //
383 //
384 // Define Translation Insertion Format (TR)
385 //
386 // PTE0 bit field positions
387 //
388 #define PTE0_P 0
389 #define PTE0_MBZ0 1
390 #define PTE0_MA 2
391 #define PTE0_A 5
392 #define PTE0_D 6
393 #define PTE0_PL 7
394 #define PTE0_AR 9
395 #define PTE0_PPN 12
396 #define PTE0_MBZ1 48
397 #define PTE0_ED 52
398 #define PTE0_IGN0 53
399
400 //
401 // ITIR bit field positions
402 //
403 #define ITIR_MBZ0 0
404 #define ITIR_PS 2
405 #define ITIR_PS_LEN 6
406 #define ITIR_KEY 8
407 #define ITIR_KEY_LEN 24
408 #define ITIR_MBZ1 32
409 #define ITIR_MBZ1_LEN 16
410 #define ITIR_PPN 48
411 #define ITIR_PPN_LEN 15
412 #define ITIR_MBZ2 63
413
414 #define ATTR_IPAGE 0x661 // Access Rights = RWX (bits 11-9=011), PL 0(8-7=0)
415 #define ATTR_DEF_BITS 0x661 // Access Rights = RWX (bits 11-9=010), PL 0(8-7=0)
416 // Dirty (bit 6=1), Accessed (bit 5=1),
417 // MA WB (bits 4-2=000), Present (bit 0=1)
418 //
419 // Memory access rights
420 //
421 #define AR_UR_KR 0x0 // user/kernel read
422 #define AR_URX_KRX 0x1 // user/kernel read and execute
423 #define AR_URW_KRW 0x2 // user/kernel read & write
424 #define AR_URWX_KRWX 0x3 // user/kernel read,write&execute
425 #define AR_UR_KRW 0x4 // user read/kernel read,write
426 #define AR_URX_KRWX 0x5 // user read/execute, kernel all
427 #define AR_URWX_KRW 0x6 // user all, kernel read & write
428 #define AR_UX_KRX 0x7 // user execute only, kernel read and execute
429 //
430 // Memory attribute values
431 //
432 //
433 // The next 4 are all cached, non-sequential & speculative, coherent
434 //
435 #define MA_WBU 0x0 // Write back, unordered
436 //
437 // The next 3 are all non-cached, sequential & non-speculative
438 //
439 #define MA_UC 0x4 // Non-coalescing, sequential & non-speculative
440 #define MA_UCE 0x5 // Non-coalescing, sequential, non-speculative
441 // & fetchadd exported
442 //
443 #define MA_WC 0x6 // Non-cached, Coalescing, non-seq., spec.
444 #define MA_NAT 0xf // NaT page
445 //
446 // Definition of the offset of TRAP/INTERRUPT/FAULT handlers from the
447 // base of IVA (Interruption Vector Address)
448 //
449 #define IVT_SIZE 0x8000
450 #define EXTRA_ALIGNMENT 0x1000
451
452 #define OFF_VHPTFLT 0x0000 // VHPT Translation fault
453 #define OFF_ITLBFLT 0x0400 // Instruction TLB fault
454 #define OFF_DTLBFLT 0x0800 // Data TLB fault
455 #define OFF_ALTITLBFLT 0x0C00 // Alternate ITLB fault
456 #define OFF_ALTDTLBFLT 0x1000 // Alternate DTLB fault
457 #define OFF_NESTEDTLBFLT 0x1400 // Nested TLB fault
458 #define OFF_IKEYMISSFLT 0x1800 // Inst Key Miss fault
459 #define OFF_DKEYMISSFLT 0x1C00 // Data Key Miss fault
460 #define OFF_DIRTYBITFLT 0x2000 // Dirty-Bit fault
461 #define OFF_IACCESSBITFLT 0x2400 // Inst Access-Bit fault
462 #define OFF_DACCESSBITFLT 0x2800 // Data Access-Bit fault
463 #define OFF_BREAKFLT 0x2C00 // Break Inst fault
464 #define OFF_EXTINT 0x3000 // External Interrupt
465 //
466 // Offset 0x3400 to 0x0x4C00 are reserved
467 //
468 #define OFF_PAGENOTPFLT 0x5000 // Page Not Present fault
469 #define OFF_KEYPERMFLT 0x5100 // Key Permission fault
470 #define OFF_IACCESSRTFLT 0x5200 // Inst Access-Rights flt
471 #define OFF_DACCESSRTFLT 0x5300 // Data Access-Rights fault
472 #define OFF_GPFLT 0x5400 // General Exception fault
473 #define OFF_FPDISFLT 0x5500 // Disable-FP fault
474 #define OFF_NATFLT 0x5600 // NAT Consumption fault
475 #define OFF_SPECLNFLT 0x5700 // Speculation fault
476 #define OFF_DBGFLT 0x5900 // Debug fault
477 #define OFF_ALIGNFLT 0x5A00 // Unaligned Reference fault
478 #define OFF_LOCKDREFFLT 0x5B00 // Locked Data Reference fault
479 #define OFF_FPFLT 0x5C00 // Floating Point fault
480 #define OFF_FPTRAP 0x5D00 // Floating Point Trap
481 #define OFF_LOPRIVTRAP 0x5E00 // Lower-Privilege Transfer Trap
482 #define OFF_TAKENBRTRAP 0x5F00 // Taken Branch Trap
483 #define OFF_SSTEPTRAP 0x6000 // Single Step Trap
484 //
485 // Offset 0x6100 to 0x6800 are reserved
486 //
487 #define OFF_IA32EXCEPTN 0x6900 // iA32 Exception
488 #define OFF_IA32INTERCEPT 0x6A00 // iA32 Intercept
489 #define OFF_IA32INT 0x6B00 // iA32 Interrupt
490 #define NUMBER_OF_VECTORS 0x100
491 //
492 // Privilege levels
493 //
494 #define PL_KERNEL 0
495 #define PL_USER 3
496
497 //
498 // Instruction set (IS) bits
499 //
500 #define IS_IA64 0
501 #define IS_IA 1
502
503 //
504 // RSC while in kernel: enabled, little endian, PL = 0, eager mode
505 //
506 #define RSC_KERNEL ((RSC_MODE_EA << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
507
508 //
509 // Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
510 //
511 #define RSC_KERNEL_LAZ ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
512
513 //
514 // RSE disabled: disabled, PL = 0, little endian, eager mode
515 //
516 #define RSC_KERNEL_DISABLED ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
517
518 #define NAT_BITS_PER_RNAT_REG 63
519
520 //
521 // Macros for generating PTE0 and PTE1 value
522 //
523 #define PTE0(ed, ppn12_47, ar, pl, d, a, ma, p) \
524 ( ( ed << PTE0_ED ) | \
525 ( ppn12_47 << PTE0_PPN ) | \
526 ( ar << PTE0_AR ) | \
527 ( pl << PTE0_PL ) | \
528 ( d << PTE0_D ) | \
529 ( a << PTE0_A ) | \
530 ( ma << PTE0_MA ) | \
531 ( p << PTE0_P ) \
532 )
533
534 #define ITIR(ppn48_63, key, ps) \
535 ( ( ps << ITIR_PS ) | \
536 ( key << ITIR_KEY ) | \
537 ( ppn48_63 << ITIR_PPN ) \
538 )
539
540 //
541 // Macro to generate mask value from bit position. The result is a
542 // 64-bit.
543 //
544 #define BITMASK(bp, value) (value << bp)
545
546 #define BUNDLE_SIZE 16
547 #define SPURIOUS_INT 0xF
548
549 #define FAST_DISABLE_INTERRUPTS rsm BITMASK (PSR_I, 1);;
550
551 #define FAST_ENABLE_INTERRUPTS ssm BITMASK (PSR_I, 1);;
552
553 #endif