added couple of PAL proc related constants
[mirror_edk2.git] / OldMdePkg / Include / Library / PalCallLib.h
1 /** @file
2 PAL Call Services
3
4 Copyright (c) 2006 -2007, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 Module Name: PalCallLib.h
15
16 **/
17
18 #ifndef __PAL_CALL_LIB_H__
19 #define __PAL_CALL_LIB_H__
20
21 //
22 // CacheType of PAL_CACHE_FLUSH.
23 //
24 #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
25 #define PAL_CACHE_FLUSH_DATA_ALL 2
26 #define PAL_CACHE_FLUSH_ALL 3
27 #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
28
29
30 //
31 // Bitmask of Opearation of PAL_CACHE_FLUSH.
32 //
33 #define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0
34 #define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0
35 #define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1
36 #define PAL_CACHE_FLUSH_NO_INTERRUPT 0
37
38 /**
39
40 PAL Procedure - PAL_CACHE_FLUSH.
41
42 Flush the instruction or data caches. It is required by IPF.
43 The PAL procedure supports the Static Registers calling
44 convention. It could be called at virtual mode and physical
45 mode.
46
47 @param Index Index of PAL_CACHE_FLUSH within the
48 list of PAL procedures.
49
50 @param CacheType Unsigned 64-bit integer indicating
51 which cache to flush.
52
53 @param Operation Formatted bit vector indicating the
54 operation of this call.
55
56 @param ProgressIndicator Unsigned 64-bit integer specifying
57 the starting position of the flush
58 operation.
59
60 @return R9 Unsigned 64-bit integer specifying the vector
61 number of the pending interrupt.
62
63 @return R10 Unsigned 64-bit integer specifying the
64 starting position of the flush operation.
65
66 @return R11 Unsigned 64-bit integer specifying the vector
67 number of the pending interrupt.
68
69 @return Status 2 - Call completed without error, but a PMI
70 was taken during the execution of this
71 procedure.
72
73 @return Status 1 - Call has not completed flushing due to
74 a pending interrupt.
75
76 @return Status 0 - Call completed without error
77
78 @return Status -2 - Invalid argument
79
80 @return Status -3 - Call completed with error
81
82 **/
83 #define PAL_CACHE_FLUSH 1
84
85
86 //
87 // Attributes of PAL_CACHE_CONFIG_INFO1
88 //
89 #define PAL_CACHE_ATTR_WT 0
90 #define PAL_CACHE_ATTR_WB 1
91
92 //
93 // PAL_CACHE_CONFIG_INFO1.StoreHint
94 //
95 #define PAL_CACHE_STORE_TEMPORAL 0
96 #define PAL_CACHE_STORE_NONE_TEMPORAL 3
97
98 //
99 // PAL_CACHE_CONFIG_INFO1.StoreHint
100 //
101 #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
102 #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
103
104 //
105 // PAL_CACHE_CONFIG_INFO1.StoreHint
106 //
107 #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
108 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
109 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
110
111 //
112 // Detail the characteristics of a given processor controlled
113 // cache in the cache hierarchy.
114 //
115 typedef struct {
116 UINT64 IsUnified : 1;
117 UINT64 Attributes : 2;
118 UINT64 Associativity:8;
119 UINT64 LineSize:8;
120 UINT64 Stride:8;
121 UINT64 StoreLatency:8;
122 UINT64 StoreHint:8;
123 UINT64 LoadHint:8;
124 } PAL_CACHE_INFO_RETURN1;
125
126 //
127 // Detail the characteristics of a given processor controlled
128 // cache in the cache hierarchy.
129 //
130 typedef struct {
131 UINT64 CacheSize:32;
132 UINT64 AliasBoundary:8;
133 UINT64 TagLsBits:8;
134 UINT64 TagMsBits:8;
135 } PAL_CACHE_INFO_RETURN2;
136
137 /**
138
139 PAL Procedure - PAL_CACHE_INFO.
140
141 Return detailed instruction or data cache information. It is
142 required by IPF. The PAL procedure supports the Static
143 Registers calling convention. It could be called at virtual
144 mode and physical mode.
145
146 @param Index Index of PAL_CACHE_INFO within the list of
147 PAL procedures.
148
149 @param CacheLevel Unsigned 64-bit integer specifying the
150 level in the cache hierarchy for which
151 information is requested. This value must
152 be between 0 and one less than the value
153 returned in the cache_levels return value
154 from PAL_CACHE_SUMMARY.
155
156 @param CacheType Unsigned 64-bit integer with a value of 1
157 for instruction cache and 2 for data or
158 unified cache. All other values are
159 reserved.
160
161 @param Reserved Should be 0.
162
163
164 @return R9 Detail the characteristics of a given
165 processor controlled cache in the cache
166 hierarchy. See PAL_CACHE_INFO_RETURN1.
167
168 @return R10 Detail the characteristics of a given
169 processor controlled cache in the cache
170 hierarchy. See PAL_CACHE_INFO_RETURN2.
171
172 @return R11 Reserved with 0.
173
174
175 @return Status 0 - Call completed without error
176
177 @return Status -2 - Invalid argument
178
179 @return Status -3 - Call completed with error
180
181 **/
182 #define PAL_CACHE_INFO 2
183
184
185
186 //
187 // Level of PAL_CACHE_INIT.
188 //
189 #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
190
191 //
192 // CacheType
193 //
194 #define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1
195 #define PAL_CACHE_INIT_TYPE_DATA 0x2
196 #define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3
197
198 //
199 // Restrict of PAL_CACHE_INIT.
200 //
201 #define PAL_CACHE_INIT_NO_RESTRICT 0
202 #define PAL_CACHE_INIT_RESTRICTED 1
203
204 /**
205
206 PAL Procedure - PAL_CACHE_INIT.
207
208 Initialize the instruction or data caches. It is required by
209 IPF. The PAL procedure supports the Static Registers calling
210 convention. It could be called at physical mode.
211
212 @param Index Index of PAL_CACHE_INIT within the list of PAL
213 procedures.
214
215 @param Level Unsigned 64-bit integer containing the level of
216 cache to initialize. If the cache level can be
217 initialized independently, only that level will
218 be initialized. Otherwise
219 implementation-dependent side-effects will
220 occur.
221
222 @param CacheType Unsigned 64-bit integer with a value of 1 to
223 initialize the instruction cache, 2 to
224 initialize the data cache, or 3 to
225 initialize both. All other values are
226 reserved.
227
228 @param Restrict Unsigned 64-bit integer with a value of 0 or
229 1. All other values are reserved. If
230 restrict is 1 and initializing the specified
231 level and cache_type of the cache would
232 cause side-effects, PAL_CACHE_INIT will
233 return -4 instead of initializing the cache.
234
235
236 @return Status 0 - Call completed without error
237
238 @return Status -2 - Invalid argument
239
240 @return Status -3 - Call completed with error.
241
242 @return Status -4 - Call could not initialize the specified
243 level and cache_type of the cache without
244 side-effects and restrict was 1.
245
246 **/
247 #define PAL_CACHE_INIT 3
248
249
250 //
251 // PAL_CACHE_PROTECTION.Method.
252 //
253 #define PAL_CACHE_PROTECTION_NONE_PROTECT 0
254 #define PAL_CACHE_PROTECTION_ODD_PROTECT 1
255 #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
256 #define PAL_CACHE_PROTECTION_ECC_PROTECT 3
257
258
259
260 //
261 // PAL_CACHE_PROTECTION.TagOrData.
262 //
263 #define PAL_CACHE_PROTECTION_PROTECT_DATA 0
264 #define PAL_CACHE_PROTECTION_PROTECT_TAG 1
265 #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
266 #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
267
268 //
269 // 32-bit protection information structures.
270 //
271 typedef struct {
272 UINT32 DataBits:8;
273 UINT32 TagProtLsb:6;
274 UINT32 TagProtMsb:6;
275 UINT32 ProtBits:6;
276 UINT32 Method:4;
277 UINT32 TagOrData:2;
278 } PAL_CACHE_PROTECTION;
279
280 /**
281
282 PAL Procedure - PAL_CACHE_PROT_INFO.
283
284 Return instruction or data cache protection information. It is
285 required by IPF. The PAL procedure supports the Static
286 Registers calling convention. It could be called at physical
287 mode and Virtual mode.
288
289 @param Index Index of PAL_CACHE_PROT_INFO within the list of
290 PAL procedures.
291
292 @param CacheLevel Unsigned 64-bit integer specifying the level
293 in the cache hierarchy for which information
294 is requested. This value must be between 0
295 and one less than the value returned in the
296 cache_levels return value from
297 PAL_CACHE_SUMMARY.
298
299 @param CacheType Unsigned 64-bit integer with a value of 1
300 for instruction cache and 2 for data or
301 unified cache. All other values are
302 reserved.
303
304 @return R9 Detail the characteristics of a given
305 processor controlled cache in the cache
306 hierarchy. See PAL_CACHE_PROTECTION[0..1].
307
308 @return R10 Detail the characteristics of a given
309 processor controlled cache in the cache
310 hierarchy. See PAL_CACHE_PROTECTION[2..3].
311
312 @return R11 Detail the characteristics of a given
313 processor controlled cache in the cache
314 hierarchy. See PAL_CACHE_PROTECTION[4..5].
315
316
317 @return Status 0 - Call completed without error
318
319 @return Status -2 - Invalid argument
320
321 @return Status -3 - Call completed with error.
322
323 **/
324 #define PAL_CACHE_PROT_INFO 38
325
326 /**
327
328 @param ThreadId The thread identifier of the logical
329 processor for which information is being
330 returned. This value will be unique on a per
331 core basis.
332
333 @param CoreId The core identifier of the logical processor
334 for which information is being returned.
335 This value will be unique on a per physical
336 processor package basis.
337
338 **/
339 typedef struct {
340 UINT64 ThreadId : 16;
341 UINT64 Reserved1: 16;
342 UINT64 CoreId: 16;
343 UINT64 Reserved2: 16;
344 } PAL_PCOC_N_CACHE_INFO1;
345
346 /**
347
348 @param LogicalAddress Logical address: geographical address
349 of the logical processor for which
350 information is being returned. This is
351 the same value that is returned by the
352 PAL_FIXED_ADDR procedure when it is
353 called on the logical processor.
354
355 **/
356 typedef struct {
357 UINT64 LogicalAddress : 16;
358 UINT64 Reserved1: 16;
359 UINT64 Reserved2: 32;
360 } PAL_PCOC_N_CACHE_INFO2;
361
362 /**
363
364 PAL Procedure - PAL_CACHE_SHARED_INFO.
365
366 Returns information on which logical processors share caches.
367 It is optional. The PAL procedure supports the Static
368 Registers calling convention. It could be called at physical
369 mode and Virtual mode.
370
371 @param Index Index of PAL_CACHE_SHARED_INFO within the list
372 of PAL procedures.
373
374 @param CacheLevel Unsigned 64-bit integer specifying the
375 level in the cache hierarchy for which
376 information is requested. This value must
377 be between 0 and one less than the value
378 returned in the cache_levels return value
379 from PAL_CACHE_SUMMARY.
380
381 @param CacheType Unsigned 64-bit integer with a value of 1
382 for instruction cache and 2 for data or
383 unified cache. All other values are
384 reserved.
385
386 @param ProcNumber Unsigned 64-bit integer that specifies for
387 which logical processor information is
388 being requested. This input argument must
389 be zero for the first call to this
390 procedure and can be a maximum value of
391 one less than the number of logical
392 processors sharing this cache, which is
393 returned by the num_shared return value.
394
395 @return R9 Unsigned integer that returns the number of
396 logical processors that share the processor
397 cache level and type, for which information was
398 requested.
399
400 @return R10 The format of PAL_PCOC_N_CACHE_INFO1.
401
402 @return R11 The format of PAL_PCOC_N_CACHE_INFO2.
403
404 @return Status 0 - Call completed without error
405
406 @return Status -1 - Unimplemented procedure
407
408 @return Status -2 - Invalid argument
409
410 @return Status -3 - Call completed with error.
411
412 **/
413 #define PAL_CACHE_SHARED_INFO 43
414
415
416 /**
417
418 PAL Procedure - PAL_CACHE_SUMMARY.
419
420 Return a summary of the cache hierarchy. It is required by
421 IPF. The PAL procedure supports the Static Registers calling
422 convention. It could be called at physical mode and Virtual
423 mode.
424
425 @param Index Index of PAL_CACHE_SUMMARY within the list of
426 PAL procedures.
427
428
429 @return R9 CacheLevels Unsigned 64-bit integer denoting the
430 number of levels of cache
431 implemented by the processor.
432 Strictly, this is the number of
433 levels for which the cache
434 controller is integrated into the
435 processor (the cache SRAMs may be
436 external to the processor).
437
438 @return R10 UniqueCaches Unsigned 64-bit integer denoting the
439 number of unique caches implemented
440 by the processor. This has a maximum
441 of 2*cache_levels, but may be less
442 if any of the levels in the cache
443 hierarchy are unified caches or do
444 not have both instruction and data
445 caches.
446
447 @return Status 0 - Call completed without error
448
449 @return Status -2 - Invalid argument
450
451 @return Status -3 - Call completed with error.
452
453 **/
454 #define PAL_CACHE_SUMMARY 4
455
456
457 //
458 // Virtual Memory Attributes implemented by processor.
459 //
460 #define PAL_MEMORY_ATTR_WB 0
461 #define PAL_MEMORY_ATTR_WC 6
462 #define PAL_MEMORY_ATTR_UC 4
463 #define PAL_MEMORY_ATTR_UCE 5
464 #define PAL_MEMORY_ATTR_NATPAGE 7
465
466 /**
467
468 PAL Procedure - PAL_MEM_ATTRIB.
469
470 Return a list of supported memory attributes.. It is required
471 by IPF. The PAL procedure supports the Static Registers calling
472 convention. It could be called at physical mode and Virtual
473 mode.
474
475 @param Index Index of PAL_MEM_ATTRIB within the list of PAL
476 procedures.
477
478
479 @return R9 Attributes 8-bit vector of memory attributes
480 implemented by processor. See Virtual
481 Memory Attributes above.
482
483 @return Status 0 - Call completed without error
484
485 @return Status -2 - Invalid argument
486
487 @return Status -3 - Call completed with error.
488
489 **/
490
491 #define PAL_MEM_ATTRIB 5
492
493 /**
494
495 PAL Procedure - PAL_PREFETCH_VISIBILITY.
496
497 Used in architected sequence to transition pages from a
498 cacheable, speculative attribute to an uncacheable attribute.
499 It is required by IPF. The PAL procedure supports the Static
500 Registers calling convention. It could be called at physical
501 mode and Virtual mode.
502
503 @param Index Index of PAL_PREFETCH_VISIBILITY within the list
504 of PAL procedures.
505
506 @param TransitionType Unsigned integer specifying the type
507 of memory attribute transition that is
508 being performed.
509
510 @return Status 1 Call completed without error; this
511 call is not necessary on remote
512 processors.
513
514 @return Status 0 - Call completed without error
515
516 @return Status -2 - Invalid argument
517
518 @return Status -3 - Call completed with error.
519
520 **/
521 #define PAL_PREFETCH_VISIBILITY 41
522
523 /**
524
525 PAL Procedure - PAL_PTCE_INFO.
526
527 Return information needed for ptc.e instruction to purge
528 entire TC. It is required by IPF. The PAL procedure supports
529 the Static Registers calling convention. It could be called at
530 physical mode and Virtual mode.
531
532 @param Index Index of PAL_PTCE_INFO within the list
533 of PAL procedures.
534
535 @return R9 Unsigned 64-bit integer denoting the beginning
536 address to be used by the first PTCE instruction
537 in the purge loop.
538
539 @return R10 Two unsigned 32-bit integers denoting the loop
540 counts of the outer (loop 1) and inner (loop 2)
541 purge loops. count1 (loop 1) is contained in bits
542 63:32 of the parameter, and count2 (loop 2) is
543 contained in bits 31:0 of the parameter.
544
545 @return R11 Two unsigned 32-bit integers denoting the loop
546 strides of the outer (loop 1) and inner (loop 2)
547 purge loops. stride1 (loop 1) is contained in bits
548 63:32 of the parameter, and stride2 (loop 2) is
549 contained in bits 31:0 of the parameter.
550
551 @return Status 0 - Call completed without error
552
553 @return Status -2 - Invalid argument
554
555 @return Status -3 - Call completed with error.
556
557 **/
558 #define PAL_PTCE_INFO 6
559
560
561
562 /**
563
564 @param NumberSets Unsigned 8-bit integer denoting the number
565 of hash sets for the specified level
566 (1=fully associative)
567
568 @param NumberWays Unsigned 8-bit integer denoting the
569 associativity of the specified level
570 (1=direct).
571
572 @param NumberEntries Unsigned 16-bit integer denoting the
573 number of entries in the specified TC.
574
575
576 @param PageSizeIsOptimized Flag denoting whether the
577 specified level is optimized for
578 the region's preferred page size
579 (1=optimized) tc_pages indicates
580 which page sizes are usable by
581 this translation cache.
582
583 @param TcIsUnified Flag denoting whether the specified TC is
584 unified (1=unified).
585
586 @param EntriesReduction Flag denoting whether installed
587 translation registers will reduce
588 the number of entries within the
589 specified TC.
590
591 **/
592 typedef struct {
593 UINT64 NumberSets:8;
594 UINT64 NumberWays:8;
595 UINT64 NumberEntries:16;
596 UINT64 PageSizeIsOptimized:1;
597 UINT64 TcIsUnified:1;
598 UINT64 EntriesReduction:1;
599 } PAL_TC_INFO;
600
601 /**
602
603 PAL Procedure - PAL_VM_INFO.
604
605 Return detailed information about virtual memory features
606 supported in the processor. It is required by IPF. The PAL
607 procedure supports the Static Registers calling convention. It
608 could be called at physical mode and Virtual mode.
609
610 @param Index Index of PAL_VM_INFO within the list
611 of PAL procedures.
612
613 @param TcLevel Unsigned 64-bit integer specifying the level
614 in the TLB hierarchy for which information is
615 required. This value must be between 0 and one
616 less than the value returned in the
617 vm_info_1.num_tc_levels return value from
618 PAL_VM_SUMMARY.
619
620 @param TcType Unsigned 64-bit integer with a value of 1 for
621 instruction translation cache and 2 for data
622 or unified translation cache. All other values
623 are reserved.
624
625 @return R9 8-byte formatted value returning information
626 about the specified TC. See PAL_TC_INFO above.
627
628 @return R10 64-bit vector containing a bit for each page
629 size supported in the specified TC, where bit
630 position n indicates a page size of 2**n.
631
632 @return Status 0 - Call completed without error
633
634 @return Status -2 - Invalid argument
635
636 @return Status -3 - Call completed with error.
637
638 **/
639 #define PAL_VM_INFO 7
640
641
642 /**
643
644 PAL Procedure - PAL_VM_PAGE_SIZE.
645
646 Return virtual memory TC and hardware walker page sizes
647 supported in the processor. It is required by IPF. The PAL
648 procedure supports the Static Registers calling convention. It
649 could be called at physical mode and Virtual mode.
650
651 @param Index Index of PAL_VM_PAGE_SIZE within the list
652 of PAL procedures.
653
654
655 @return R9 64-bit vector containing a bit for each
656 architected page size that is supported for
657 TLB insertions and region registers.
658
659 @return R10 64-bit vector containing a bit for each
660 architected page size supported for TLB purge
661 operations.
662
663 @return Status 0 - Call completed without error
664
665 @return Status -2 - Invalid argument
666
667 @return Status -3 - Call completed with error.
668
669 **/
670 #define PAL_VM_PAGE_SIZE 34
671
672 /**
673
674 @param WalkerPresent 1-bit flag indicating whether a hardware
675 TLB walker is implemented (1 = walker
676 present).
677
678 @param WidthOfPhysicalAddress Unsigned 7-bit integer
679 denoting the number of bits of
680 physical address implemented.
681
682 @param WidthOfKey Unsigned 8-bit integer denoting the number
683 of bits mplemented in the PKR.key field.
684
685 @param MaxPkrIndex Unsigned 8-bit integer denoting the
686 maximum PKR index (number of PKRs-1).
687
688 @param HashTagId Unsigned 8-bit integer which uniquely
689 identifies the processor hash and tag
690 algorithm.
691
692 @param MaxDtrIndex Unsigned 8 bit integer denoting the
693 maximum data translation register index
694 (number of dtr entries - 1).
695
696 @param MaxItrIndex Unsigned 8 bit integer denoting the
697 maximum instruction translation register
698 index (number of itr entries - 1).
699
700 @param NumberOfUniqueTc Unsigned 8-bit integer denoting the
701 number of unique TCs implemented.
702 This is a maximum of
703 2*num_tc_levels.
704
705 @param NumberOfTcLevels Unsigned 8-bit integer denoting the
706 number of TC levels.
707
708 **/
709 typedef struct {
710 UINT64 WalkerPresent:1;
711 UINT64 WidthOfPhysicalAddress: 7;
712 UINT64 WidthOfKey:8;
713 UINT64 MaxPkrIndex:8;
714 UINT64 HashTagId:8;
715 UINT64 MaxDtrIndex:8;
716 UINT64 MaxItrIndex:8;
717 UINT64 NumberOfUniqueTc:8;
718 UINT64 NumberOfTcLevels:8;
719 } PAL_VM_INFO1;
720
721 /**
722
723 @param WidthOfVirtualAddress Unsigned 8-bit integer denoting
724 is the total number of virtual
725 address bits - 1.
726
727 @param WidthOfRid Unsigned 8-bit integer denoting the number
728 of bits implemented in the RR.rid field.
729
730 @param MaxPurgedTlbs Unsigned 16 bit integer denoting the
731 maximum number of concurrent outstanding
732 TLB purges allowed by the processor. A
733 value of 0 indicates one outstanding
734 purge allowed. A value of 216-1
735 indicates no limit on outstanding
736 purges. All other values indicate the
737 actual number of concurrent outstanding
738 purges allowed.
739
740 **/
741 typedef struct {
742 UINT64 WidthOfVirtualAddress:8;
743 UINT64 WidthOfRid:8;
744 UINT64 MaxPurgedTlbs:16;
745 UINT64 Reserved:32;
746 } PAL_VM_INFO2;
747
748 /**
749
750 PAL Procedure - PAL_VM_SUMMARY.
751
752 Return summary information about virtual memory features
753 supported in the processor. It is required by IPF. The PAL
754 procedure supports the Static Registers calling convention. It
755 could be called at physical mode and Virtual mode.
756
757 @param Index Index of PAL_VM_SUMMARY within the list
758 of PAL procedures.
759
760
761 @return R9 8-byte formatted value returning global virtual
762 memory information. See PAL_VM_INFO1 above.
763
764 @return R10 8-byte formatted value returning global virtual
765 memory information. See PAL_VM_INFO2 above.
766
767 @return Status 0 - Call completed without error
768
769 @return Status -2 - Invalid argument
770
771 @return Status -3 - Call completed with error.
772
773 **/
774 #define PAL_VM_SUMMARY 8
775
776
777 //
778 // Bit mask of TR_valid flag.
779 //
780 #define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0
781 #define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1
782 #define PAL_TR_DIRTY_IS_VALID BIT2
783 #define PAL_TR_MEMORY_ATTR_IS_VALID BIT3
784
785
786 /**
787
788 PAL Procedure - PAL_VM_TR_READ.
789
790 Read contents of a translation register. It is required by
791 IPF. The PAL procedure supports the Stacked Register calling
792 convention. It could be called at physical mode.
793
794 @param Index Index of PAL_VM_TR_READ within the list
795 of PAL procedures.
796
797 @param RegNumber Unsigned 64-bit number denoting which TR to
798 read.
799
800 @param TrType Unsigned 64-bit number denoting whether to
801 read an ITR (0) or DTR (1). All other values
802 are reserved.
803
804 @param TrBuffer 64-bit pointer to the 32-byte memory buffer in
805 which translation data is returned.
806
807 @return R9 Formatted bit vector denoting which fields are
808 valid. See TR_valid above.
809
810 @return Status 0 - Call completed without error
811
812 @return Status -2 - Invalid argument
813
814 @return Status -3 - Call completed with error.
815
816 **/
817 #define PAL_VM_TR_READ 261
818
819
820
821
822 //
823 // Bit Mask of Processor Bus Fesatures .
824 //
825
826 /**
827
828 When 0, bus data errors are detected and single bit errors are
829 corrected. When 1, no error detection or correction is done.
830
831 **/
832 #define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63
833
834
835 /**
836
837 When 0, bus address errors are signalled on the bus. When 1,
838 no bus errors are signalled on the bus. If Disable Bus Address
839 Error Checking is 1, this bit is ignored.
840
841 **/
842 #define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62
843
844
845
846
847 /**
848
849 When 0, bus errors are detected, single bit errors are
850 corrected., and a CMCI or MCA is generated internally to the
851 processor. When 1, no bus address errors are detected or
852 corrected.
853
854 **/
855 #define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61
856
857
858 /**
859
860 When 0, bus protocol errors (BINIT#) are signaled by the
861 processor on the bus. When 1, bus protocol errors (BINIT#) are
862 not signaled on the bus. If Disable Bus Initialization Event
863 Checking is 1, this bit is ignored.
864
865 **/
866 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60
867
868
869 /**
870
871 When 0, bus protocol errors (BINIT#) are detected and sampled
872 and an MCA is generated internally to the processor. When 1,
873 the processor will ignore bus protocol error conditions
874 (BINIT#).
875
876 **/
877 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59
878
879
880
881 /**
882
883 When 0, BERR# is signalled if a bus error is detected. When 1,
884 bus errors are not signalled on the bus.
885
886 **/
887 #define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58
888
889
890
891
892 /**
893
894 When 0, BERR# is signalled when internal processor requestor
895 initiated bus errors are detected. When 1, internal requester
896 bus errors are not signalled on the bus.
897
898 **/
899 #define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57
900
901
902 /**
903
904 When 0, the processor takes an MCA if BERR# is asserted. When
905 1, the processor ignores the BERR# signal.
906
907 **/
908 #define PAL_BUS_DISABLE_ERROR_CHECK BIT56
909
910
911 /**
912
913 When 0, the processor asserts BINIT# if it detects a parity
914 error on the signals which identify the transactions to which
915 this is a response. When 1, the processor ignores parity on
916 these signals.
917
918 **/
919 #define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55
920
921
922 /**
923
924 When 0, the in-order transaction queue is limited only by the
925 number of hardware entries. When 1, the processor's in-order
926 transactions queue is limited to one entry.
927
928 **/
929 #define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54
930
931 /**
932
933 Enable a bus cache line replacement transaction when a cache
934 line in the exclusive state is replaced from the highest level
935 processor cache and is not present in the lower level processor
936 caches. When 0, no bus cache line replacement transaction will
937 be seen on the bus. When 1, bus cache line replacement
938 transactions will be seen on the bus when the above condition is
939 detected.
940
941 **/
942 #define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53
943
944
945 /**
946
947 Enable a bus cache line replacement transaction when a cache
948 line in the shared or exclusive state is replaced from the
949 highest level processor cache and is not present in the lower
950 level processor caches.
951 When 0, no bus cache line replacement transaction will be seen
952 on the bus. When 1, bus cache line replacement transactions
953 will be seen on the bus when the above condition is detected.
954
955 **/
956 #define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52
957
958
959
960 /**
961
962 When 0, the data bus is configured at the 2x data transfer
963 rate.When 1, the data bus is configured at the 1x data
964 transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the
965 processor executes locked transactions atomically. When 1, the
966 processor masks the bus lock signal and executes locked
967 transactions as a non-atomic series of transactions.
968
969 **/
970 #define PAL_BUS_ENABLE_HALF_TRANSFER BIT30
971
972 /**
973
974 When 0, the processor will deassert bus request when finished
975 with each transaction. When 1, the processor will continue to
976 assert bus request after it has finished, if it was the last
977 agent to own the bus and if there are no other pending
978 requests.
979
980 **/
981 #define PAL_BUS_REQUEST_BUS_PARKING BIT29
982
983
984 /**
985
986 PAL Procedure - PAL_BUS_GET_FEATURES.
987
988 Return configurable processor bus interface features and their
989 current settings. It is required by IPF. The PAL procedure
990 supports the Stacked Register calling convention. It could be
991 called at physical mode.
992
993 @param Index Index of PAL_BUS_GET_FEATURES within the list
994 of PAL procedures.
995
996 @return R9 64-bit vector of features implemented.
997 (1=implemented, 0=not implemented)
998
999 @return R10 64-bit vector of current feature settings.
1000
1001 @return R11 64-bit vector of features controllable by
1002 software. (1=controllable, 0= not controllable)
1003
1004 @return Status 0 - Call completed without error
1005
1006 @return Status -2 - Invalid argument
1007
1008 @return Status -3 - Call completed with error.
1009
1010 **/
1011 #define PAL_BUS_GET_FEATURES 9
1012
1013 /**
1014
1015 PAL Procedure - PAL_BUS_SET_FEATURES.
1016
1017 Enable or disable configurable features in processor bus
1018 interface. It is required by IPF. It is required by IPF. The PAL procedure
1019 supports the Static Registers calling convention. It could be
1020 called at physical mode.
1021
1022 @param Index Index of PAL_BUS_SET_FEATURES within the list
1023 of PAL procedures.
1024
1025 @param FeatureSelect 64-bit vector denoting desired state of
1026 each feature (1=select, 0=non-select).
1027
1028 @return Status 0 - Call completed without error
1029
1030 @return Status -2 - Invalid argument
1031
1032 @return Status -3 - Call completed with error.
1033
1034 **/
1035 #define PAL_BUS_SET_FEATURES 10
1036
1037
1038 /**
1039
1040 PAL Procedure - PAL_DEBUG_INFO.
1041
1042 Return the number of instruction and data breakpoint
1043 registers. It is required by IPF. It is required by IPF. The
1044 PAL procedure supports the Static Registers calling
1045 convention. It could be called at physical mode and virtual
1046 mode.
1047
1048 @param Index Index of PAL_DEBUG_INFO within the list of PAL
1049 procedures.
1050
1051 @return R9 Unsigned 64-bit integer denoting the number of
1052 pairs of instruction debug registers implemented
1053 by the processor.
1054
1055 @return R10 Unsigned 64-bit integer denoting the number of
1056 pairs of data debug registers implemented by the
1057 processor.
1058
1059 @return Status 0 - Call completed without error
1060
1061 @return Status -2 - Invalid argument
1062
1063 @return Status -3 - Call completed with error.
1064
1065 **/
1066 #define PAL_DEBUG_INFO 11
1067
1068 /**
1069
1070 PAL Procedure - PAL_FIXED_ADDR.
1071
1072 Return the fixed component of a processor¡¯s directed address.
1073 It is required by IPF. It is required by IPF. The PAL
1074 procedure supports the Static Registers calling convention. It
1075 could be called at physical mode and virtual mode.
1076
1077 @param Index Index of PAL_FIXED_ADDR within the list of PAL
1078 procedures.
1079
1080 @return R9 Fixed geographical address of this processor.
1081
1082
1083 @return Status 0 - Call completed without error
1084
1085 @return Status -2 - Invalid argument
1086
1087 @return Status -3 - Call completed with error.
1088
1089 **/
1090 #define PAL_FIXED_ADDR 12
1091
1092 /**
1093
1094 PAL Procedure - PAL_FREQ_BASE.
1095
1096 Return the frequency of the output clock for use by the
1097 platform, if generated by the processor. It is optinal. The
1098 PAL procedure supports the Static Registers calling
1099 convention. It could be called at physical mode and virtual
1100 mode.
1101
1102 @param Index Index of PAL_FREQ_BASE within the list of PAL
1103 procedures.
1104
1105 @return R9 Base frequency of the platform if generated by the
1106 processor chip.
1107
1108
1109 @return Status 0 - Call completed without error
1110
1111 @return Status -1 - Unimplemented procedure
1112
1113 @return Status -2 - Invalid argument
1114
1115 @return Status -3 - Call completed with error.
1116
1117 **/
1118 #define PAL_FREQ_BASE 13
1119
1120
1121 /**
1122
1123 PAL Procedure - PAL_FREQ_RATIOS.
1124
1125 Return ratio of processor, bus, and interval time counter to
1126 processor input clock or output clock for platform use, if
1127 generated by the processor. It is required by IPF. The PAL
1128 procedure supports the Static Registers calling convention. It
1129 could be called at physical mode and virtual mode.
1130
1131 @param Index Index of PAL_FREQ_RATIOS within the list of PAL
1132 procedures.
1133
1134 @return R9 Ratio of the processor frequency to the input
1135 clock of the processor, if the platform clock is
1136 generated externally or to the output clock to the
1137 platform, if the platform clock is generated by
1138 the processor.
1139
1140 @return R10 Ratio of the bus frequency to the input clock of
1141 the processor, if the platform clock is generated
1142 externally or to the output clock to the platform,
1143 if the platform clock is generated by the
1144 processor.
1145
1146 @return R11 Ratio of the interval timer counter rate to input
1147 clock of the processor, if the platform clock is
1148 generated externally or to the output clock to the
1149 platform, if the platform clock is generated by
1150 the processor.
1151
1152 @return Status 0 - Call completed without error
1153
1154 @return Status -2 - Invalid argument
1155
1156 @return Status -3 - Call completed with error.
1157
1158 **/
1159 #define PAL_FREQ_RATIOS 14
1160
1161 /**
1162
1163 @param NumberOfLogicalProcessors Total number of logical
1164 processors on this physical
1165 processor package that are
1166 enabled.
1167
1168 @param ThreadsPerCore Number of threads per core.
1169
1170 @param CoresPerProcessor Total number of cores on this
1171 physical processor package.
1172
1173 @param PhysicalProcessorPackageId Physical processor package
1174 identifier which was
1175 assigned at reset by the
1176 platform or bus
1177 controller. This value may
1178 or may not be unique
1179 across the entire platform
1180 since it depends on the
1181 platform vendor's policy.
1182 **/
1183 typedef struct {
1184 UINT64 NumberOfLogicalProcessors:16;
1185 UINT64 ThreadsPerCore:8;
1186 UINT64 Reserved1:8;
1187 UINT64 CoresPerProcessor;
1188 UINT64 Reserved2:8;
1189 UINT64 PhysicalProcessorPackageId:8;
1190 UINT64 Reserved3:8;
1191 } PAL_LOGICAL_PROCESSPR_OVERVIEW;
1192
1193 /**
1194
1195 @param ThreadId The thread identifier of the logical
1196 processor for which information is being
1197 returned. This value will be unique on a per
1198 core basis.
1199
1200 @param CoreId The core identifier of the logical processor
1201 for which information is being returned.
1202 This value will be unique on a per physical
1203 processor package basis.
1204
1205 **/
1206 typedef struct {
1207 UINT64 ThreadId:16;
1208 UINT64 Reserved1:16;
1209 UINT64 CoreId:16;
1210 UINT64 Reserved2:16;
1211 } PAL_LOGICAL_PROCESSORN_INFO1;
1212
1213
1214 /**
1215
1216 @param LogicalAddress Geographical address of the logical
1217 processor for which information is being
1218 returned. This is the same value that is
1219 returned by the PAL_FIXED_ADDR procedure
1220 when it is called on the logical
1221 processor.
1222
1223
1224 **/
1225 typedef struct {
1226 UINT64 LogicalAddress:16;
1227 UINT64 Reserved:48;
1228 } PAL_LOGICAL_PROCESSORN_INFO2;
1229
1230 /**
1231
1232 PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.
1233
1234 Return information on which logical processors map to a
1235 physical processor die. It is optinal. The PAL procedure
1236 supports the Static Registers calling convention. It could be
1237 called at physical mode and virtual mode.
1238
1239 @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL
1240 procedures.
1241
1242 @param ProcessorNumber Signed 64-bit integer that specifies
1243 for which logical processor
1244 information is being requested. When
1245 this input argument is -1, information
1246 is returned about the logical
1247 processor on which the procedure call
1248 is made. This input argument must be
1249 in the range of 1 up to one less than
1250 the number of logical processors
1251 returned by num_log in the
1252 log_overview return value.
1253
1254
1255 @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.
1256
1257 @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.
1258
1259 @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.
1260
1261
1262 @return Status 0 - Call completed without error
1263
1264 @return Status -1 - Unimplemented procedure
1265
1266 @return Status -2 - Invalid argument
1267
1268 @return Status -3 - Call completed with error.
1269
1270 **/
1271 #define PAL_LOGICAL_TO_PHYSICAL 42
1272
1273
1274 /**
1275
1276 @param NumberOfPmcPairs Unsigned 8-bit number defining the
1277 number of generic PMC/PMD pairs.
1278
1279 @param WidthOfCounter Unsigned 8-bit number in the range
1280 0:60 defining the number of
1281 implemented counter bits.
1282
1283 @param TypeOfCycleCounting Unsigned 8-bit number defining the
1284 event type for counting processor
1285 cycles.
1286
1287
1288 @param TypeOfRetiredInstructionBundle Retired Unsigned 8-bit
1289 number defining the
1290 event type for retired
1291 instruction bundles.
1292
1293 **/
1294 typedef struct {
1295 UINT64 NumberOfPmcPairs:8;
1296 UINT64 WidthOfCounter:8;
1297 UINT64 TypeOfCycleCounting:8;
1298 UINT64 TypeOfRetiredInstructionBundle:8;
1299 UINT64 Reserved:32;
1300 } PAL_PERFORMANCE_INFO;
1301
1302 /**
1303
1304 PAL Procedure - PAL_PERF_MON_INFO.
1305
1306 Return the number and type of performance monitors. It is
1307 required by IPF. The PAL procedure supports the Static
1308 Registers calling convention. It could be called at physical
1309 mode and virtual mode.
1310
1311 @param Index Index of PAL_PERF_MON_INFO within the list of
1312 PAL procedures.
1313
1314 @param PerformanceBuffer An address to an 8-byte aligned
1315 128-byte memory buffer.
1316
1317
1318 @return R9 Information about the performance monitors
1319 implemented. See PAL_PERFORMANCE_INFO;
1320
1321 @return Status 0 - Call completed without error
1322
1323 @return Status -2 - Invalid argument
1324
1325 @return Status -3 - Call completed with error.
1326
1327 **/
1328 #define PAL_PERF_MON_INFO 15
1329
1330 /**
1331
1332 PAL Procedure - PAL_PLATFORM_ADDR.
1333
1334 Specify processor interrupt block address and I/O port space
1335 address. It is required by IPF. The PAL procedure supports the
1336 Static Registers calling convention. It could be called at
1337 physical mode and virtual mode.
1338
1339 @param Index Index of PAL_PLATFORM_ADDR within the list of
1340 PAL procedures.
1341
1342 @param Type Unsigned 64-bit integer specifying the type of
1343 block. 0 indicates that the processor interrupt
1344 block pointer should be initialized. 1 indicates
1345 that the processor I/O block pointer should be
1346 initialized.
1347
1348 @param Address Unsigned 64-bit integer specifying the address
1349 to which the processor I/O block or interrupt
1350 block shall be set. The address must specify
1351 an implemented physical address on the
1352 processor model, bit 63 is ignored.
1353
1354
1355 @return Status 0 - Call completed without error
1356
1357 @return Status -1 - Unimplemented procedure.
1358
1359 @return Status -2 - Invalid argument
1360
1361 @return Status -3 - Call completed with error.
1362
1363 **/
1364 #define PAL_PLATFORM_ADDR 16
1365
1366
1367 /**
1368
1369 @param EnableBerrPromotion Bit63. Enable BERR promotion. When
1370 1, the Bus Error (BERR) signal is
1371 promoted to the Bus Initialization
1372 (BINIT) signal, and the BINIT pin
1373 is asserted on the occurrence of
1374 each Bus Error. Setting this bit
1375 has no effect if BINIT signalling
1376 is disabled. (See
1377 PAL_BUS_GET/SET_FEATURES)
1378
1379 @param EnableMcaPromotion Bit62, Enable MCA promotion. When
1380 1, machine check aborts (MCAs) are
1381 promoted to the Bus Error signal,
1382 and the BERR pin is assert on each
1383 occurrence of an MCA. Setting this
1384 bit has no effect if BERR
1385 signalling is disabled. (See
1386 PAL_BUS_GET/SET_FEATURES)
1387
1388 @param EnableMcaToBinitPromotion Bit61, Enable MCA to BINIT
1389 promotion. When 1, machine
1390 check aborts (MCAs) are
1391 promoted to the Bus
1392 Initialization signal, and
1393 the BINIT pin is assert on
1394 each occurrence of an MCA.
1395 Setting this bit has no
1396 effect if BINIT signalling
1397 is disabled. (See
1398 PAL_BUS_GET/SET_FEATURES)
1399
1400 @param EnableCmciPromotion Bit60, Enable CMCI promotion When
1401 1, Corrected Machine Check
1402 Interrupts (CMCI) are promoted to
1403 MCAs. They are also further
1404 promoted to BERR if bit 39, Enable
1405 MCA promotion, is also set and
1406 they are promoted to BINIT if bit
1407 38, Enable MCA to BINIT promotion,
1408 is also set. This bit has no
1409 effect if MCA signalling is
1410 disabled (see
1411 PAL_BUS_GET/SET_FEATURES)
1412
1413 @param DisableCache Bit59, Disable Cache. When 0, the
1414 processor performs cast outs on
1415 cacheable pages and issues and responds
1416 to coherency requests normally. When 1,
1417 the processor performs a memory access
1418 for each reference regardless of cache
1419 contents and issues no coherence
1420 requests and responds as if the line
1421 were not present. Cache contents cannot
1422 be relied upon when the cache is
1423 disabled. WARNING: Semaphore
1424 instructions may not be atomic or may
1425 cause Unsupported Data Reference faults
1426 if caches are disabled.
1427
1428 @param DisableCoherency Bit58, Disable Coherency. When 0,
1429 the processor uses normal coherency
1430 requests and responses. When 1, the
1431 processor answers all requests as if
1432 the line were not present.
1433
1434 @param DisableDPM Bit57, Disable Dynamic Power Management
1435 (DPM). When 0, the hardware may reduce
1436 power consumption by removing the clock
1437 input from idle functional units. When 1,
1438 all functional units will receive clock
1439 input, even when idle.
1440
1441 @param DisableBinitWithTimeout Bit56, Disable a BINIT on
1442 internal processor time-out.
1443 When 0, the processor may
1444 generate a BINIT on an
1445 internal processor time-out.
1446 When 1, the processor will not
1447 generate a BINIT on an
1448 internal processor time-out.
1449 The event is silently ignored.
1450
1451
1452 @param EnableEnvNotification Bit55, Enable external
1453 notification when the processor
1454 detects hardware errors caused
1455 by environmental factors that
1456 could cause loss of
1457 deterministic behavior of the
1458 processor. When 1, this bit will
1459 enable external notification,
1460 when 0 external notification is
1461 not provided. The type of
1462 external notification of these
1463 errors is processor-dependent. A
1464 loss of processor deterministic
1465 behavior is considered to have
1466 occurred if these
1467 environmentally induced errors
1468 cause the processor to deviate
1469 from its normal execution and
1470 eventually causes different
1471 behavior which can be observed
1472 at the processor bus pins.
1473 Processor errors that do not
1474 have this effects (i.e.,
1475 software induced machine checks)
1476 may or may not be promoted
1477 depending on the processor
1478 implementation.
1479
1480 @param EnableVmsw Bit54, Enable the use of the vmsw
1481 instruction. When 0, the vmsw instruction
1482 causes a Virtualization fault when
1483 executed at the most privileged level.
1484 When 1, this bit will enable normal
1485 operation of the vmsw instruction.
1486
1487 @param EnableMcaOnDataPoisoning Bit53, Enable MCA signaling
1488 on data-poisoning event
1489 detection. When 0, a CMCI
1490 will be signaled on error
1491 detection. When 1, an MCA
1492 will be signaled on error
1493 detection. If this feature
1494 is not supported, then the
1495 corresponding argument is
1496 ignored when calling
1497 PAL_PROC_SET_FEATURES. Note
1498 that the functionality of
1499 this bit is independent of
1500 the setting in bit 60
1501 (Enable CMCI promotion), and
1502 that the bit 60 setting does
1503 not affect CMCI signaling
1504 for data-poisoning related
1505 events. Volume 2: Processor
1506 Abstraction Layer 2:431
1507 PAL_PROC_GET_FEATURES
1508
1509 @param DisablePState Bit52, Disable P-states. When 1, the PAL
1510 P-state procedures (PAL_PSTATE_INFO,
1511 PAL_SET_PSTATE, PAL_GET_PSTATE) will
1512 return with a status of -1
1513 (Unimplemented procedure).
1514
1515 @param DisableBranchPrediction Bit47, Disable Dynamic branch
1516 prediction. When 0, the
1517 processor may predict branch
1518 targets and speculatively
1519 execute, but may not commit
1520 results. When 1, the processor
1521 must wait until branch targets
1522 are known to execute.
1523
1524 @param DisableDynamicInsCachePrefetch Bit46, Disable
1525 DynamicInstruction Cache
1526 Prefetch. When 0, the
1527 processor may prefetch
1528 into the caches any
1529 instruction which has
1530 not been executed, but
1531 whose execution is
1532 likely. When 1,
1533 instructions may not be
1534 fetched until needed or
1535 hinted for execution.
1536 (Prefetch for a hinted
1537 branch is allowed even
1538 when dynamic instruction
1539 cache prefetch is
1540 disabled.)
1541
1542 @param DisableDynamicDataCachePrefetch Bit45, Disable Dynamic
1543 Data Cache Prefetch.
1544 When 0, the processor
1545 may prefetch into the
1546 caches any data which
1547 has not been accessed
1548 by instruction
1549 execution, but which
1550 is likely to be
1551 accessed. When 1, no
1552 data may be fetched
1553 until it is needed for
1554 instruction execution
1555 or is fetched by an
1556 lfetch instruction.
1557
1558 @param DisableSpontaneousDeferral Bit44, Disable Spontaneous
1559 Deferral. When 1, the
1560 processor may optionally
1561 defer speculative loads
1562 that do not encounter any
1563 exception conditions, but
1564 that trigger other
1565 implementation-dependent
1566 conditions (e.g., cache
1567 miss). When 0, spontaneous
1568 deferral is disabled.
1569
1570 @param DisableDynamicPrediction Bit43, Disable Dynamic
1571 Predicate Prediction. When
1572 0, the processor may predict
1573 predicate results and
1574 execute speculatively, but
1575 may not commit results until
1576 the actual predicates are
1577 known. When 1, the processor
1578 shall not execute predicated
1579 instructions until the
1580 actual predicates are known.
1581
1582 @param NoXr1ThroughXr3 Bit42, No XR1 through XR3 implemented.
1583 Denotes whether XR1 XR3 are
1584 implemented for machine check
1585 recovery. This feature may only be
1586 interrogated by PAL_PROC_GET_FEATURES.
1587 It may not be enabled or disabled by
1588 PAL_PROC_SET_FEATURES. The
1589 corresponding argument is ignored.
1590
1591 @param NoXipXpsrXfs Bit41, No XIP, XPSR, and XFS
1592 implemented. Denotes whether XIP, XPSR,
1593 and XFS are implemented for machine
1594 check recovery. This feature may only be
1595 interrogated by PAL_PROC_GET_FEATURES.
1596 It may not be enabled or disabled by
1597 PAL_PROC_SET_FEATURES. The corresponding
1598 argument is ignored.
1599
1600 @param NoVM Bit40, No Virtual Machine features implemented.
1601 Denotes whether PSR.vm is implemented. This
1602 feature may only be interrogated by
1603 PAL_PROC_GET_FEATURES. It may not be enabled or
1604 disabled by PAL_PROC_SET_FEATURES. The
1605 corresponding argument is ignored.
1606
1607 @param NoVariablePState Bit39, No Variable P-state
1608 performance: A value of 1, indicates
1609 that a processor implements
1610 techniques to optimize performance
1611 for the given P-state power budget
1612 by dynamically varying the
1613 frequency, such that maximum
1614 performance is achieved for the
1615 power budget. A value of 0,
1616 indicates that P-states have no
1617 frequency variation or very small
1618 frequency variations for their given
1619 power budget. This feature may only
1620 be interrogated by
1621 PAL_PROC_GET_FEATURES. it may not be
1622 enabled or disabled by
1623 PAL_PROC_SET_FEATURES. The
1624 corresponding argument is ignored.
1625
1626
1627 @param NoSimpleImpInUndefinedIns Bit38, No Simple
1628 implementation of
1629 unimplemented instruction
1630 addresses. Denotes how an
1631 unimplemented instruction
1632 address is recorded in IIP
1633 on an Unimplemented
1634 Instruction Address trap or
1635 fault. When 1, the full
1636 unimplemented address is
1637 recorded in IIP; when 0, the
1638 address is sign extended
1639 (virtual addresses) or zero
1640 extended (physical
1641 addresses). This feature may
1642 only be interrogated by
1643 PAL_PROC_GET_FEATURES. It
1644 may not be enabled or
1645 disabled by
1646 PAL_PROC_SET_FEATURES. The
1647 corresponding argument is
1648 ignored.
1649
1650 @param NoPresentPmi Bit37, No INIT, PMI, and LINT pins
1651 present. Denotes the absence of INIT,
1652 PMI, LINT0 and LINT1 pins on the
1653 processor. When 1, the pins are absent.
1654 When 0, the pins are present. This
1655 feature may only be interrogated by
1656 PAL_PROC_GET_FEATURES. It may not be
1657 enabled or disabled by
1658 PAL_PROC_SET_FEATURES. The corresponding
1659 argument is ignored.
1660
1661 @param FaultInUndefinedIns Bit36, No Unimplemented
1662 instruction address reported as
1663 fault. Denotes how the processor
1664 reports the detection of
1665 unimplemented instruction
1666 addresses. When 1, the processor
1667 reports an Unimplemented
1668 Instruction Address fault on the
1669 unimplemented address; when 0, it
1670 reports an Unimplemented
1671 Instruction Address trap on the
1672 previous instruction in program
1673 order. This feature may only be
1674 interrogated by
1675 PAL_PROC_GET_FEATURES. It may not
1676 be enabled or disabled by
1677 PAL_PROC_SET_FEATURES. The
1678 corresponding argument is
1679 ignored.
1680
1681 **/
1682 typedef struct {
1683 UINT64 Reserved1:36;
1684 UINT64 FaultInUndefinedIns:1;
1685 UINT64 NoPresentPmi:1;
1686 UINT64 NoSimpleImpInUndefinedIns:1;
1687 UINT64 NoVariablePState:1;
1688 UINT64 NoVM:1;
1689 UINT64 NoXipXpsrXfs:1;
1690 UINT64 NoXr1ThroughXr3:1;
1691 UINT64 DisableDynamicPrediction:1;
1692 UINT64 DisableSpontaneousDeferral:1;
1693 UINT64 DisableDynamicDataCachePrefetch:1;
1694 UINT64 DisableDynamicInsCachePrefetch:1;
1695 UINT64 DisableBranchPrediction:1;
1696 UINT64 Reserved2:4;
1697 UINT64 DisablePState:1;
1698 UINT64 EnableMcaOnDataPoisoning:1;
1699 UINT64 EnableVmsw:1;
1700 UINT64 EnableEnvNotification:1;
1701 UINT64 DisableBinitWithTimeout:1;
1702 UINT64 DisableDPM:1;
1703 UINT64 DisableCoherency:1;
1704 UINT64 DisableCache:1;
1705 UINT64 EnableCmciPromotion:1;
1706 UINT64 EnableMcaToBinitPromotion:1;
1707 UINT64 EnableMcaPromotion:1;
1708 UINT64 EnableBerrPromotion:1;
1709 } PAL_PROCESSOR_FEATURES;
1710
1711 /**
1712
1713 PAL Procedure - PAL_PROC_GET_FEATURES.
1714
1715 Return configurable processor features and their current
1716 setting. It is required by IPF. The PAL procedure supports the
1717 Static Registers calling convention. It could be called at
1718 physical mode and virtual mode.
1719
1720 @param Index Index of PAL_PROC_GET_FEATURES within the list of
1721 PAL procedures.
1722
1723 @param Reserved Reserved parameter.
1724
1725 @param FeatureSet Feature set information is being requested
1726 for.
1727
1728
1729 @return R9 64-bit vector of features implemented. See
1730 PAL_PROCESSOR_FEATURES.
1731
1732 @return R10 64-bit vector of current feature settings. See
1733 PAL_PROCESSOR_FEATURES.
1734
1735 @return R11 64-bit vector of features controllable by
1736 software.
1737
1738 @return Status 1 - Call completed without error; The
1739 feature_set passed is not supported but a
1740 feature_set of a larger value is supported.
1741
1742 @return Status 0 - Call completed without error
1743
1744 @return Status -2 - Invalid argument
1745
1746 @return Status -3 - Call completed with error.
1747
1748 @return Status -8 - feature_set passed is beyond the maximum
1749 feature_set supported
1750
1751 **/
1752 #define PAL_PROC_GET_FEATURES 17
1753
1754
1755 /**
1756
1757 PAL Procedure - PAL_PROC_SET_FEATURES.
1758
1759 Enable or disable configurable processor features. It is
1760 required by IPF. The PAL procedure supports the Static
1761 Registers calling convention. It could be called at physical
1762 mode.
1763
1764 @param Index Index of PAL_PROC_SET_FEATURES within the list of
1765 PAL procedures.
1766
1767 @param FeatureSelect 64-bit vector denoting desired state of
1768 each feature (1=select, 0=non-select).
1769
1770 @param FeatureSet Feature set to apply changes to. See
1771 PAL_PROC_GET_FEATURES for more information
1772 on feature sets.
1773
1774
1775
1776 @return Status 1 - Call completed without error; The
1777 feature_set passed is not supported but a
1778 feature_set of a larger value is supported
1779
1780 @return Status 0 - Call completed without error
1781
1782 @return Status -2 - Invalid argument
1783
1784 @return Status -3 - Call completed with error.
1785
1786 @return Status -8 - feature_set passed is beyond the maximum
1787 feature_set supported
1788
1789 **/
1790 #define PAL_PROC_SET_FEATURES 18
1791
1792
1793 //
1794 // Value of PAL_REGISTER_INFO.InfoRequest.
1795 //
1796 #define PAL_APPLICATION_REGISTER_IMPLEMENTED 0
1797 #define PAL_APPLICATION_REGISTER_READABLE 1
1798 #define PAL_CONTROL_REGISTER_IMPLEMENTED 2
1799 #define PAL_CONTROL_REGISTER_READABLE 3
1800
1801
1802 /**
1803
1804 PAL Procedure - PAL_REGISTER_INFO.
1805
1806 Return AR and CR register information. It is required by IPF.
1807 The PAL procedure supports the Static Registers calling
1808 convention. It could be called at physical mode and virtual
1809 mode.
1810
1811 @param Index Index of PAL_REGISTER_INFO within the list of
1812 PAL procedures.
1813
1814 @param InfoRequest Unsigned 64-bit integer denoting what
1815 register information is requested. See
1816 PAL_REGISTER_INFO.InfoRequest above.
1817
1818 @return R9 64-bit vector denoting information for registers
1819 0-63. Bit 0 is register 0, bit 63 is register 63.
1820
1821 @return R10 64-bit vector denoting information for registers
1822 64-127. Bit 0 is register 64, bit 63 is register
1823 127.
1824
1825
1826 @return Status 0 - Call completed without error
1827
1828 @return Status -2 - Invalid argument
1829
1830 @return Status -3 - Call completed with error.
1831
1832
1833 **/
1834 #define PAL_REGISTER_INFO 39
1835
1836 /**
1837
1838 PAL Procedure - PAL_RSE_INFO.
1839
1840 Return RSE information. It is required by IPF. The PAL
1841 procedure supports the Static Registers calling convention. It
1842 could be called at physical mode and virtual mode.
1843
1844 @param Index Index of PAL_RSE_INFO within the list of
1845 PAL procedures.
1846
1847 @param InfoRequest Unsigned 64-bit integer denoting what
1848 register information is requested. See
1849 PAL_REGISTER_INFO.InfoRequest above.
1850
1851 @return R9 Number of physical stacked general registers.
1852
1853 @return R10 RSE hints supported by processor.
1854
1855 @return Status 0 - Call completed without error
1856
1857 @return Status -2 - Invalid argument
1858
1859 @return Status -3 - Call completed with error.
1860
1861
1862 **/
1863 #define PAL_RSE_INFO 19
1864
1865 /**
1866
1867 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
1868 number that provides identification
1869 information about the PAL_B firmware.
1870
1871 @param PalVendor Is an unsigned 8-bit integer indicating the
1872 vendor of the PAL code.
1873
1874 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
1875 number that provides identification
1876 information about the PAL_A firmware. In
1877 the split PAL_A model, this return value
1878 is the version number of the
1879 processor-specific PAL_A. The generic
1880 PAL_A version is not returned by this
1881 procedure in the split PAL_A model.
1882
1883 **/
1884 typedef struct {
1885 UINT64 VersionOfPalB:16;
1886 UINT64 Reserved1:8;
1887 UINT64 PalVendor:8;
1888 UINT64 VersionOfPalA:16;
1889 UINT64 Reserved2:16;
1890 } PAL_VERSION_INFO;
1891
1892 /**
1893
1894 PAL Procedure - PAL_VERSION.
1895
1896 Return version of PAL code. It is required by IPF. The PAL
1897 procedure supports the Static Registers calling convention. It
1898 could be called at physical mode and virtual mode.
1899
1900 @param Index Index of PAL_VERSION within the list of
1901 PAL procedures.
1902
1903 @param InfoRequest Unsigned 64-bit integer denoting what
1904 register information is requested. See
1905 PAL_REGISTER_INFO.InfoRequest above.
1906
1907 @return R9 8-byte formatted value returning the minimum PAL
1908 version needed for proper operation of the
1909 processor. See PAL_VERSION_INFO above.
1910
1911 @return R10 8-byte formatted value returning the current PAL
1912 version running on the processor. See
1913 PAL_VERSION_INFO above.
1914
1915 @return Status 0 - Call completed without error
1916
1917 @return Status -2 - Invalid argument
1918
1919 @return Status -3 - Call completed with error.
1920
1921
1922 **/
1923 #define PAL_VERSION 20
1924
1925
1926
1927 //
1928 // Vectors of PAL_MC_CLEAR_LOG.pending
1929 //
1930 #define PAL_MC_PENDING BIT0
1931 #define PAL_INIT_PENDING BIT1
1932
1933 /**
1934
1935 PAL Procedure - PAL_MC_CLEAR_LOG.
1936
1937 Clear all error information from processor error logging
1938 registers. It is required by IPF. The PAL procedure supports
1939 the Static Registers calling convention. It could be called at
1940 physical mode and virtual mode.
1941
1942 @param Index Index of PAL_MC_CLEAR_LOG within the list of
1943 PAL procedures.
1944
1945
1946 @return R9 64-bit vector denoting whether an event is
1947 pending. See PAL_MC_CLEAR_LOG.pending above.
1948
1949
1950 @return Status 0 - Call completed without error
1951
1952 @return Status -2 - Invalid argument
1953
1954 @return Status -3 - Call completed with error.
1955
1956
1957 **/
1958 #define PAL_MC_CLEAR_LOG 21
1959
1960 /**
1961
1962 PAL Procedure - PAL_MC_DRAIN.
1963
1964 Ensure that all operations that could cause an MCA have
1965 completed. It is required by IPF. The PAL procedure supports
1966 the Static Registers calling convention. It could be called at
1967 physical mode and virtual mode.
1968
1969 @param Index Index of PAL_MC_DRAIN within the list of PAL
1970 procedures.
1971
1972
1973 @return Status 0 - Call completed without error
1974
1975 @return Status -2 - Invalid argument
1976
1977 @return Status -3 - Call completed with error.
1978
1979
1980 **/
1981 #define PAL_MC_DRAIN 22
1982
1983
1984 /**
1985
1986 PAL Procedure - PAL_MC_DYNAMIC_STATE.
1987
1988 Return Processor Dynamic State for logging by SAL. It is
1989 optional. The PAL procedure supports the Static Registers
1990 calling convention. It could be called at physical mode.
1991
1992 @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL
1993 procedures.
1994
1995 @param Offset Offset of the next 8 bytes of Dynamic Processor
1996 State to return. (multiple of 8).
1997
1998 @return R9 Unsigned 64-bit integer denoting bytes of Dynamic
1999 Processor State returned.
2000
2001 @return R10 Next 8 bytes of Dynamic Processor State.
2002
2003 @return Status 0 - Call completed without error
2004
2005 @return Status -1 - Unimplemented procedure.
2006
2007 @return Status -2 - Invalid argument
2008
2009 @return Status -3 - Call completed with error.
2010
2011
2012 **/
2013 #define PAL_MC_DYNAMIC_STATE 24
2014
2015
2016
2017 //
2018 // Values of PAL_MC_ERROR_INFO.InfoIndex.
2019 //
2020 #define PAL_PROCESSOR_ERROR_MAP 0
2021 #define PAL_PROCESSOR_STATE_PARAM 1
2022 #define PAL_STRUCTURE_SPECIFIC_ERROR 2
2023
2024 /**
2025
2026 @param CoreId Bit3:0, Processor core ID (default is 0 for
2027 processors with a single core)
2028
2029 @param ThreadId Bit7:4, Logical thread ID (default is 0 for
2030 processors that execute a single thread)
2031
2032 @param InfoOfInsCache Bit11:8, Error information is
2033 available for 1st, 2nd, 3rd, and 4th
2034 level instruction caches.
2035
2036 @param InfoOfDataCache Bit15:12, Error information is
2037 available for 1st, 2nd, 3rd, and 4th
2038 level data/unified caches.
2039
2040 @param InfoOfInsTlb Bit19:16 Error information is available
2041 for 1st, 2nd, 3rd, and 4th level
2042 instruction TLB.
2043
2044 @param InfoOfDataTlb Bit23:20, Error information is available
2045 for 1st, 2nd, 3rd, and 4th level
2046 data/unified TLB
2047
2048 @param InfoOfProcessorBus Bit27:24 Error information is
2049 available for the 1st, 2nd, 3rd,
2050 and 4th level processor bus
2051 hierarchy.
2052
2053 @param InfoOfRegisterFile Bit31:28 Error information is
2054 available on register file
2055 structures.
2056
2057 @param InfoOfMicroArch Bit47:32, Error information is
2058 available on micro-architectural
2059 structures.
2060
2061 **/
2062 typedef struct {
2063 UINT64 CoreId:4;
2064 UINT64 ThreadId:4;
2065 UINT64 InfoOfInsCache:4;
2066 UINT64 InfoOfDataCache:4;
2067 UINT64 InfoOfInsTlb:4;
2068 UINT64 InfoOfDataTlb:4;
2069 UINT64 InfoOfProcessorBus:4;
2070 UINT64 InfoOfRegisterFile:4;
2071 UINT64 InfoOfMicroArch:4;
2072 UINT64 Reserved:16;
2073 } PAL_MC_ERROR_INFO_LEVEL_INDEX;
2074
2075 //
2076 // Value of PAL_MC_ERROR_INFO.ErrorTypeIndex
2077 //
2078 #define PAL_ERR_INFO_BY_LEVEL_INDEX 0
2079 #define PAL_ERR_INFO_TARGET_ADDRESS 1
2080 #define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2
2081 #define PAL_ERR_INFO_REPONSER_INDENTIFIER 3
2082 #define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4
2083
2084 /**
2085
2086 @param Operation Bit3:0, Type of cache operation that caused
2087 the machine check: 0 - unknown or internal
2088 error 1 - load 2 - store 3 - instruction
2089 fetch or instruction prefetch 4 - data
2090 prefetch (both hardware and software) 5 -
2091 snoop (coherency check) 6 - cast out
2092 (explicit or implicit write-back of a cache
2093 line) 7 - move in (cache line fill)
2094
2095 @param FailedCacheLevel Bit5:4 Level of cache where the
2096 error occurred. A value of 0
2097 indicates the first level of cache.
2098
2099 @param FailedInDataPart Bit8, Failure located in the data
2100 part of the cache line.
2101
2102 @param FailedInTagPart Bit9, Failure located in the tag part
2103 of the cache line.
2104
2105 @param FailedInDataCache Bit10, Failure located in the data
2106 cache
2107
2108 @param FailedInInsCache Bit11, Failure located in the
2109 instruction cache.
2110
2111
2112 @param Mesi Bit14:12, 0 - cache line is invalid. 1 - cache
2113 line is held shared. 2 - cache line is held
2114 exclusive. 3 - cache line is modified. All other
2115 values are reserved.
2116
2117 @param MesiIsValid Bit15, The mesi field in the cache_check
2118 parameter is valid.
2119
2120 @param FailedWay Bit20:16, Failure located in the way of
2121 the cache indicated by this value.
2122
2123 @param WayIndexIsValid Bit21, The way and index field in the
2124 cache_check parameter is valid.
2125
2126 @param MultipleBitsError Bit23, A multiple-bit error was
2127 detected, and data was poisoned for
2128 the corresponding cache line during
2129 castout.
2130
2131 @param IndexOfCacheLineError Bit51:32, Index of the cache
2132 line where the error occurred.
2133
2134 @param InstructionSet Bit54, Instruction set. If this value
2135 is set to zero, the instruction that
2136 generated the machine check was an
2137 Intel Itanium instruction. If this bit
2138 is set to one, the instruction that
2139 generated the machine check was IA-32
2140 instruction.
2141
2142 @param InstructionSetIsValid Bit55, The is field in the
2143 cache_check parameter is valid.
2144
2145 @param PrivilegeLevel Bit57:56, Privilege level. The
2146 privilege level of the instruction
2147 bundle responsible for generating the
2148 machine check.
2149
2150 @param PrivilegeLevelIsValide Bit58, The pl field of the
2151 cache_check parameter is
2152 valid.
2153
2154 @param McCorrected Bit59, Machine check corrected: This bit
2155 is set to one to indicate that the machine
2156 check has been corrected.
2157
2158 @param TargetAddressIsValid Bit60, Target address is valid:
2159 This bit is set to one to
2160 indicate that a valid target
2161 address has been logged.
2162
2163 @param RequesterIdentifier Bit61, Requester identifier: This
2164 bit is set to one to indicate that
2165 a valid requester identifier has
2166 been logged.
2167
2168 @param ResponserIdentifier Bit62, Responder identifier: This
2169 bit is set to one to indicate that
2170 a valid responder identifier has
2171 been logged.
2172
2173 @param PreciseInsPointer Bit63, Precise instruction pointer.
2174 This bit is set to one to indicate
2175 that a valid precise instruction
2176 pointer has been logged.
2177
2178 **/
2179 typedef struct {
2180 UINT64 Operation:4;
2181 UINT64 FailedCacheLevel:2;
2182 UINT64 Reserved1:2;
2183 UINT64 FailedInDataPart:1;
2184 UINT64 FailedInTagPart:1;
2185 UINT64 FailedInDataCache:1;
2186 UINT64 FailedInInsCache:1;
2187 UINT64 Mesi:3;
2188 UINT64 MesiIsValid:1;
2189 UINT64 FailedWay:5;
2190 UINT64 WayIndexIsValid:1;
2191
2192 UINT64 Reserved2:1;
2193 UINT64 MultipleBitsError:1;
2194 UINT64 Reserved3:8;
2195 UINT64 IndexOfCacheLineError:20;
2196 UINT64 Reserved4:2;
2197 UINT64 InstructionSet:1;
2198 UINT64 InstructionSetIsValid:1;
2199
2200 UINT64 PrivilegeLevel:2;
2201 UINT64 PrivilegeLevelIsValide:1;
2202
2203 UINT64 McCorrected:1;
2204
2205 UINT64 TargetAddressIsValid:1;
2206 UINT64 RequesterIdentifier:1;
2207 UINT64 ResponserIdentifier:1;
2208 UINT64 PreciseInsPointer:1;
2209
2210 } PAL_CACHE_CHECK_INFO;
2211
2212 /**
2213
2214 @param FailedSlot Bit7:0, Slot number of the translation
2215 register where the failure occurred.
2216
2217 @param FailedSlotIsValid Bit8, The tr_slot field in the
2218 TLB_check parameter is valid.
2219
2220 @param TlbLevel Bit11:10, The level of the TLB where the
2221 error occurred. A value of 0 indicates the
2222 first level of TLB
2223
2224 @param FailedInDataTr Bit16, Error occurred in the data
2225 translation registers.
2226
2227 @param FailedInInsTr Bit17, Error occurred in the instruction
2228 translation registers
2229
2230 @param FailedInDataTc Bit18, Error occurred in data
2231 translation cache.
2232
2233 @param FailedInInsTc Bit19, Error occurred in the instruction
2234 translation cache.
2235
2236 @param FailedOperation Bit23:20, Type of cache operation that
2237 caused the machine check: 0 - unknown
2238 1 - TLB access due to load instruction
2239 2 - TLB access due to store
2240 instruction 3 - TLB access due to
2241 instruction fetch or instruction
2242 prefetch 4 - TLB access due to data
2243 prefetch (both hardware and software)
2244 5 - TLB shoot down access 6 - TLB
2245 probe instruction (probe, tpa) 7 -
2246 move in (VHPT fill) 8 - purge (insert
2247 operation that purges entries or a TLB
2248 purge instruction) All other values
2249 are reserved.
2250
2251 @param InstructionSet Bit54, Instruction set. If this value
2252 is set to zero, the instruction that
2253 generated the machine check was an
2254 Intel Itanium instruction. If this bit
2255 is set to one, the instruction that
2256 generated the machine check was IA-32
2257 instruction.
2258
2259 @param InstructionSetIsValid Bit55, The is field in the
2260 TLB_check parameter is valid.
2261
2262 @param PrivelegeLevel Bit57:56, Privilege level. The
2263 privilege level of the instruction
2264 bundle responsible for generating the
2265 machine check.
2266
2267 @param PrivelegeLevelIsValid Bit58, The pl field of the
2268 TLB_check parameter is valid.
2269
2270 @param McCorrected Bit59, Machine check corrected: This bit
2271 is set to one to indicate that the machine
2272 check has been corrected.
2273
2274 @param TargetAddressIsValid Bit60, Target address is valid:
2275 This bit is set to one to
2276 indicate that a valid target
2277 address has been logged.
2278
2279 @param RequesterIdentifier Bit61 Requester identifier: This
2280 bit is set to one to indicate that
2281 a valid requester identifier has
2282 been logged.
2283
2284 @param ResponserIdentifier Bit62, Responder identifier: This
2285 bit is set to one to indicate that
2286 a valid responder identifier has
2287 been logged.
2288
2289 @param PreciseInsPointer Bit63 Precise instruction pointer.
2290 This bit is set to one to indicate
2291 that a valid precise instruction
2292 pointer has been logged.
2293 **/
2294 typedef struct {
2295 UINT64 FailedSlot:8;
2296 UINT64 FailedSlotIsValid:1;
2297 UINT64 Reserved1 :1;
2298 UINT64 TlbLevel:2;
2299 UINT64 Reserved2 :4;
2300 UINT64 FailedInDataTr:1;
2301 UINT64 FailedInInsTr:1;
2302 UINT64 FailedInDataTc:1;
2303 UINT64 FailedInInsTc:1;
2304 UINT64 FailedOperation:4;
2305 UINT64 Reserved3:30;
2306 UINT64 InstructionSet:1;
2307 UINT64 InstructionSetIsValid:1;
2308 UINT64 PrivelegeLevel:2;
2309 UINT64 PrivelegeLevelIsValid:1;
2310 UINT64 McCorrected:1;
2311 UINT64 TargetAddressIsValid:1;
2312 UINT64 RequesterIdentifier:1;
2313 UINT64 ResponserIdentifier:1;
2314 UINT64 PreciseInsPointer:1;
2315 } PAL_TLB_CHECK_INFO;
2316
2317 /**
2318
2319 PAL Procedure - PAL_MC_ERROR_INFO.
2320
2321 Return Processor Machine Check Information and Processor
2322 Static State for logging by SAL. It is required by IPF. The
2323 PAL procedure supports the Static Registers calling
2324 convention. It could be called at physical and virtual mode.
2325
2326 @param Index Index of PAL_MC_ERROR_INFO within the list of PAL
2327 procedures.
2328
2329 @param InfoIndex Unsigned 64-bit integer identifying the
2330 error information that is being requested.
2331 See PAL_MC_ERROR_INFO.InfoIndex.
2332
2333 @param LevelIndex 8-byte formatted value identifying the
2334 structure to return error information
2335 on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.
2336
2337 @param ErrorTypeIndex Unsigned 64-bit integer denoting the
2338 type of error information that is
2339 being requested for the structure
2340 identified in LevelIndex.
2341
2342
2343 @return R9 Error information returned. The format of this
2344 value is dependant on the input values passed.
2345
2346 @return R10 If this value is zero, all the error information
2347 specified by err_type_index has been returned. If
2348 this value is one, more structure-specific error
2349 information is available and the caller needs to
2350 make this procedure call again with level_index
2351 unchanged and err_type_index, incremented.
2352
2353
2354 @return Status 0 - Call completed without error
2355
2356 @return Status -2 - Invalid argument
2357
2358 @return Status -3 - Call completed with error.
2359
2360 @return Status -6 - Argument was valid, but no error
2361 information was available
2362
2363
2364 **/
2365 #define PAL_MC_ERROR_INFO 25
2366
2367 /**
2368
2369 PAL Procedure - PAL_MC_EXPECTED.
2370
2371 Set/Reset Expected Machine Check Indicator. It is required by
2372 IPF. The PAL procedure supports the Static Registers calling
2373 convention. It could be called at physical mode.
2374
2375 @param Index Index of PAL_MC_EXPECTED within the list of PAL
2376 procedures.
2377
2378 @param Expected Unsigned integer with a value of 0 or 1 to
2379 set or reset the hardware resource
2380 PALE_CHECK examines for expected machine
2381 checks.
2382
2383
2384 @return R9 Unsigned integer denoting whether a machine check
2385 was previously expected.
2386
2387
2388 @return Status 0 - Call completed without error
2389
2390 @return Status -2 - Invalid argument
2391
2392 @return Status -3 - Call completed with error.
2393
2394 **/
2395 #define PAL_MC_EXPECTED 23
2396
2397 /**
2398
2399 PAL Procedure - PAL_MC_REGISTER_MEM.
2400
2401 Register min-state save area with PAL for machine checks and
2402 inits. It is required by IPF. The PAL procedure supports the
2403 Static Registers calling convention. It could be called at
2404 physical mode.
2405
2406 @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL
2407 procedures.
2408
2409 @param Address Physical address of the buffer to be
2410 registered with PAL.
2411
2412
2413
2414 @return Status 0 - Call completed without error
2415
2416 @return Status -2 - Invalid argument
2417
2418 @return Status -3 - Call completed with error.
2419
2420 **/
2421 #define PAL_MC_REGISTER_MEM 27
2422
2423 /**
2424
2425 PAL Procedure - PAL_MC_RESUME.
2426
2427 Restore minimal architected state and return to interrupted
2428 process. It is required by IPF. The PAL procedure supports the
2429 Static Registers calling convention. It could be called at
2430 physical mode.
2431
2432 @param Index Index of PAL_MC_RESUME within the list of PAL
2433 procedures.
2434
2435 @param SetCmci Unsigned 64 bit integer denoting whether to
2436 set the CMC interrupt. A value of 0 indicates
2437 not to set the interrupt, a value of 1
2438 indicated to set the interrupt, and all other
2439 values are reserved.
2440
2441 @param SavePtr Physical address of min-state save area used
2442 to used to restore processor state.
2443
2444 @param NewContext Unsigned 64-bit integer denoting whether
2445 the caller is returning to a new context.
2446 A value of 0 indicates the caller is
2447 returning to the interrupted context, a
2448 value of 1 indicates that the caller is
2449 returning to a new context.
2450
2451
2452
2453 @return Status -2 - Invalid argument
2454
2455 @return Status -3 - Call completed with error.
2456
2457 **/
2458 #define PAL_MC_RESUME 26
2459
2460 /**
2461
2462 PAL Procedure - PAL_HALT.
2463
2464 Enter the low-power HALT state or an implementation-dependent
2465 low-power state. It is optinal. The PAL procedure supports the
2466 Static Registers calling convention. It could be called at
2467 physical mode.
2468
2469 @param Index Index of PAL_HALT within the list of PAL
2470 procedures.
2471
2472 @param HaltState Unsigned 64-bit integer denoting low power
2473 state requested.
2474
2475 @param IoDetailPtr 8-byte aligned physical address pointer to
2476 information on the type of I/O
2477 (load/store) requested.
2478
2479
2480 @return R9 Value returned if a load instruction is requested
2481 in the io_detail_ptr
2482
2483
2484 @return Status 0 - Call completed without error
2485
2486 @return Status -1 - Unimplemented procedure
2487
2488 @return Status -2 - Invalid argument
2489
2490 @return Status -3 - Call completed with error.
2491
2492 **/
2493 #define PAL_HALT 28
2494
2495
2496 /**
2497
2498 PAL Procedure - PAL_HALT_INFO.
2499
2500 Return the low power capabilities of the processor. It is
2501 required by IPF. The PAL procedure supports the
2502 Stacked Registers calling convention. It could be called at
2503 physical and virtual mode.
2504
2505 @param Index Index of PAL_HALT_INFO within the list of PAL
2506 procedures.
2507
2508 @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned
2509 on an 8-byte boundary.
2510
2511
2512
2513 @return Status 0 - Call completed without error
2514
2515 @return Status -2 - Invalid argument
2516
2517 @return Status -3 - Call completed with error.
2518
2519 **/
2520 #define PAL_HALT_INFO 257
2521
2522
2523 /**
2524
2525 PAL Procedure - PAL_HALT_LIGHT.
2526
2527 Enter the low power LIGHT HALT state. It is required by
2528 IPF. The PAL procedure supports the Static Registers calling
2529 convention. It could be called at physical and virtual mode.
2530
2531 @param Index Index of PAL_HALT_LIGHT within the list of PAL
2532 procedures.
2533
2534
2535 @return Status 0 - Call completed without error
2536
2537 @return Status -2 - Invalid argument
2538
2539 @return Status -3 - Call completed with error.
2540
2541 **/
2542 #define PAL_HALT_LIGHT 29
2543
2544 /**
2545
2546 PAL Procedure - PAL_CACHE_LINE_INIT.
2547
2548 Initialize tags and data of a cache line for processor
2549 testing. It is required by IPF. The PAL procedure supports the
2550 Static Registers calling convention. It could be called at
2551 physical and virtual mode.
2552
2553 @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL
2554 procedures.
2555
2556 @param Address Unsigned 64-bit integer value denoting the
2557 physical address from which the physical page
2558 number is to be generated. The address must be
2559 an implemented physical address, bit 63 must
2560 be zero.
2561
2562 @param DataValue 64-bit data value which is used to
2563 initialize the cache line.
2564
2565
2566 @return Status 0 - Call completed without error
2567
2568 @return Status -2 - Invalid argument
2569
2570 @return Status -3 - Call completed with error.
2571
2572 **/
2573 #define PAL_CACHE_LINE_INIT 31
2574
2575 /**
2576
2577 PAL Procedure - PAL_CACHE_READ.
2578
2579 Read tag and data of a cache line for diagnostic testing. It
2580 is optional. The PAL procedure supports the
2581 Satcked Registers calling convention. It could be called at
2582 physical mode.
2583
2584 @param Index Index of PAL_CACHE_READ within the list of PAL
2585 procedures.
2586
2587 @param LineId 8-byte formatted value describing where in the
2588 cache to read the data.
2589
2590 @param Address 64-bit 8-byte aligned physical address from
2591 which to read the data. The address must be an
2592 implemented physical address on the processor
2593 model with bit 63 set to zero.
2594
2595 @return R9 Right-justified value returned from the cache
2596 line.
2597
2598 @return R10 The number of bits returned in data.
2599
2600 @return R11 The status of the cache line.
2601
2602
2603
2604 @return Status 1 - The word at address was found in the
2605 cache, but the line was invalid.
2606
2607 @return Status 0 - Call completed without error
2608
2609 @return Status -2 - Invalid argument
2610
2611 @return Status -3 - Call completed with error.
2612
2613 @return Status -5 - The word at address was not found in the
2614 cache.
2615
2616 @return Status -7 - The operation requested is not supported
2617 for this cache_type and level.
2618
2619 **/
2620 #define PAL_CACHE_READ 259
2621
2622
2623 /**
2624
2625 Write tag and data of a cache for diagnostic testing. It is
2626 optional. The PAL procedure supports the Satcked Registers
2627 calling convention. It could be called at physical mode.
2628
2629 @param Index Index of PAL_CACHE_WRITE within the list of PAL
2630 procedures.
2631
2632 @param LineId 8-byte formatted value describing where in the
2633 cache to write the data.
2634
2635 @param Address 64-bit 8-byte aligned physical address at
2636 which the data should be written. The address
2637 must be an implemented physical address on the
2638 processor model with bit 63 set to 0.
2639
2640 @param Data Unsigned 64-bit integer value to write into
2641 the specified part of the cache.
2642
2643
2644 @return Status 0 - Call completed without error
2645
2646 @return Status -2 - Invalid argument
2647
2648 @return Status -3 - Call completed with error.
2649
2650
2651 @return Status -7 - The operation requested is not supported
2652 for this cache_type and level.
2653
2654 **/
2655 #define PAL_CACHE_WRITE 260
2656
2657 /**
2658
2659 PAL Procedure - PAL_TEST_INFO.
2660
2661 Returns alignment and size requirements needed for the memory
2662 buffer passed to the PAL_TEST_PROC procedure as well as
2663 information on self-test control words for the processor self
2664 tests. It is required by IPF. The PAL procedure supports the
2665 Static Registers calling convention. It could be called at
2666 physical mode.
2667
2668 @param Index Index of PAL_TEST_INFO within the list of PAL
2669 procedures.
2670
2671 @param TestPhase Unsigned integer that specifies which phase
2672 of the processor self-test information is
2673 being requested on. A value of 0 indicates
2674 the phase two of the processor self-test and
2675 a value of 1 indicates phase one of the
2676 processor self-test. All other values are
2677 reserved.
2678
2679 @return R9 Unsigned 64-bit integer denoting the number of
2680 bytes of main memory needed to perform the second
2681 phase of processor self-test.
2682
2683 @return R10 Unsigned 64-bit integer denoting the alignment
2684 required for the memory buffer.
2685
2686 @return R11 48-bit wide bit-field indicating if control of
2687 the processor self-tests is supported and which
2688 bits of the test_control field are defined for
2689 use.
2690
2691
2692 @return Status 0 - Call completed without error
2693
2694 @return Status -2 - Invalid argument
2695
2696 @return Status -3 - Call completed with error.
2697
2698
2699 **/
2700 #define PAL_TEST_INFO 37
2701
2702 /**
2703
2704 @param BufferSize Indicates the size in bytes of the memory
2705 buffer that is passed to this procedure.
2706 BufferSize must be greater than or equal in
2707 size to the bytes_needed return value from
2708 PAL_TEST_INFO, otherwise this procedure will
2709 return with an invalid argument return
2710 value.
2711
2712 @param TestPhase Defines which phase of the processor
2713 self-tests are requested to be run. A value
2714 of zero indicates to run phase two of the
2715 processor self-tests. Phase two of the
2716 processor self-tests are ones that require
2717 external memory to execute correctly. A
2718 value of one indicates to run phase one of
2719 the processor self-tests. Phase one of the
2720 processor self-tests are tests run during
2721 PALE_RESET and do not depend on external
2722 memory to run correctly. When the caller
2723 requests to have phase one of the processor
2724 self-test run via this procedure call, a
2725 memory buffer may be needed to save and
2726 restore state as required by the PAL calling
2727 conventions. The procedure PAL_TEST_INFO
2728 informs the caller about the requirements of
2729 the memory buffer.
2730
2731 **/
2732 typedef struct {
2733 UINT64 BufferSize:56;
2734 UINT64 TestPhase:8;
2735 } PAL_TEST_INFO_INFO;
2736
2737 /**
2738
2739 @param TestControl This is an ordered implementation-specific
2740 control word that allows the user control
2741 over the length and runtime of the
2742 processor self-tests. This control word is
2743 ordered from the longest running tests up
2744 to the shortest running tests with bit 0
2745 controlling the longest running test. PAL
2746 may not implement all 47-bits of the
2747 test_control word. PAL communicates if a
2748 bit provides control by placing a zero in
2749 that bit. If a bit provides no control,
2750 PAL will place a one in it. PAL will have
2751 two sets of test_control bits for the two
2752 phases of the processor self-test. PAL
2753 provides information about implemented
2754 test_control bits at the hand-off from PAL
2755 to SAL for the firmware recovery check.
2756 These test_control bits provide control
2757 for phase one of processor self-test. It
2758 also provides this information via the PAL
2759 procedure call PAL_TEST_INFO for both the
2760 phase one and phase two processor tests
2761 depending on which information the caller
2762 is requesting. PAL interprets these bits
2763 as input parameters on two occasions. The
2764 first time is when SAL passes control back
2765 to PAL after the firmware recovery check.
2766 The second time is when a call to
2767 PAL_TEST_PROC is made. When PAL interprets
2768 these bits it will only interpret
2769 implemented test_control bits and will
2770 ignore the values located in the
2771 unimplemented test_control bits. PAL
2772 interprets the implemented bits such that
2773 if a bit contains a zero, this indicates
2774 to run the test. If a bit contains a one,
2775 this indicates to PAL to skip the test. If
2776 the cs bit indicates that control is not
2777 available, the test_control bits will be
2778 ignored or generate an illegal argument in
2779 procedure calls if the caller sets these
2780 bits.
2781
2782 @param ControlSupport This bit defines if an implementation
2783 supports control of the PAL self-tests
2784 via the self-test control word. If
2785 this bit is 0, the implementation does
2786 not support control of the processor
2787 self-tests via the self-test control
2788 word. If this bit is 1, the
2789 implementation does support control of
2790 the processor self-tests via the
2791 self-test control word. If control is
2792 not supported, GR37 will be ignored at
2793 the hand-off between SAL and PAL after
2794 the firmware recovery check and the
2795 PAL procedures related to the
2796 processor self-tests may return
2797 illegal arguments if a user tries to
2798 use the self-test control features.
2799
2800 **/
2801 typedef struct {
2802 UINT64 TestControl:47;
2803 UINT64 ControlSupport:1;
2804 UINT64 Reserved:16;
2805 } PAL_SELF_TEST_CONTROL;
2806
2807 /**
2808
2809 @param Attributes Specifies the memory attributes that are
2810 allowed to be used with the memory buffer
2811 passed to this procedure. The attributes
2812 parameter is a vector where each bit
2813 represents one of the virtual memory
2814 attributes defined by the architecture.See
2815 MEMORY_AATRIBUTES. The caller is required
2816 to support the cacheable attribute for the
2817 memory buffer, otherwise an invalid
2818 argument will be returned.
2819
2820
2821 @param TestControl Is the self-test control word
2822 corresponding to the test_phase passed.
2823 This test_control directs the coverage and
2824 runtime of the processor self-tests
2825 specified by the test_phase input
2826 argument. Information on if this
2827 feature is implemented and the number of
2828 bits supported can be obtained by the
2829 PAL_TEST_INFO procedure call. If this
2830 feature is implemented by the processor,
2831 the caller can selectively skip parts of
2832 the processor self-test by setting
2833 test_control bits to a one. If a bit has a
2834 zero, this test will be run. The values in
2835 the unimplemented bits are ignored. If
2836 PAL_TEST_INFO indicated that the self-test
2837 control word is not implemented, this
2838 procedure will return with an invalid
2839 argument status if the caller sets any of
2840 the test_control bits. See
2841 PAL_SELF_TEST_CONTROL.
2842 **/
2843 typedef struct {
2844 UINT64 Attributes:8;
2845 UINT64 Reserved:8;
2846 UINT64 TestControl:48;
2847 } PAL_TEST_CONTROL;
2848
2849 /**
2850
2851 PAL Procedure - PAL_TEST_PROC.
2852
2853 Perform late processor self test. It is required by IPF. The
2854 PAL procedure supports the Static Registers calling
2855 convention. It could be called at physical mode.
2856
2857 @param Index Index of PAL_TEST_PROC within the list of PAL
2858 procedures.
2859
2860 @param TestAddress 64-bit physical address of main memory
2861 area to be used by processor self-test.
2862 The memory region passed must be
2863 cacheable, bit 63 must be zero.
2864
2865 @param TestInfo Input argument specifying the size of the
2866 memory buffer passed and the phase of the
2867 processor self-test that should be run. See
2868 PAL_TEST_INFO.
2869
2870 @param TestParam Input argument specifying the self-test
2871 control word and the allowable memory
2872 attributes that can be used with the memory
2873 buffer. See PAL_TEST_CONTROL.
2874
2875 @return R9 Formatted 8-byte value denoting the state of the
2876 processor after self-test
2877
2878
2879
2880 @return Status 1 - Call completed without error, but hardware
2881 failures occurred during self-test.
2882
2883 @return Status 0 - Call completed without error
2884
2885 @return Status -2 - Invalid argument
2886
2887 @return Status -3 - Call completed with error.
2888
2889
2890 **/
2891 #define PAL_TEST_PROC 258
2892
2893 /**
2894
2895 @param NumberOfInterruptControllers Number of interrupt
2896 controllers currently
2897 enabled on the system.
2898
2899 @param NumberOfProcessors Number of processors currently
2900 enabled on the system.
2901
2902 **/
2903 typedef struct {
2904 UINT32 NumberOfInterruptControllers;
2905 UINT32 NumberOfProcessors;
2906 } PAL_PLATFORM_INFO;
2907
2908 /**
2909
2910 PAL Procedure - PAL_COPY_INFO.
2911
2912 Return information needed to relocate PAL procedures and PAL
2913 PMI code to memory. It is required by IPF. The PAL procedure
2914 supports the Static Registers calling convention. It could be
2915 called at physical mode.
2916
2917 @param Index Index of PAL_COPY_INFO within the list of PAL
2918 procedures.
2919
2920 @param CopyType Unsigned integer denoting type of procedures
2921 for which copy information is requested.
2922
2923 @param PlatformInfo 8-byte formatted value describing the
2924 number of processors and the number of
2925 interrupt controllers currently enabled
2926 on the system. See PAL_PLATFORM_INFO.
2927
2928
2929 @param McaProcStateInfo Unsigned integer denoting the number
2930 of bytes that SAL needs for the
2931 min-state save area for each
2932 processor.
2933
2934
2935
2936 @return R9 Unsigned integer denoting the number of bytes of
2937 PAL information that must be copied to main
2938 memory.
2939
2940 @return R10 Unsigned integer denoting the starting alignment
2941 of the data to be copied.
2942
2943 @return Status 0 - Call completed without error
2944
2945 @return Status -2 - Invalid argument
2946
2947 @return Status -3 - Call completed with error.
2948
2949
2950 **/
2951 #define PAL_COPY_INFO 30
2952
2953 /**
2954
2955 PAL Procedure - PAL_COPY_PAL.
2956
2957 Relocate PAL procedures and PAL PMI code to memory. It is
2958 required by IPF. The PAL procedure supports the Stacked
2959 Registers calling convention. It could be called at physical
2960 mode.
2961
2962 @param Index Index of PAL_COPY_PAL within the list of PAL
2963 procedures.
2964
2965 @param TargetAddress Physical address of a memory buffer to
2966 copy relocatable PAL procedures and PAL
2967 PMI code.
2968
2969 @param AllocSize Unsigned integer denoting the size of the
2970 buffer passed by SAL for the copy operation.
2971
2972
2973 @param CopyOption Unsigned integer indicating whether
2974 relocatable PAL code and PAL PMI code
2975 should be copied from firmware address
2976 space to main memory.
2977
2978
2979 @return R9 Unsigned integer denoting the offset of PAL_PROC
2980 in the relocatable segment copied.
2981
2982 @return Status 0 - Call completed without error
2983
2984 @return Status -2 - Invalid argument
2985
2986 @return Status -3 - Call completed with error.
2987
2988
2989 **/
2990 #define PAL_COPY_PAL 256
2991
2992 /**
2993
2994 PAL Procedure - PAL_ENTER_IA_32_ENV.
2995
2996 Enter IA-32 System environment. It is optional. The PAL
2997 procedure supports the Static Registers calling convention.
2998 It could be called at physical mode.
2999
3000 Note: Since this is a special call, it does not follow the PAL
3001 static register calling convention. GR28 contains the index of
3002 PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other
3003 input arguments including GR29-GR31 are setup by SAL to values
3004 as required by the IA-32 operating system defined in Table
3005 11-67. The registers that are designated as preserved, scratch,
3006 input arguments and procedure return values by the static
3007 procedure calling convention are not followed by this call. For
3008 instance, GR5 and GR6 need not be preserved since these are
3009 regarded as scratch by the IA-32 operating system. Note: In an
3010 MP system, this call must be COMPLETED on the first CPU to enter
3011 the IA-32 System Environment (may or may not be the BSP) prior
3012 to being called on the remaining processors in the MP system.
3013
3014 @param Index GR28 contains the index of the
3015 PAL_ENTER_IA_32_ENV call within the list of PAL
3016 procedures.
3017
3018
3019 @return Status The status is returned in GR4.
3020 -1 - Un-implemented procedure 0 JMPE detected
3021 at privilege level
3022
3023 0 - 1 SAL allocated buffer for IA-32 System
3024 Environment operation is too small
3025
3026 2 - IA-32 Firmware Checksum Error
3027
3028 3 - SAL allocated buffer for IA-32 System
3029 Environment operation is not properly aligned
3030
3031 4 - Error in SAL MP Info Table
3032
3033 5 - Error in SAL Memory Descriptor Table
3034
3035 6 - Error in SAL System Table
3036
3037 7 - Inconsistent IA-32 state
3038
3039 8 - IA-32 Firmware Internal Error
3040
3041 9 - IA-32 Soft Reset (Note: remaining register
3042 state is undefined for this termination
3043 reason)
3044
3045 10 - Machine Check Error
3046
3047 11 - Error in SAL I/O Intercept Table
3048
3049 12 - Processor exit due to other processor in
3050 MP system terminating the IA32 system
3051 environment. (Note: remaining register state
3052 is undefined for this termination reason.)
3053
3054 13 - Itanium architecture-based state
3055 corruption by either SAL PMI handler or I/O
3056 Intercept callback function.
3057
3058
3059 **/
3060 #define PAL_ENTER_IA_32_ENV 33
3061
3062 /**
3063
3064 PAL Procedure - PAL_PMI_ENTRYPOINT.
3065
3066 Register PMI memory entrypoints with processor. It is required
3067 by IPF. The PAL procedure supports the Stacked Registers
3068 calling convention. It could be called at physical mode.
3069
3070 @param Index Index of PAL_PMI_ENTRYPOINT within the list of
3071 PAL procedures.
3072
3073 @param SalPmiEntry 256-byte aligned physical address of SAL
3074 PMI entrypoint in memory.
3075
3076
3077 @return Status 0 - Call completed without error
3078
3079 @return Status -2 - Invalid argument
3080
3081 @return Status -3 - Call completed with error.
3082
3083
3084 **/
3085 #define PAL_PMI_ENTRYPOINT 32
3086
3087
3088 /**
3089
3090 The ASCII brand identification string will be copied to the
3091 address specified in the address input argument. The processor
3092 brand identification string is defined to be a maximum of 128
3093 characters long; 127 bytes will contain characters and the 128th
3094 byte is defined to be NULL (0). A processor may return less than
3095 the 127 ASCII characters as long as the string is null
3096 terminated. The string length will be placed in the brand_info
3097 return argument.
3098
3099 **/
3100 #define PAL_BRAND_INFO_ID_REQUEST 0
3101
3102 /**
3103
3104 PAL Procedure - PAL_BRAND_INFO.
3105
3106 Provides processor branding information. It is optional by
3107 IPF. The PAL procedure supports the Stacked Registers calling
3108 convention. It could be called at physical and Virtual mode.
3109
3110
3111 @param Index Index of PAL_BRAND_INFO within the list of PAL
3112 procedures.
3113
3114 @param InfoRequest Unsigned 64-bit integer specifying the
3115 information that is being requested. (See
3116 PAL_BRAND_INFO_ID_REQUEST)
3117
3118 @param Address Unsigned 64-bit integer specifying the
3119 address of the 128-byte block to which the
3120 processor brand string shall be written.
3121
3122
3123 @reture R9 Brand information returned. The format of this
3124 value is dependent on the input values passed.
3125
3126
3127 @return Status 0 - Call completed without error
3128
3129 @return Status -1 - Unimplemented procedure
3130
3131 @return Status -2 - Invalid argument
3132
3133 @return Status -3 - Call completed with error.
3134
3135 @return Status -6 - Input argument is not implemented.
3136
3137 **/
3138 #define PAL_BRAND_INFO 274
3139
3140 /**
3141
3142 PAL Procedure - PAL_GET_HW_POLICY.
3143
3144 Returns the current hardware resource sharing policy of the
3145 processor. It is optional by IPF. The PAL procedure supports
3146 the Static Registers calling convention. It could be called at
3147 physical and Virtual mode.
3148
3149
3150 @param Index Index of PAL_GET_HW_POLICY within the list of PAL
3151 procedures.
3152
3153 @param ProcessorNumber Unsigned 64-bit integer that specifies
3154 for which logical processor
3155 information is being requested. This
3156 input argument must be zero for the
3157 first call to this procedure and can
3158 be a maximum value of one less than
3159 the number of logical processors
3160 impacted by the hardware resource
3161 sharing policy, which is returned by
3162 the R10 return value.
3163
3164
3165 @reture R9 Unsigned 64-bit integer representing the current
3166 hardware resource sharing policy.
3167
3168 @return R10 Unsigned 64-bit integer that returns the number
3169 of logical processors impacted by the policy
3170 input argument.
3171
3172 @return R11 Unsigned 64-bit integer containing the logical
3173 address of one of the logical processors
3174 impacted by policy modification.
3175
3176
3177 @return Status 0 - Call completed without error
3178
3179 @return Status -1 - Unimplemented procedure
3180
3181 @return Status -2 - Invalid argument
3182
3183 @return Status -3 - Call completed with error.
3184
3185 @return Status -9 - Call requires PAL memory buffer.
3186
3187 **/
3188 #define PAL_GET_HW_POLICY 48
3189
3190
3191 //
3192 // Value of PAL_SET_HW_POLICY.Policy
3193 //
3194 #define PAL_SET_HW_POLICY_PERFORMANCE 0
3195 #define PAL_SET_HW_POLICY_FAIRNESS 1
3196 #define PAL_SET_HW_POLICY_HIGH_PRIORITY 2
3197 #define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3
3198
3199 /**
3200
3201 PAL Procedure - PAL_SET_HW_POLICY.
3202
3203 Sets the current hardware resource sharing policy of the
3204 processor. It is optional by IPF. The PAL procedure supports
3205 the Static Registers calling convention. It could be called at
3206 physical and Virtual mode.
3207
3208
3209 @param Index Index of PAL_SET_HW_POLICY within the list of PAL
3210 procedures.
3211
3212 @param Policy Unsigned 64-bit integer specifying the hardware
3213 resource sharing policy the caller is setting.
3214 See Value of PAL_SET_HW_POLICY.Policy above.
3215
3216
3217 @return Status 1 - Call completed successfully but could not
3218 change the hardware policy since a
3219 competing logical processor is set in
3220 exclusive high priority.
3221
3222 @return Status 0 - Call completed without error
3223
3224 @return Status -1 - Unimplemented procedure
3225
3226 @return Status -2 - Invalid argument
3227
3228 @return Status -3 - Call completed with error.
3229
3230 @return Status -9 - Call requires PAL memory buffer.
3231
3232 **/
3233 #define PAL_SET_HW_POLICY 49
3234
3235
3236 /**
3237
3238 @param Mode Bit2:0, Indicates the mode of operation for this
3239 procedure: 0 - Query mode 1 ¨C Error inject mode
3240 (err_inj should also be specified) 2 - Cancel
3241 outstanding trigger. All other fields in
3242 PAL_MC_ERROR_TYPE_INFO,
3243 PAL_MC_ERROR_STRUCTURE_INFO and
3244 PAL_MC_ERROR_DATA_BUFFER are ignored. All other
3245 values are reserved.
3246
3247 @param ErrorInjection Bit5:3, indicates the mode of error
3248 injection: 0 - Error inject only (no
3249 error consumption) 1 - Error inject
3250 and consume All other values are
3251 reserved.
3252
3253
3254 @param ErrorSeverity Bit7:6, indicates the severity desired
3255 for error injection/query. Definitions
3256 of the different error severity types
3257 0 - Corrected error 1 - Recoverable
3258 error 2 - Fatal error 3 - Reserved
3259
3260
3261 @param ErrorStructure Bit12:8, Indicates the structure
3262 identification for error
3263 injection/query: 0 - Any structure
3264 (cannot be used during query mode).
3265 When selected, the structure type used
3266 for error injection is determined by
3267 PAL. 1 - Cache 2 - TLB 3 - Register
3268 file 4 - Bus/System interconnect 5-15
3269 - Reserved 16-31 - Processor
3270 specific error injection
3271 capabilities.ErrorDataBuffer is used
3272 to specify error types. Please refer
3273 to the processor specific
3274 documentation for additional details.
3275
3276 @param StructureHierarchy Bit15:13, Indicates the structure
3277 hierarchy for error
3278 injection/query: 0 - Any level of
3279 hierarchy (cannot be used during
3280 query mode). When selected, the
3281 structure hierarchy used for error
3282 injection is determined by PAL. 1
3283 - Error structure hierarchy
3284 level-1 2 - Error structure
3285 hierarchy level-2 3 - Error
3286 structure hierarchy level-3 4 -
3287 Error structure hierarchy level-4
3288 All other values are reserved.
3289 Reserved 63:16 Reserved
3290
3291 **/
3292 typedef struct {
3293 UINT64 Mode:3;
3294 UINT64 ErrorInjection:3;
3295 UINT64 ErrorSeverity:2;
3296 UINT64 ErrorStructure:5;
3297 UINT64 StructureHierarchy:3;
3298 UINT64 Reserved:48;
3299 } PAL_MC_ERROR_TYPE_INFO;
3300
3301 /**
3302
3303 @param StructInfoIsValid Bit0 When 1, indicates that the
3304 structure information fields
3305 (c_t,cl_p,cl_id) are valid and
3306 should be used for error injection.
3307 When 0, the structure information
3308 fields are ignored, and the values
3309 of these fields used for error
3310 injection are
3311 implementation-specific.
3312
3313 @param CacheType Bit2:1 Indicates which cache should be used
3314 for error injection: 0 - Reserved 1 -
3315 Instruction cache 2 - Data or unified cache
3316 3 - Reserved
3317
3318
3319 @param PortionOfCacheLine Bit5:3 Indicates the portion of the
3320 cache line where the error should
3321 be injected: 0 - Reserved 1 - Tag
3322 2 - Data 3 - mesi All other
3323 values are reserved.
3324
3325 @param Mechanism Bit8:6 Indicates which mechanism is used to
3326 identify the cache line to be used for error
3327 injection: 0 - Reserved 1 - Virtual address
3328 provided in the inj_addr field of the buffer
3329 pointed to by err_data_buffer should be used
3330 to identify the cache line for error
3331 injection. 2 - Physical address provided in
3332 the inj_addr field of the buffer pointed to
3333 by err_data_buffershould be used to identify
3334 the cache line for error injection. 3 - way
3335 and index fields provided in err_data_buffer
3336 should be used to identify the cache line
3337 for error injection. All other values are
3338 reserved.
3339
3340 @param DataPoisonOfCacheLine Bit9 When 1, indicates that a
3341 multiple bit, non-correctable
3342 error should be injected in the
3343 cache line specified by cl_id.
3344 If this injected error is not
3345 consumed, it may eventually
3346 cause a data-poisoning event
3347 resulting in a corrected error
3348 signal, when the associated
3349 cache line is cast out (implicit
3350 or explicit write-back of the
3351 cache line). The error severity
3352 specified by err_sev in
3353 err_type_info must be set to 0
3354 (corrected error) when this bit
3355 is set.
3356
3357
3358 @param TrigerInfoIsValid Bit32 When 1, indicates that the
3359 trigger information fields (trigger,
3360 trigger_pl) are valid and should be
3361 used for error injection. When 0,
3362 the trigger information fields are
3363 ignored and error injection is
3364 performed immediately.
3365
3366 @param Triger Bit36:33 Indicates the operation type to be
3367 used as the error trigger condition. The
3368 address corresponding to the trigger is
3369 specified in the trigger_addr field of the
3370 buffer pointed to by err_data_buffer: 0 -
3371 Instruction memory access. The trigger match
3372 conditions for this operation type are similar
3373 to the IBR address breakpoint match conditions
3374 1 - Data memory access. The trigger match
3375 conditions for this operation type are similar
3376 to the DBR address breakpoint match conditions
3377 All other values are reserved.
3378
3379 @param PrivilegeOfTriger Bit39:37 Indicates the privilege
3380 level of the context during which
3381 the error should be injected: 0 -
3382 privilege level 0 1 - privilege
3383 level 1 2 - privilege level 2 3 -
3384 privilege level 3 All other values
3385 are reserved. If the implementation
3386 does not support privilege level
3387 qualifier for triggers (i.e. if
3388 trigger_pl is 0 in the capabilities
3389 vector), this field is ignored and
3390 triggers can be taken at any
3391 privilege level.
3392
3393 **/
3394 typedef struct {
3395 UINT64 StructInfoIsValid:1;
3396 UINT64 CacheType:2;
3397 UINT64 PortionOfCacheLine:3;
3398 UINT64 Mechanism:3;
3399 UINT64 DataPoisonOfCacheLine:1;
3400 UINT64 Reserved1:22;
3401 UINT64 TrigerInfoIsValid:1;
3402 UINT64 Triger:4;
3403 UINT64 PrivilegeOfTriger:3;
3404 UINT64 Reserved2:24;
3405 } PAL_MC_ERROR_STRUCT_INFO;
3406
3407 /**
3408
3409 Buffer Pointed to by err_data_buffer ¨C TLB
3410
3411 **/
3412 typedef struct {
3413 UINT64 TrigerAddress;
3414 UINT64 VirtualPageNumber:52;
3415 UINT64 Reserved1:8;
3416 UINT64 RegionId:24;
3417 UINT64 Reserved2:40;
3418 } PAL_MC_ERROR_DATA_BUFFER_TLB;
3419
3420 /**
3421
3422 PAL Procedure - PAL_MC_ERROR_INJECT.
3423
3424 Injects the requested processor error or returns information
3425 on the supported injection capabilities for this particular
3426 processor implementation. It is optional by IPF. The PAL
3427 procedure supports the Stacked Registers calling convention.
3428 It could be called at physical and Virtual mode.
3429
3430
3431 @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL
3432 procedures.
3433
3434 @param ErrorTypeInfo Unsigned 64-bit integer specifying the
3435 first level error information which
3436 identifies the error structure and
3437 corresponding structure hierarchy, and
3438 the error severity.
3439
3440 @param ErrorStructInfo Unsigned 64-bit integer identifying
3441 the optional structure specific
3442 information that provides the second
3443 level details for the requested error.
3444
3445 @param ErrorDataBuffer 64-bit physical address of a buffer
3446 providing additional parameters for
3447 the requested error. The address of
3448 this buffer must be 8-byte aligned.
3449
3450 @return R9 64-bit vector specifying the supported error
3451 injection capabilities for the input argument
3452 combination of struct_hier, err_struct and
3453 err_sev fields in ErrorTypeInfo.
3454
3455 @return R10 64-bit vector specifying the architectural
3456 resources that are used by the procedure.
3457
3458
3459 @return Status 0 - Call completed without error
3460
3461 @return Status -1 - Unimplemented procedure
3462
3463 @return Status -2 - Invalid argument
3464
3465 @return Status -3 - Call completed with error.
3466
3467 @return Status -4 - Call completed with error; the requested
3468 error could not be injected due to failure in
3469 locating the target location in the specified
3470 structure.
3471
3472 @return Status -5 - Argument was valid, but requested error
3473 injection capability is not supported.
3474
3475 @return Status -9 - Call requires PAL memory buffer.
3476
3477 **/
3478 #define PAL_MC_ERROR_INJECT 276
3479
3480
3481 //
3482 // Types of PAL_GET_PSTATE.Type
3483 //
3484 #define PAL_GET_PSTATE_RECENT 0
3485 #define PAL_GET_PSTATE_AVERAGE_NEW_START 1
3486 #define PAL_GET_PSTATE_AVERAGE 2
3487 #define PAL_GET_PSTATE_NOW 3
3488
3489 /**
3490
3491 PAL Procedure - PAL_GET_PSTATE.
3492
3493 Returns the performance index of the processor. It is optional
3494 by IPF. The PAL procedure supports the Stacked Registers
3495 calling convention. It could be called at physical and Virtual
3496 mode.
3497
3498
3499 @param Index Index of PAL_GET_PSTATE within the list of PAL
3500 procedures.
3501
3502 @param Type Type of performance_index value to be returned
3503 by this procedure.See PAL_GET_PSTATE.Type above.
3504
3505
3506 @return R9 Unsigned integer denoting the processor
3507 performance for the time duration since the last
3508 PAL_GET_PSTATE procedure call was made. The
3509 value returned is between 0 and 100, and is
3510 relative to the performance index of the highest
3511 available P-state.
3512
3513 @return Status 1 - Call completed without error, but accuracy
3514 of performance index has been impacted by a
3515 thermal throttling event, or a
3516 hardware-initiated event.
3517
3518 @return Status 0 - Call completed without error
3519
3520 @return Status -1 - Unimplemented procedure
3521
3522 @return Status -2 - Invalid argument
3523
3524 @return Status -3 - Call completed with error.
3525
3526 @return Status -9 - Call requires PAL memory buffer.
3527
3528 **/
3529 #define PAL_GET_PSTATE 262
3530
3531 /**
3532
3533 Layout of PAL_PSTATE_INFO.PStateBuffer
3534
3535 **/
3536 typedef struct {
3537 UINT32 PerformanceIndex:7;
3538 UINT32 Reserved1:5;
3539 UINT32 TypicalPowerDissipation:20;
3540 UINT32 TransitionLatency1;
3541 UINT32 TransitionLatency2;
3542 UINT32 Reserved2;
3543 } PAL_PSTATE_INFO_BUFFER;
3544
3545
3546 /**
3547
3548 PAL Procedure - PAL_PSTATE_INFO.
3549
3550 Returns information about the P-states supported by the
3551 processor. It is optional by IPF. The PAL procedure supports