copied the PalCallLib.h from the new MdePkg
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1 /** @file
2 PAL Call Services
3
4 Copyright (c) 2006 -2007, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 Module Name: PalCallLib.h
15
16 **/
17
18 #ifndef __PAL_CALL_LIB_H__
19 #define __PAL_CALL_LIB_H__
20
21 //
22 // CacheType of PAL_CACHE_FLUSH.
23 //
24 #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
25 #define PAL_CACHE_FLUSH_DATA_ALL 2
26 #define PAL_CACHE_FLUSH_ALL 3
27 #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
28
29
30 //
31 // Bitmask of Opearation of PAL_CACHE_FLUSH.
32 //
33 #define PAL_CACHE_FLUSH_INVIDED_LINES BIT0
34 #define PAL_CACHE_FLUSH_PROBE_INTERRUPT BIT1
35
36 /**
37
38 PAL Procedure - PAL_CACHE_FLUSH.
39
40 Flush the instruction or data caches. It is required by IPF.
41 The PAL procedure supports the Static Registers calling
42 convention. It could be called at virtual mode and physical
43 mode.
44
45 @param Index Index of PAL_CACHE_FLUSH within the
46 list of PAL procedures.
47
48 @param CacheType Unsigned 64-bit integer indicating
49 which cache to flush.
50
51 @param Operation Formatted bit vector indicating the
52 operation of this call.
53
54 @param ProgressIndicator Unsigned 64-bit integer specifying
55 the starting position of the flush
56 operation.
57
58 @return R9 Unsigned 64-bit integer specifying the vector
59 number of the pending interrupt.
60
61 @return R10 Unsigned 64-bit integer specifying the
62 starting position of the flush operation.
63
64 @return R11 Unsigned 64-bit integer specifying the vector
65 number of the pending interrupt.
66
67 @return Status 2 - Call completed without error, but a PMI
68 was taken during the execution of this
69 procedure.
70
71 @return Status 1 - Call has not completed flushing due to
72 a pending interrupt.
73
74 @return Status 0 - Call completed without error
75
76 @return Status -2 - Invalid argument
77
78 @return Status -3 - Call completed with error
79
80 **/
81 #define PAL_CACHE_FLUSH 1
82
83
84 //
85 // Attributes of PAL_CACHE_CONFIG_INFO1
86 //
87 #define PAL_CACHE_ATTR_WT 0
88 #define PAL_CACHE_ATTR_WB 1
89
90 //
91 // PAL_CACHE_CONFIG_INFO1.StoreHint
92 //
93 #define PAL_CACHE_STORE_TEMPORAL 0
94 #define PAL_CACHE_STORE_NONE_TEMPORAL 3
95
96 //
97 // PAL_CACHE_CONFIG_INFO1.StoreHint
98 //
99 #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
100 #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
101
102 //
103 // PAL_CACHE_CONFIG_INFO1.StoreHint
104 //
105 #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
106 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
107 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
108
109 //
110 // Detail the characteristics of a given processor controlled
111 // cache in the cache hierarchy.
112 //
113 typedef struct {
114 UINT64 IsUnified : 1;
115 UINT64 Attributes : 2;
116 UINT64 Associativity:8;
117 UINT64 LineSize:8;
118 UINT64 Stride:8;
119 UINT64 StoreLatency:8;
120 UINT64 StoreHint:8;
121 UINT64 LoadHint:8;
122 } PAL_CACHE_INFO_RETURN1;
123
124 //
125 // Detail the characteristics of a given processor controlled
126 // cache in the cache hierarchy.
127 //
128 typedef struct {
129 UINT64 CacheSize:32;
130 UINT64 AliasBoundary:8;
131 UINT64 TagLsBits:8;
132 UINT64 TagMsBits:8;
133 } PAL_CACHE_INFO_RETURN2;
134
135 /**
136
137 PAL Procedure - PAL_CACHE_INFO.
138
139 Return detailed instruction or data cache information. It is
140 required by IPF. The PAL procedure supports the Static
141 Registers calling convention. It could be called at virtual
142 mode and physical mode.
143
144 @param Index Index of PAL_CACHE_INFO within the list of
145 PAL procedures.
146
147 @param CacheLevel Unsigned 64-bit integer specifying the
148 level in the cache hierarchy for which
149 information is requested. This value must
150 be between 0 and one less than the value
151 returned in the cache_levels return value
152 from PAL_CACHE_SUMMARY.
153
154 @param CacheType Unsigned 64-bit integer with a value of 1
155 for instruction cache and 2 for data or
156 unified cache. All other values are
157 reserved.
158
159 @param Reserved Should be 0.
160
161
162 @return R9 Detail the characteristics of a given
163 processor controlled cache in the cache
164 hierarchy. See PAL_CACHE_INFO_RETURN1.
165
166 @return R10 Detail the characteristics of a given
167 processor controlled cache in the cache
168 hierarchy. See PAL_CACHE_INFO_RETURN2.
169
170 @return R11 Reserved with 0.
171
172
173 @return Status 0 - Call completed without error
174
175 @return Status -2 - Invalid argument
176
177 @return Status -3 - Call completed with error
178
179 **/
180 #define PAL_CACHE_INFO 2
181
182
183
184 //
185 // Level of PAL_CACHE_INIT.
186 //
187 #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
188
189 //
190 // Restrict of PAL_CACHE_INIT.
191 //
192 #define PAL_CACHE_INIT_NO_RESTRICT 0
193 #define PAL_CACHE_INIT_RESTRICTED 1
194
195 /**
196
197 PAL Procedure - PAL_CACHE_INIT.
198
199 Initialize the instruction or data caches. It is required by
200 IPF. The PAL procedure supports the Static Registers calling
201 convention. It could be called at physical mode.
202
203 @param Index Index of PAL_CACHE_INIT within the list of PAL
204 procedures.
205
206 @param Level Unsigned 64-bit integer containing the level of
207 cache to initialize. If the cache level can be
208 initialized independently, only that level will
209 be initialized. Otherwise
210 implementation-dependent side-effects will
211 occur.
212
213 @param CacheType Unsigned 64-bit integer with a value of 1 to
214 initialize the instruction cache, 2 to
215 initialize the data cache, or 3 to
216 initialize both. All other values are
217 reserved.
218
219 @param Restrict Unsigned 64-bit integer with a value of 0 or
220 1. All other values are reserved. If
221 restrict is 1 and initializing the specified
222 level and cache_type of the cache would
223 cause side-effects, PAL_CACHE_INIT will
224 return -4 instead of initializing the cache.
225
226
227 @return Status 0 - Call completed without error
228
229 @return Status -2 - Invalid argument
230
231 @return Status -3 - Call completed with error.
232
233 @return Status -4 - Call could not initialize the specified
234 level and cache_type of the cache without
235 side-effects and restrict was 1.
236
237 **/
238 #define PAL_CACHE_INIT 3
239
240
241 //
242 // PAL_CACHE_PROTECTION.Method.
243 //
244 #define PAL_CACHE_PROTECTION_NONE_PROTECT 0
245 #define PAL_CACHE_PROTECTION_ODD_PROTECT 1
246 #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
247 #define PAL_CACHE_PROTECTION_ECC_PROTECT 3
248
249
250
251 //
252 // PAL_CACHE_PROTECTION.TagOrData.
253 //
254 #define PAL_CACHE_PROTECTION_PROTECT_DATA 0
255 #define PAL_CACHE_PROTECTION_PROTECT_TAG 1
256 #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
257 #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
258
259 //
260 // 32-bit protection information structures.
261 //
262 typedef struct {
263 UINT32 DataBits:8;
264 UINT32 TagProtLsb:6;
265 UINT32 TagProtMsb:6;
266 UINT32 ProtBits:6;
267 UINT32 Method:4;
268 UINT32 TagOrData:2;
269 } PAL_CACHE_PROTECTION;
270
271 /**
272
273 PAL Procedure - PAL_CACHE_PROT_INFO.
274
275 Return instruction or data cache protection information. It is
276 required by IPF. The PAL procedure supports the Static
277 Registers calling convention. It could be called at physical
278 mode and Virtual mode.
279
280 @param Index Index of PAL_CACHE_PROT_INFO within the list of
281 PAL procedures.
282
283 @param CacheLevel Unsigned 64-bit integer specifying the level
284 in the cache hierarchy for which information
285 is requested. This value must be between 0
286 and one less than the value returned in the
287 cache_levels return value from
288 PAL_CACHE_SUMMARY.
289
290 @param CacheType Unsigned 64-bit integer with a value of 1
291 for instruction cache and 2 for data or
292 unified cache. All other values are
293 reserved.
294
295 @return R9 Detail the characteristics of a given
296 processor controlled cache in the cache
297 hierarchy. See PAL_CACHE_PROTECTION[0..1].
298
299 @return R10 Detail the characteristics of a given
300 processor controlled cache in the cache
301 hierarchy. See PAL_CACHE_PROTECTION[2..3].
302
303 @return R11 Detail the characteristics of a given
304 processor controlled cache in the cache
305 hierarchy. See PAL_CACHE_PROTECTION[4..5].
306
307
308 @return Status 0 - Call completed without error
309
310 @return Status -2 - Invalid argument
311
312 @return Status -3 - Call completed with error.
313
314 **/
315 #define PAL_CACHE_PROT_INFO 38
316
317 /**
318
319 @param ThreadId The thread identifier of the logical
320 processor for which information is being
321 returned. This value will be unique on a per
322 core basis.
323
324 @param CoreId The core identifier of the logical processor
325 for which information is being returned.
326 This value will be unique on a per physical
327 processor package basis.
328
329 **/
330 typedef struct {
331 UINT64 ThreadId : 16;
332 UINT64 Reserved1: 16;
333 UINT64 CoreId: 16;
334 UINT64 Reserved2: 16;
335 } PAL_PCOC_N_CACHE_INFO1;
336
337 /**
338
339 @param LogicalAddress Logical address: geographical address
340 of the logical processor for which
341 information is being returned. This is
342 the same value that is returned by the
343 PAL_FIXED_ADDR procedure when it is
344 called on the logical processor.
345
346 **/
347 typedef struct {
348 UINT64 LogicalAddress : 16;
349 UINT64 Reserved1: 16;
350 UINT64 Reserved2: 32;
351 } PAL_PCOC_N_CACHE_INFO2;
352
353 /**
354
355 PAL Procedure - PAL_CACHE_SHARED_INFO.
356
357 Returns information on which logical processors share caches.
358 It is optional. The PAL procedure supports the Static
359 Registers calling convention. It could be called at physical
360 mode and Virtual mode.
361
362 @param Index Index of PAL_CACHE_SHARED_INFO within the list
363 of PAL procedures.
364
365 @param CacheLevel Unsigned 64-bit integer specifying the
366 level in the cache hierarchy for which
367 information is requested. This value must
368 be between 0 and one less than the value
369 returned in the cache_levels return value
370 from PAL_CACHE_SUMMARY.
371
372 @param CacheType Unsigned 64-bit integer with a value of 1
373 for instruction cache and 2 for data or
374 unified cache. All other values are
375 reserved.
376
377 @param ProcNumber Unsigned 64-bit integer that specifies for
378 which logical processor information is
379 being requested. This input argument must
380 be zero for the first call to this
381 procedure and can be a maximum value of
382 one less than the number of logical
383 processors sharing this cache, which is
384 returned by the num_shared return value.
385
386 @return R9 Unsigned integer that returns the number of
387 logical processors that share the processor
388 cache level and type, for which information was
389 requested.
390
391 @return R10 The format of PAL_PCOC_N_CACHE_INFO1.
392
393 @return R11 The format of PAL_PCOC_N_CACHE_INFO2.
394
395 @return Status 0 - Call completed without error
396
397 @return Status -1 - Unimplemented procedure
398
399 @return Status -2 - Invalid argument
400
401 @return Status -3 - Call completed with error.
402
403 **/
404 #define PAL_CACHE_SHARED_INFO 43
405
406
407 /**
408
409 PAL Procedure - PAL_CACHE_SUMMARY.
410
411 Return a summary of the cache hierarchy. It is required by
412 IPF. The PAL procedure supports the Static Registers calling
413 convention. It could be called at physical mode and Virtual
414 mode.
415
416 @param Index Index of PAL_CACHE_SUMMARY within the list of
417 PAL procedures.
418
419
420 @return R9 CacheLevels Unsigned 64-bit integer denoting the
421 number of levels of cache
422 implemented by the processor.
423 Strictly, this is the number of
424 levels for which the cache
425 controller is integrated into the
426 processor (the cache SRAMs may be
427 external to the processor).
428
429 @return R10 UniqueCaches Unsigned 64-bit integer denoting the
430 number of unique caches implemented
431 by the processor. This has a maximum
432 of 2*cache_levels, but may be less
433 if any of the levels in the cache
434 hierarchy are unified caches or do
435 not have both instruction and data
436 caches.
437
438 @return Status 0 - Call completed without error
439
440 @return Status -2 - Invalid argument
441
442 @return Status -3 - Call completed with error.
443
444 **/
445 #define PAL_CACHE_SUMMARY 4
446
447
448 //
449 // Virtual Memory Attributes implemented by processor.
450 //
451 #define PAL_MEMORY_ATTR_WB 0
452 #define PAL_MEMORY_ATTR_WC 6
453 #define PAL_MEMORY_ATTR_UC 4
454 #define PAL_MEMORY_ATTR_UCE 5
455 #define PAL_MEMORY_ATTR_NATPAGE 7
456
457 /**
458
459 PAL Procedure - PAL_MEM_ATTRIB.
460
461 Return a list of supported memory attributes.. It is required
462 by IPF. The PAL procedure supports the Static Registers calling
463 convention. It could be called at physical mode and Virtual
464 mode.
465
466 @param Index Index of PAL_MEM_ATTRIB within the list of PAL
467 procedures.
468
469
470 @return R9 Attributes 8-bit vector of memory attributes
471 implemented by processor. See Virtual
472 Memory Attributes above.
473
474 @return Status 0 - Call completed without error
475
476 @return Status -2 - Invalid argument
477
478 @return Status -3 - Call completed with error.
479
480 **/
481
482 #define PAL_MEM_ATTRIB 5
483
484 /**
485
486 PAL Procedure - PAL_PREFETCH_VISIBILITY.
487
488 Used in architected sequence to transition pages from a
489 cacheable, speculative attribute to an uncacheable attribute.
490 It is required by IPF. The PAL procedure supports the Static
491 Registers calling convention. It could be called at physical
492 mode and Virtual mode.
493
494 @param Index Index of PAL_PREFETCH_VISIBILITY within the list
495 of PAL procedures.
496
497 @param TransitionType Unsigned integer specifying the type
498 of memory attribute transition that is
499 being performed.
500
501 @return Status 1 Call completed without error; this
502 call is not necessary on remote
503 processors.
504
505 @return Status 0 - Call completed without error
506
507 @return Status -2 - Invalid argument
508
509 @return Status -3 - Call completed with error.
510
511 **/
512 #define PAL_PREFETCH_VISIBILITY 41
513
514 /**
515
516 PAL Procedure - PAL_PTCE_INFO.
517
518 Return information needed for ptc.e instruction to purge
519 entire TC. It is required by IPF. The PAL procedure supports
520 the Static Registers calling convention. It could be called at
521 physical mode and Virtual mode.
522
523 @param Index Index of PAL_PTCE_INFO within the list
524 of PAL procedures.
525
526 @return R9 Unsigned 64-bit integer denoting the beginning
527 address to be used by the first PTCE instruction
528 in the purge loop.
529
530 @return R10 Two unsigned 32-bit integers denoting the loop
531 counts of the outer (loop 1) and inner (loop 2)
532 purge loops. count1 (loop 1) is contained in bits
533 63:32 of the parameter, and count2 (loop 2) is
534 contained in bits 31:0 of the parameter.
535
536 @return R11 Two unsigned 32-bit integers denoting the loop
537 strides of the outer (loop 1) and inner (loop 2)
538 purge loops. stride1 (loop 1) is contained in bits
539 63:32 of the parameter, and stride2 (loop 2) is
540 contained in bits 31:0 of the parameter.
541
542 @return Status 0 - Call completed without error
543
544 @return Status -2 - Invalid argument
545
546 @return Status -3 - Call completed with error.
547
548 **/
549 #define PAL_PTCE_INFO 6
550
551
552
553 /**
554
555 @param NumberSets Unsigned 8-bit integer denoting the number
556 of hash sets for the specified level
557 (1=fully associative)
558
559 @param NumberWays Unsigned 8-bit integer denoting the
560 associativity of the specified level
561 (1=direct).
562
563 @param NumberEntries Unsigned 16-bit integer denoting the
564 number of entries in the specified TC.
565
566
567 @param PageSizeIsOptimized Flag denoting whether the
568 specified level is optimized for
569 the region's preferred page size
570 (1=optimized) tc_pages indicates
571 which page sizes are usable by
572 this translation cache.
573
574 @param TcIsUnified Flag denoting whether the specified TC is
575 unified (1=unified).
576
577 @param EntriesReduction Flag denoting whether installed
578 translation registers will reduce
579 the number of entries within the
580 specified TC.
581
582 **/
583 typedef struct {
584 UINT64 NumberSets:8;
585 UINT64 NumberWays:8;
586 UINT64 NumberEntries:16;
587 UINT64 PageSizeIsOptimized:1;
588 UINT64 TcIsUnified:1;
589 UINT64 EntriesReduction:1;
590 } PAL_TC_INFO;
591
592 /**
593
594 PAL Procedure - PAL_VM_INFO.
595
596 Return detailed information about virtual memory features
597 supported in the processor. It is required by IPF. The PAL
598 procedure supports the Static Registers calling convention. It
599 could be called at physical mode and Virtual mode.
600
601 @param Index Index of PAL_VM_INFO within the list
602 of PAL procedures.
603
604 @param TcLevel Unsigned 64-bit integer specifying the level
605 in the TLB hierarchy for which information is
606 required. This value must be between 0 and one
607 less than the value returned in the
608 vm_info_1.num_tc_levels return value from
609 PAL_VM_SUMMARY.
610
611 @param TcType Unsigned 64-bit integer with a value of 1 for
612 instruction translation cache and 2 for data
613 or unified translation cache. All other values
614 are reserved.
615
616 @return R9 8-byte formatted value returning information
617 about the specified TC. See PAL_TC_INFO above.
618
619 @return R10 64-bit vector containing a bit for each page
620 size supported in the specified TC, where bit
621 position n indicates a page size of 2**n.
622
623 @return Status 0 - Call completed without error
624
625 @return Status -2 - Invalid argument
626
627 @return Status -3 - Call completed with error.
628
629 **/
630 #define PAL_VM_INFO 7
631
632
633 /**
634
635 PAL Procedure - PAL_VM_PAGE_SIZE.
636
637 Return virtual memory TC and hardware walker page sizes
638 supported in the processor. It is required by IPF. The PAL
639 procedure supports the Static Registers calling convention. It
640 could be called at physical mode and Virtual mode.
641
642 @param Index Index of PAL_VM_PAGE_SIZE within the list
643 of PAL procedures.
644
645
646 @return R9 64-bit vector containing a bit for each
647 architected page size that is supported for
648 TLB insertions and region registers.
649
650 @return R10 64-bit vector containing a bit for each
651 architected page size supported for TLB purge
652 operations.
653
654 @return Status 0 - Call completed without error
655
656 @return Status -2 - Invalid argument
657
658 @return Status -3 - Call completed with error.
659
660 **/
661 #define PAL_VM_PAGE_SIZE 34
662
663 /**
664
665 @param WalkerPresent 1-bit flag indicating whether a hardware
666 TLB walker is implemented (1 = walker
667 present).
668
669 @param WidthOfPhysicalAddress Unsigned 7-bit integer
670 denoting the number of bits of
671 physical address implemented.
672
673 @param WidthOfKey Unsigned 8-bit integer denoting the number
674 of bits mplemented in the PKR.key field.
675
676 @param MaxPkrIndex Unsigned 8-bit integer denoting the
677 maximum PKR index (number of PKRs-1).
678
679 @param HashTagId Unsigned 8-bit integer which uniquely
680 identifies the processor hash and tag
681 algorithm.
682
683 @param MaxDtrIndex Unsigned 8 bit integer denoting the
684 maximum data translation register index
685 (number of dtr entries - 1).
686
687 @param MaxItrIndex Unsigned 8 bit integer denoting the
688 maximum instruction translation register
689 index (number of itr entries - 1).
690
691 @param NumberOfUniqueTc Unsigned 8-bit integer denoting the
692 number of unique TCs implemented.
693 This is a maximum of
694 2*num_tc_levels.
695
696 @param NumberOfTcLevels Unsigned 8-bit integer denoting the
697 number of TC levels.
698
699 **/
700 typedef struct {
701 UINT64 WalkerPresent:1;
702 UINT64 WidthOfPhysicalAddress: 7;
703 UINT64 WidthOfKey:8;
704 UINT64 MaxPkrIndex:8;
705 UINT64 HashTagId:8;
706 UINT64 MaxDtrIndex:8;
707 UINT64 MaxItrIndex:8;
708 UINT64 NumberOfUniqueTc:8;
709 UINT64 NumberOfTcLevels:8;
710 } PAL_VM_INFO1;
711
712 /**
713
714 @param WidthOfVirtualAddress Unsigned 8-bit integer denoting
715 is the total number of virtual
716 address bits - 1.
717
718 @param WidthOfRid Unsigned 8-bit integer denoting the number
719 of bits implemented in the RR.rid field.
720
721 @param MaxPurgedTlbs Unsigned 16 bit integer denoting the
722 maximum number of concurrent outstanding
723 TLB purges allowed by the processor. A
724 value of 0 indicates one outstanding
725 purge allowed. A value of 216-1
726 indicates no limit on outstanding
727 purges. All other values indicate the
728 actual number of concurrent outstanding
729 purges allowed.
730
731 **/
732 typedef struct {
733 UINT64 WidthOfVirtualAddress:8;
734 UINT64 WidthOfRid:8;
735 UINT64 MaxPurgedTlbs:16;
736 UINT64 Reserved:32;
737 } PAL_VM_INFO2;
738
739 /**
740
741 PAL Procedure - PAL_VM_SUMMARY.
742
743 Return summary information about virtual memory features
744 supported in the processor. It is required by IPF. The PAL
745 procedure supports the Static Registers calling convention. It
746 could be called at physical mode and Virtual mode.
747
748 @param Index Index of PAL_VM_SUMMARY within the list
749 of PAL procedures.
750
751
752 @return R9 8-byte formatted value returning global virtual
753 memory information. See PAL_VM_INFO1 above.
754
755 @return R10 8-byte formatted value returning global virtual
756 memory information. See PAL_VM_INFO2 above.
757
758 @return Status 0 - Call completed without error
759
760 @return Status -2 - Invalid argument
761
762 @return Status -3 - Call completed with error.
763
764 **/
765 #define PAL_VM_SUMMARY 8
766
767
768 //
769 // Bit mask of TR_valid flag.
770 //
771 #define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0
772 #define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1
773 #define PAL_TR_DIRTY_IS_VALID BIT2
774 #define PAL_TR_MEMORY_ATTR_IS_VALID BIT3
775
776
777 /**
778
779 PAL Procedure - PAL_VM_TR_READ.
780
781 Read contents of a translation register. It is required by
782 IPF. The PAL procedure supports the Stacked Register calling
783 convention. It could be called at physical mode.
784
785 @param Index Index of PAL_VM_TR_READ within the list
786 of PAL procedures.
787
788 @param RegNumber Unsigned 64-bit number denoting which TR to
789 read.
790
791 @param TrType Unsigned 64-bit number denoting whether to
792 read an ITR (0) or DTR (1). All other values
793 are reserved.
794
795 @param TrBuffer 64-bit pointer to the 32-byte memory buffer in
796 which translation data is returned.
797
798 @return R9 Formatted bit vector denoting which fields are
799 valid. See TR_valid above.
800
801 @return Status 0 - Call completed without error
802
803 @return Status -2 - Invalid argument
804
805 @return Status -3 - Call completed with error.
806
807 **/
808 #define PAL_VM_TR_READ 261
809
810
811
812
813 //
814 // Bit Mask of Processor Bus Fesatures .
815 //
816
817 /**
818
819 When 0, bus data errors are detected and single bit errors are
820 corrected. When 1, no error detection or correction is done.
821
822 **/
823 #define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63
824
825
826 /**
827
828 When 0, bus address errors are signalled on the bus. When 1,
829 no bus errors are signalled on the bus. If Disable Bus Address
830 Error Checking is 1, this bit is ignored.
831
832 **/
833 #define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62
834
835
836
837
838 /**
839
840 When 0, bus errors are detected, single bit errors are
841 corrected., and a CMCI or MCA is generated internally to the
842 processor. When 1, no bus address errors are detected or
843 corrected.
844
845 **/
846 #define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61
847
848
849 /**
850
851 When 0, bus protocol errors (BINIT#) are signaled by the
852 processor on the bus. When 1, bus protocol errors (BINIT#) are
853 not signaled on the bus. If Disable Bus Initialization Event
854 Checking is 1, this bit is ignored.
855
856 **/
857 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60
858
859
860 /**
861
862 When 0, bus protocol errors (BINIT#) are detected and sampled
863 and an MCA is generated internally to the processor. When 1,
864 the processor will ignore bus protocol error conditions
865 (BINIT#).
866
867 **/
868 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59
869
870
871
872 /**
873
874 When 0, BERR# is signalled if a bus error is detected. When 1,
875 bus errors are not signalled on the bus.
876
877 **/
878 #define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58
879
880
881
882
883 /**
884
885 When 0, BERR# is signalled when internal processor requestor
886 initiated bus errors are detected. When 1, internal requester
887 bus errors are not signalled on the bus.
888
889 **/
890 #define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57
891
892
893 /**
894
895 When 0, the processor takes an MCA if BERR# is asserted. When
896 1, the processor ignores the BERR# signal.
897
898 **/
899 #define PAL_BUS_DISABLE_ERROR_CHECK BIT56
900
901
902 /**
903
904 When 0, the processor asserts BINIT# if it detects a parity
905 error on the signals which identify the transactions to which
906 this is a response. When 1, the processor ignores parity on
907 these signals.
908
909 **/
910 #define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55
911
912
913 /**
914
915 When 0, the in-order transaction queue is limited only by the
916 number of hardware entries. When 1, the processor's in-order
917 transactions queue is limited to one entry.
918
919 **/
920 #define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54
921
922 /**
923
924 Enable a bus cache line replacement transaction when a cache
925 line in the exclusive state is replaced from the highest level
926 processor cache and is not present in the lower level processor
927 caches. When 0, no bus cache line replacement transaction will
928 be seen on the bus. When 1, bus cache line replacement
929 transactions will be seen on the bus when the above condition is
930 detected.
931
932 **/
933 #define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53
934
935
936 /**
937
938 Enable a bus cache line replacement transaction when a cache
939 line in the shared or exclusive state is replaced from the
940 highest level processor cache and is not present in the lower
941 level processor caches.
942 When 0, no bus cache line replacement transaction will be seen
943 on the bus. When 1, bus cache line replacement transactions
944 will be seen on the bus when the above condition is detected.
945
946 **/
947 #define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52
948
949
950
951 /**
952
953 When 0, the data bus is configured at the 2x data transfer
954 rate.When 1, the data bus is configured at the 1x data
955 transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the
956 processor executes locked transactions atomically. When 1, the
957 processor masks the bus lock signal and executes locked
958 transactions as a non-atomic series of transactions.
959
960 **/
961 #define PAL_BUS_ENABLE_HALF_TRANSFER BIT30
962
963 /**
964
965 When 0, the processor will deassert bus request when finished
966 with each transaction. When 1, the processor will continue to
967 assert bus request after it has finished, if it was the last
968 agent to own the bus and if there are no other pending
969 requests.
970
971 **/
972 #define PAL_BUS_REQUEST_BUS_PARKING BIT29
973
974
975 /**
976
977 PAL Procedure - PAL_BUS_GET_FEATURES.
978
979 Return configurable processor bus interface features and their
980 current settings. It is required by IPF. The PAL procedure
981 supports the Stacked Register calling convention. It could be
982 called at physical mode.
983
984 @param Index Index of PAL_BUS_GET_FEATURES within the list
985 of PAL procedures.
986
987 @return R9 64-bit vector of features implemented.
988 (1=implemented, 0=not implemented)
989
990 @return R10 64-bit vector of current feature settings.
991
992 @return R11 64-bit vector of features controllable by
993 software. (1=controllable, 0= not controllable)
994
995 @return Status 0 - Call completed without error
996
997 @return Status -2 - Invalid argument
998
999 @return Status -3 - Call completed with error.
1000
1001 **/
1002 #define PAL_BUS_GET_FEATURES 9
1003
1004 /**
1005
1006 PAL Procedure - PAL_BUS_SET_FEATURES.
1007
1008 Enable or disable configurable features in processor bus
1009 interface. It is required by IPF. It is required by IPF. The PAL procedure
1010 supports the Static Registers calling convention. It could be
1011 called at physical mode.
1012
1013 @param Index Index of PAL_BUS_SET_FEATURES within the list
1014 of PAL procedures.
1015
1016 @param FeatureSelect 64-bit vector denoting desired state of
1017 each feature (1=select, 0=non-select).
1018
1019 @return Status 0 - Call completed without error
1020
1021 @return Status -2 - Invalid argument
1022
1023 @return Status -3 - Call completed with error.
1024
1025 **/
1026 #define PAL_BUS_SET_FEATURES 10
1027
1028
1029 /**
1030
1031 PAL Procedure - PAL_DEBUG_INFO.
1032
1033 Return the number of instruction and data breakpoint
1034 registers. It is required by IPF. It is required by IPF. The
1035 PAL procedure supports the Static Registers calling
1036 convention. It could be called at physical mode and virtual
1037 mode.
1038
1039 @param Index Index of PAL_DEBUG_INFO within the list of PAL
1040 procedures.
1041
1042 @return R9 Unsigned 64-bit integer denoting the number of
1043 pairs of instruction debug registers implemented
1044 by the processor.
1045
1046 @return R10 Unsigned 64-bit integer denoting the number of
1047 pairs of data debug registers implemented by the
1048 processor.
1049
1050 @return Status 0 - Call completed without error
1051
1052 @return Status -2 - Invalid argument
1053
1054 @return Status -3 - Call completed with error.
1055
1056 **/
1057 #define PAL_DEBUG_INFO 11
1058
1059 /**
1060
1061 PAL Procedure - PAL_FIXED_ADDR.
1062
1063 Return the fixed component of a processor¡¯s directed address.
1064 It is required by IPF. It is required by IPF. The PAL
1065 procedure supports the Static Registers calling convention. It
1066 could be called at physical mode and virtual mode.
1067
1068 @param Index Index of PAL_FIXED_ADDR within the list of PAL
1069 procedures.
1070
1071 @return R9 Fixed geographical address of this processor.
1072
1073
1074 @return Status 0 - Call completed without error
1075
1076 @return Status -2 - Invalid argument
1077
1078 @return Status -3 - Call completed with error.
1079
1080 **/
1081 #define PAL_FIXED_ADDR 12
1082
1083 /**
1084
1085 PAL Procedure - PAL_FREQ_BASE.
1086
1087 Return the frequency of the output clock for use by the
1088 platform, if generated by the processor. It is optinal. The
1089 PAL procedure supports the Static Registers calling
1090 convention. It could be called at physical mode and virtual
1091 mode.
1092
1093 @param Index Index of PAL_FREQ_BASE within the list of PAL
1094 procedures.
1095
1096 @return R9 Base frequency of the platform if generated by the
1097 processor chip.
1098
1099
1100 @return Status 0 - Call completed without error
1101
1102 @return Status -1 - Unimplemented procedure
1103
1104 @return Status -2 - Invalid argument
1105
1106 @return Status -3 - Call completed with error.
1107
1108 **/
1109 #define PAL_FREQ_BASE 13
1110
1111
1112 /**
1113
1114 PAL Procedure - PAL_FREQ_RATIOS.
1115
1116 Return ratio of processor, bus, and interval time counter to
1117 processor input clock or output clock for platform use, if
1118 generated by the processor. It is required by IPF. The PAL
1119 procedure supports the Static Registers calling convention. It
1120 could be called at physical mode and virtual mode.
1121
1122 @param Index Index of PAL_FREQ_RATIOS within the list of PAL
1123 procedures.
1124
1125 @return R9 Ratio of the processor frequency to the input
1126 clock of the processor, if the platform clock is
1127 generated externally or to the output clock to the
1128 platform, if the platform clock is generated by
1129 the processor.
1130
1131 @return R10 Ratio of the bus frequency to the input clock of
1132 the processor, if the platform clock is generated
1133 externally or to the output clock to the platform,
1134 if the platform clock is generated by the
1135 processor.
1136
1137 @return R11 Ratio of the interval timer counter rate to input
1138 clock of the processor, if the platform clock is
1139 generated externally or to the output clock to the
1140 platform, if the platform clock is generated by
1141 the processor.
1142
1143 @return Status 0 - Call completed without error
1144
1145 @return Status -2 - Invalid argument
1146
1147 @return Status -3 - Call completed with error.
1148
1149 **/
1150 #define PAL_FREQ_RATIOS 14
1151
1152 /**
1153
1154 @param NumberOfLogicalProcessors Total number of logical
1155 processors on this physical
1156 processor package that are
1157 enabled.
1158
1159 @param ThreadsPerCore Number of threads per core.
1160
1161 @param CoresPerProcessor Total number of cores on this
1162 physical processor package.
1163
1164 @param PhysicalProcessorPackageId Physical processor package
1165 identifier which was
1166 assigned at reset by the
1167 platform or bus
1168 controller. This value may
1169 or may not be unique
1170 across the entire platform
1171 since it depends on the
1172 platform vendor's policy.
1173 **/
1174 typedef struct {
1175 UINT64 NumberOfLogicalProcessors:16;
1176 UINT64 ThreadsPerCore:8;
1177 UINT64 Reserved1:8;
1178 UINT64 CoresPerProcessor;
1179 UINT64 Reserved2:8;
1180 UINT64 PhysicalProcessorPackageId:8;
1181 UINT64 Reserved3:8;
1182 } PAL_LOGICAL_PROCESSPR_OVERVIEW;
1183
1184 /**
1185
1186 @param ThreadId The thread identifier of the logical
1187 processor for which information is being
1188 returned. This value will be unique on a per
1189 core basis.
1190
1191 @param CoreId The core identifier of the logical processor
1192 for which information is being returned.
1193 This value will be unique on a per physical
1194 processor package basis.
1195
1196 **/
1197 typedef struct {
1198 UINT64 ThreadId:16;
1199 UINT64 Reserved1:16;
1200 UINT64 CoreId:16;
1201 UINT64 Reserved2:16;
1202 } PAL_LOGICAL_PROCESSORN_INFO1;
1203
1204
1205 /**
1206
1207 @param LogicalAddress Geographical address of the logical
1208 processor for which information is being
1209 returned. This is the same value that is
1210 returned by the PAL_FIXED_ADDR procedure
1211 when it is called on the logical
1212 processor.
1213
1214
1215 **/
1216 typedef struct {
1217 UINT64 LogicalAddress:16;
1218 UINT64 Reserved:48;
1219 } PAL_LOGICAL_PROCESSORN_INFO2;
1220
1221 /**
1222
1223 PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.
1224
1225 Return information on which logical processors map to a
1226 physical processor die. It is optinal. The PAL procedure
1227 supports the Static Registers calling convention. It could be
1228 called at physical mode and virtual mode.
1229
1230 @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL
1231 procedures.
1232
1233 @param ProcessorNumber Signed 64-bit integer that specifies
1234 for which logical processor
1235 information is being requested. When
1236 this input argument is -1, information
1237 is returned about the logical
1238 processor on which the procedure call
1239 is made. This input argument must be
1240 in the range of 1 up to one less than
1241 the number of logical processors
1242 returned by num_log in the
1243 log_overview return value.
1244
1245
1246 @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.
1247
1248 @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.
1249
1250 @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.
1251
1252
1253 @return Status 0 - Call completed without error
1254
1255 @return Status -1 - Unimplemented procedure
1256
1257 @return Status -2 - Invalid argument
1258
1259 @return Status -3 - Call completed with error.
1260
1261 **/
1262 #define PAL_LOGICAL_TO_PHYSICAL 42
1263
1264
1265 /**
1266
1267 @param NumberOfPmcPairs Unsigned 8-bit number defining the
1268 number of generic PMC/PMD pairs.
1269
1270 @param WidthOfCounter Unsigned 8-bit number in the range
1271 0:60 defining the number of
1272 implemented counter bits.
1273
1274 @param TypeOfCycleCounting Unsigned 8-bit number defining the
1275 event type for counting processor
1276 cycles.
1277
1278
1279 @param TypeOfRetiredInstructionBundle Retired Unsigned 8-bit
1280 number defining the
1281 event type for retired
1282 instruction bundles.
1283
1284 **/
1285 typedef struct {
1286 UINT64 NumberOfPmcPairs:8;
1287 UINT64 WidthOfCounter:8;
1288 UINT64 TypeOfCycleCounting:8;
1289 UINT64 TypeOfRetiredInstructionBundle:8;
1290 UINT64 Reserved:32;
1291 } PAL_PERFORMANCE_INFO;
1292
1293 /**
1294
1295 PAL Procedure - PAL_PERF_MON_INFO.
1296
1297 Return the number and type of performance monitors. It is
1298 required by IPF. The PAL procedure supports the Static
1299 Registers calling convention. It could be called at physical
1300 mode and virtual mode.
1301
1302 @param Index Index of PAL_PERF_MON_INFO within the list of
1303 PAL procedures.
1304
1305 @param PerformanceBuffer An address to an 8-byte aligned
1306 128-byte memory buffer.
1307
1308
1309 @return R9 Information about the performance monitors
1310 implemented. See PAL_PERFORMANCE_INFO;
1311
1312 @return Status 0 - Call completed without error
1313
1314 @return Status -2 - Invalid argument
1315
1316 @return Status -3 - Call completed with error.
1317
1318 **/
1319 #define PAL_PERF_MON_INFO 15
1320
1321 /**
1322
1323 PAL Procedure - PAL_PLATFORM_ADDR.
1324
1325 Specify processor interrupt block address and I/O port space
1326 address. It is required by IPF. The PAL procedure supports the
1327 Static Registers calling convention. It could be called at
1328 physical mode and virtual mode.
1329
1330 @param Index Index of PAL_PLATFORM_ADDR within the list of
1331 PAL procedures.
1332
1333 @param Type Unsigned 64-bit integer specifying the type of
1334 block. 0 indicates that the processor interrupt
1335 block pointer should be initialized. 1 indicates
1336 that the processor I/O block pointer should be
1337 initialized.
1338
1339 @param Address Unsigned 64-bit integer specifying the address
1340 to which the processor I/O block or interrupt
1341 block shall be set. The address must specify
1342 an implemented physical address on the
1343 processor model, bit 63 is ignored.
1344
1345
1346 @return Status 0 - Call completed without error
1347
1348 @return Status -1 - Unimplemented procedure.
1349
1350 @return Status -2 - Invalid argument
1351
1352 @return Status -3 - Call completed with error.
1353
1354 **/
1355 #define PAL_PLATFORM_ADDR 16
1356
1357
1358 /**
1359
1360 @param EnableBerrPromotion Bit63. Enable BERR promotion. When
1361 1, the Bus Error (BERR) signal is
1362 promoted to the Bus Initialization
1363 (BINIT) signal, and the BINIT pin
1364 is asserted on the occurrence of
1365 each Bus Error. Setting this bit
1366 has no effect if BINIT signalling
1367 is disabled. (See
1368 PAL_BUS_GET/SET_FEATURES)
1369
1370 @param EnableMcaPromotion Bit62, Enable MCA promotion. When
1371 1, machine check aborts (MCAs) are
1372 promoted to the Bus Error signal,
1373 and the BERR pin is assert on each
1374 occurrence of an MCA. Setting this
1375 bit has no effect if BERR
1376 signalling is disabled. (See
1377 PAL_BUS_GET/SET_FEATURES)
1378
1379 @param EnableMcaToBinitPromotion Bit61, Enable MCA to BINIT
1380 promotion. When 1, machine
1381 check aborts (MCAs) are
1382 promoted to the Bus
1383 Initialization signal, and
1384 the BINIT pin is assert on
1385 each occurrence of an MCA.
1386 Setting this bit has no
1387 effect if BINIT signalling
1388 is disabled. (See
1389 PAL_BUS_GET/SET_FEATURES)
1390
1391 @param EnableCmciPromotion Bit60, Enable CMCI promotion When
1392 1, Corrected Machine Check
1393 Interrupts (CMCI) are promoted to
1394 MCAs. They are also further
1395 promoted to BERR if bit 39, Enable
1396 MCA promotion, is also set and
1397 they are promoted to BINIT if bit
1398 38, Enable MCA to BINIT promotion,
1399 is also set. This bit has no
1400 effect if MCA signalling is
1401 disabled (see
1402 PAL_BUS_GET/SET_FEATURES)
1403
1404 @param DisableCache Bit59, Disable Cache. When 0, the
1405 processor performs cast outs on
1406 cacheable pages and issues and responds
1407 to coherency requests normally. When 1,
1408 the processor performs a memory access
1409 for each reference regardless of cache
1410 contents and issues no coherence
1411 requests and responds as if the line
1412 were not present. Cache contents cannot
1413 be relied upon when the cache is
1414 disabled. WARNING: Semaphore
1415 instructions may not be atomic or may
1416 cause Unsupported Data Reference faults
1417 if caches are disabled.
1418
1419 @param DisableCoherency Bit58, Disable Coherency. When 0,
1420 the processor uses normal coherency
1421 requests and responses. When 1, the
1422 processor answers all requests as if
1423 the line were not present.
1424
1425 @param DisableDPM Bit57, Disable Dynamic Power Management
1426 (DPM). When 0, the hardware may reduce
1427 power consumption by removing the clock
1428 input from idle functional units. When 1,
1429 all functional units will receive clock
1430 input, even when idle.
1431
1432 @param DisableBinitWithTimeout Bit56, Disable a BINIT on
1433 internal processor time-out.
1434 When 0, the processor may
1435 generate a BINIT on an
1436 internal processor time-out.
1437 When 1, the processor will not
1438 generate a BINIT on an
1439 internal processor time-out.
1440 The event is silently ignored.
1441
1442
1443 @param EnableEnvNotification Bit55, Enable external
1444 notification when the processor
1445 detects hardware errors caused
1446 by environmental factors that
1447 could cause loss of
1448 deterministic behavior of the
1449 processor. When 1, this bit will
1450 enable external notification,
1451 when 0 external notification is
1452 not provided. The type of
1453 external notification of these
1454 errors is processor-dependent. A
1455 loss of processor deterministic
1456 behavior is considered to have
1457 occurred if these
1458 environmentally induced errors
1459 cause the processor to deviate
1460 from its normal execution and
1461 eventually causes different
1462 behavior which can be observed
1463 at the processor bus pins.
1464 Processor errors that do not
1465 have this effects (i.e.,
1466 software induced machine checks)
1467 may or may not be promoted
1468 depending on the processor
1469 implementation.
1470
1471 @param EnableVmsw Bit54, Enable the use of the vmsw
1472 instruction. When 0, the vmsw instruction
1473 causes a Virtualization fault when
1474 executed at the most privileged level.
1475 When 1, this bit will enable normal
1476 operation of the vmsw instruction.
1477
1478 @param EnableMcaOnDataPoisoning Bit53, Enable MCA signaling
1479 on data-poisoning event
1480 detection. When 0, a CMCI
1481 will be signaled on error
1482 detection. When 1, an MCA
1483 will be signaled on error
1484 detection. If this feature
1485 is not supported, then the
1486 corresponding argument is
1487 ignored when calling
1488 PAL_PROC_SET_FEATURES. Note
1489 that the functionality of
1490 this bit is independent of
1491 the setting in bit 60
1492 (Enable CMCI promotion), and
1493 that the bit 60 setting does
1494 not affect CMCI signaling
1495 for data-poisoning related
1496 events. Volume 2: Processor
1497 Abstraction Layer 2:431
1498 PAL_PROC_GET_FEATURES
1499
1500 @param DisablePState Bit52, Disable P-states. When 1, the PAL
1501 P-state procedures (PAL_PSTATE_INFO,
1502 PAL_SET_PSTATE, PAL_GET_PSTATE) will
1503 return with a status of -1
1504 (Unimplemented procedure).
1505
1506 @param DisableBranchPrediction Bit47, Disable Dynamic branch
1507 prediction. When 0, the
1508 processor may predict branch
1509 targets and speculatively
1510 execute, but may not commit
1511 results. When 1, the processor
1512 must wait until branch targets
1513 are known to execute.
1514
1515 @param DisableDynamicInsCachePrefetch Bit46, Disable
1516 DynamicInstruction Cache
1517 Prefetch. When 0, the
1518 processor may prefetch
1519 into the caches any
1520 instruction which has
1521 not been executed, but
1522 whose execution is
1523 likely. When 1,
1524 instructions may not be
1525 fetched until needed or
1526 hinted for execution.
1527 (Prefetch for a hinted
1528 branch is allowed even
1529 when dynamic instruction
1530 cache prefetch is
1531 disabled.)
1532
1533 @param DisableDynamicDataCachePrefetch Bit45, Disable Dynamic
1534 Data Cache Prefetch.
1535 When 0, the processor
1536 may prefetch into the
1537 caches any data which
1538 has not been accessed
1539 by instruction
1540 execution, but which
1541 is likely to be
1542 accessed. When 1, no
1543 data may be fetched
1544 until it is needed for
1545 instruction execution
1546 or is fetched by an
1547 lfetch instruction.
1548
1549 @param DisableSpontaneousDeferral Bit44, Disable Spontaneous
1550 Deferral. When 1, the
1551 processor may optionally
1552 defer speculative loads
1553 that do not encounter any
1554 exception conditions, but
1555 that trigger other
1556 implementation-dependent
1557 conditions (e.g., cache
1558 miss). When 0, spontaneous
1559 deferral is disabled.
1560
1561 @param DisableDynamicPrediction Bit43, Disable Dynamic
1562 Predicate Prediction. When
1563 0, the processor may predict
1564 predicate results and
1565 execute speculatively, but
1566 may not commit results until
1567 the actual predicates are
1568 known. When 1, the processor
1569 shall not execute predicated
1570 instructions until the
1571 actual predicates are known.
1572
1573 @param NoXr1ThroughXr3 Bit42, No XR1 through XR3 implemented.
1574 Denotes whether XR1 XR3 are
1575 implemented for machine check
1576 recovery. This feature may only be
1577 interrogated by PAL_PROC_GET_FEATURES.
1578 It may not be enabled or disabled by
1579 PAL_PROC_SET_FEATURES. The
1580 corresponding argument is ignored.
1581
1582 @param NoXipXpsrXfs Bit41, No XIP, XPSR, and XFS
1583 implemented. Denotes whether XIP, XPSR,
1584 and XFS are implemented for machine
1585 check recovery. This feature may only be
1586 interrogated by PAL_PROC_GET_FEATURES.
1587 It may not be enabled or disabled by
1588 PAL_PROC_SET_FEATURES. The corresponding
1589 argument is ignored.
1590
1591 @param NoVM Bit40, No Virtual Machine features implemented.
1592 Denotes whether PSR.vm is implemented. This
1593 feature may only be interrogated by
1594 PAL_PROC_GET_FEATURES. It may not be enabled or
1595 disabled by PAL_PROC_SET_FEATURES. The
1596 corresponding argument is ignored.
1597
1598 @param NoVariablePState Bit39, No Variable P-state
1599 performance: A value of 1, indicates
1600 that a processor implements
1601 techniques to optimize performance
1602 for the given P-state power budget
1603 by dynamically varying the
1604 frequency, such that maximum
1605 performance is achieved for the
1606 power budget. A value of 0,
1607 indicates that P-states have no
1608 frequency variation or very small
1609 frequency variations for their given
1610 power budget. This feature may only
1611 be interrogated by
1612 PAL_PROC_GET_FEATURES. it may not be
1613 enabled or disabled by
1614 PAL_PROC_SET_FEATURES. The
1615 corresponding argument is ignored.
1616
1617
1618 @param NoSimpleImpInUndefinedIns Bit38, No Simple
1619 implementation of
1620 unimplemented instruction
1621 addresses. Denotes how an
1622 unimplemented instruction
1623 address is recorded in IIP
1624 on an Unimplemented
1625 Instruction Address trap or
1626 fault. When 1, the full
1627 unimplemented address is
1628 recorded in IIP; when 0, the
1629 address is sign extended
1630 (virtual addresses) or zero
1631 extended (physical
1632 addresses). This feature may
1633 only be interrogated by
1634 PAL_PROC_GET_FEATURES. It
1635 may not be enabled or
1636 disabled by
1637 PAL_PROC_SET_FEATURES. The
1638 corresponding argument is
1639 ignored.
1640
1641 @param NoPresentPmi Bit37, No INIT, PMI, and LINT pins
1642 present. Denotes the absence of INIT,
1643 PMI, LINT0 and LINT1 pins on the
1644 processor. When 1, the pins are absent.
1645 When 0, the pins are present. This
1646 feature may only be interrogated by
1647 PAL_PROC_GET_FEATURES. It may not be
1648 enabled or disabled by
1649 PAL_PROC_SET_FEATURES. The corresponding
1650 argument is ignored.
1651
1652 @param FaultInUndefinedIns Bit36, No Unimplemented
1653 instruction address reported as
1654 fault. Denotes how the processor
1655 reports the detection of
1656 unimplemented instruction
1657 addresses. When 1, the processor
1658 reports an Unimplemented
1659 Instruction Address fault on the
1660 unimplemented address; when 0, it
1661 reports an Unimplemented
1662 Instruction Address trap on the
1663 previous instruction in program
1664 order. This feature may only be
1665 interrogated by
1666 PAL_PROC_GET_FEATURES. It may not
1667 be enabled or disabled by
1668 PAL_PROC_SET_FEATURES. The
1669 corresponding argument is
1670 ignored.
1671
1672 **/
1673 typedef struct {
1674 UINT64 Reserved1:36;
1675 UINT64 FaultInUndefinedIns:1;
1676 UINT64 NoPresentPmi:1;
1677 UINT64 NoSimpleImpInUndefinedIns:1;
1678 UINT64 NoVariablePState:1;
1679 UINT64 NoVM:1;
1680 UINT64 NoXipXpsrXfs:1;
1681 UINT64 NoXr1ThroughXr3:1;
1682 UINT64 DisableDynamicPrediction:1;
1683 UINT64 DisableSpontaneousDeferral:1;
1684 UINT64 DisableDynamicDataCachePrefetch:1;
1685 UINT64 DisableDynamicInsCachePrefetch:1;
1686 UINT64 DisableBranchPrediction:1;
1687 UINT64 Reserved2:4;
1688 UINT64 DisablePState:1;
1689 UINT64 EnableMcaOnDataPoisoning:1;
1690 UINT64 EnableVmsw:1;
1691 UINT64 EnableEnvNotification:1;
1692 UINT64 DisableBinitWithTimeout:1;
1693 UINT64 DisableDPM:1;
1694 UINT64 DisableCoherency:1;
1695 UINT64 DisableCache:1;
1696 UINT64 EnableCmciPromotion:1;
1697 UINT64 EnableMcaToBinitPromotion:1;
1698 UINT64 EnableMcaPromotion:1;
1699 UINT64 EnableBerrPromotion:1;
1700 } PAL_PROCESSOR_FEATURES;
1701
1702 /**
1703
1704 PAL Procedure - PAL_PROC_GET_FEATURES.
1705
1706 Return configurable processor features and their current
1707 setting. It is required by IPF. The PAL procedure supports the
1708 Static Registers calling convention. It could be called at
1709 physical mode and virtual mode.
1710
1711 @param Index Index of PAL_PROC_GET_FEATURES within the list of
1712 PAL procedures.
1713
1714 @param Reserved Reserved parameter.
1715
1716 @param FeatureSet Feature set information is being requested
1717 for.
1718
1719
1720 @return R9 64-bit vector of features implemented. See
1721 PAL_PROCESSOR_FEATURES.
1722
1723 @return R10 64-bit vector of current feature settings. See
1724 PAL_PROCESSOR_FEATURES.
1725
1726 @return R11 64-bit vector of features controllable by
1727 software.
1728
1729 @return Status 1 - Call completed without error; The
1730 feature_set passed is not supported but a
1731 feature_set of a larger value is supported.
1732
1733 @return Status 0 - Call completed without error
1734
1735 @return Status -2 - Invalid argument
1736
1737 @return Status -3 - Call completed with error.
1738
1739 @return Status -8 - feature_set passed is beyond the maximum
1740 feature_set supported
1741
1742 **/
1743 #define PAL_PROC_GET_FEATURES 17
1744
1745
1746 /**
1747
1748 PAL Procedure - PAL_PROC_SET_FEATURES.
1749
1750 Enable or disable configurable processor features. It is
1751 required by IPF. The PAL procedure supports the Static
1752 Registers calling convention. It could be called at physical
1753 mode.
1754
1755 @param Index Index of PAL_PROC_SET_FEATURES within the list of
1756 PAL procedures.
1757
1758 @param FeatureSelect 64-bit vector denoting desired state of
1759 each feature (1=select, 0=non-select).
1760
1761 @param FeatureSet Feature set to apply changes to. See
1762 PAL_PROC_GET_FEATURES for more information
1763 on feature sets.
1764
1765
1766
1767 @return Status 1 - Call completed without error; The
1768 feature_set passed is not supported but a
1769 feature_set of a larger value is supported
1770
1771 @return Status 0 - Call completed without error
1772
1773 @return Status -2 - Invalid argument
1774
1775 @return Status -3 - Call completed with error.
1776
1777 @return Status -8 - feature_set passed is beyond the maximum
1778 feature_set supported
1779
1780 **/
1781 #define PAL_PROC_SET_FEATURES 18
1782
1783
1784 //
1785 // Value of PAL_REGISTER_INFO.InfoRequest.
1786 //
1787 #define PAL_APPLICATION_REGISTER_IMPLEMENTED 0
1788 #define PAL_APPLICATION_REGISTER_READABLE 1
1789 #define PAL_CONTROL_REGISTER_IMPLEMENTED 2
1790 #define PAL_CONTROL_REGISTER_READABLE 3
1791
1792
1793 /**
1794
1795 PAL Procedure - PAL_REGISTER_INFO.
1796
1797 Return AR and CR register information. It is required by IPF.
1798 The PAL procedure supports the Static Registers calling
1799 convention. It could be called at physical mode and virtual
1800 mode.
1801
1802 @param Index Index of PAL_REGISTER_INFO within the list of
1803 PAL procedures.
1804
1805 @param InfoRequest Unsigned 64-bit integer denoting what
1806 register information is requested. See
1807 PAL_REGISTER_INFO.InfoRequest above.
1808
1809 @return R9 64-bit vector denoting information for registers
1810 0-63. Bit 0 is register 0, bit 63 is register 63.
1811
1812 @return R10 64-bit vector denoting information for registers
1813 64-127. Bit 0 is register 64, bit 63 is register
1814 127.
1815
1816
1817 @return Status 0 - Call completed without error
1818
1819 @return Status -2 - Invalid argument
1820
1821 @return Status -3 - Call completed with error.
1822
1823
1824 **/
1825 #define PAL_REGISTER_INFO 39
1826
1827 /**
1828
1829 PAL Procedure - PAL_RSE_INFO.
1830
1831 Return RSE information. It is required by IPF. The PAL
1832 procedure supports the Static Registers calling convention. It
1833 could be called at physical mode and virtual mode.
1834
1835 @param Index Index of PAL_RSE_INFO within the list of
1836 PAL procedures.
1837
1838 @param InfoRequest Unsigned 64-bit integer denoting what
1839 register information is requested. See
1840 PAL_REGISTER_INFO.InfoRequest above.
1841
1842 @return R9 Number of physical stacked general registers.
1843
1844 @return R10 RSE hints supported by processor.
1845
1846 @return Status 0 - Call completed without error
1847
1848 @return Status -2 - Invalid argument
1849
1850 @return Status -3 - Call completed with error.
1851
1852
1853 **/
1854 #define PAL_RSE_INFO 19
1855
1856 /**
1857
1858 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
1859 number that provides identification
1860 information about the PAL_B firmware.
1861
1862 @param PalVendor Is an unsigned 8-bit integer indicating the
1863 vendor of the PAL code.
1864
1865 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
1866 number that provides identification
1867 information about the PAL_A firmware. In
1868 the split PAL_A model, this return value
1869 is the version number of the
1870 processor-specific PAL_A. The generic
1871 PAL_A version is not returned by this
1872 procedure in the split PAL_A model.
1873
1874 **/
1875 typedef struct {
1876 UINT64 VersionOfPalB:16;
1877 UINT64 Reserved1:8;
1878 UINT64 PalVendor:8;
1879 UINT64 VersionOfPalA:16;
1880 UINT64 Reserved2:16;
1881 } PAL_VERSION_INFO;
1882
1883 /**
1884
1885 PAL Procedure - PAL_VERSION.
1886
1887 Return version of PAL code. It is required by IPF. The PAL
1888 procedure supports the Static Registers calling convention. It
1889 could be called at physical mode and virtual mode.
1890
1891 @param Index Index of PAL_VERSION within the list of
1892 PAL procedures.
1893
1894 @param InfoRequest Unsigned 64-bit integer denoting what
1895 register information is requested. See
1896 PAL_REGISTER_INFO.InfoRequest above.
1897
1898 @return R9 8-byte formatted value returning the minimum PAL
1899 version needed for proper operation of the
1900 processor. See PAL_VERSION_INFO above.
1901
1902 @return R10 8-byte formatted value returning the current PAL
1903 version running on the processor. See
1904 PAL_VERSION_INFO above.
1905
1906 @return Status 0 - Call completed without error
1907
1908 @return Status -2 - Invalid argument
1909
1910 @return Status -3 - Call completed with error.
1911
1912
1913 **/
1914 #define PAL_VERSION 20
1915
1916
1917
1918 //
1919 // Vectors of PAL_MC_CLEAR_LOG.pending
1920 //
1921 #define PAL_MC_PENDING BIT0
1922 #define PAL_INIT_PENDING BIT1
1923
1924 /**
1925
1926 PAL Procedure - PAL_MC_CLEAR_LOG.
1927
1928 Clear all error information from processor error logging
1929 registers. It is required by IPF. The PAL procedure supports
1930 the Static Registers calling convention. It could be called at
1931 physical mode and virtual mode.
1932
1933 @param Index Index of PAL_MC_CLEAR_LOG within the list of
1934 PAL procedures.
1935
1936
1937 @return R9 64-bit vector denoting whether an event is
1938 pending. See PAL_MC_CLEAR_LOG.pending above.
1939
1940
1941 @return Status 0 - Call completed without error
1942
1943 @return Status -2 - Invalid argument
1944
1945 @return Status -3 - Call completed with error.
1946
1947
1948 **/
1949 #define PAL_MC_CLEAR_LOG 21
1950
1951 /**
1952
1953 PAL Procedure - PAL_MC_DRAIN.
1954
1955 Ensure that all operations that could cause an MCA have
1956 completed. It is required by IPF. The PAL procedure supports
1957 the Static Registers calling convention. It could be called at
1958 physical mode and virtual mode.
1959
1960 @param Index Index of PAL_MC_DRAIN within the list of PAL
1961 procedures.
1962
1963
1964 @return Status 0 - Call completed without error
1965
1966 @return Status -2 - Invalid argument
1967
1968 @return Status -3 - Call completed with error.
1969
1970
1971 **/
1972 #define PAL_MC_DRAIN 22
1973
1974
1975 /**
1976
1977 PAL Procedure - PAL_MC_DYNAMIC_STATE.
1978
1979 Return Processor Dynamic State for logging by SAL. It is
1980 optional. The PAL procedure supports the Static Registers
1981 calling convention. It could be called at physical mode.
1982
1983 @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL
1984 procedures.
1985
1986 @param Offset Offset of the next 8 bytes of Dynamic Processor
1987 State to return. (multiple of 8).
1988
1989 @return R9 Unsigned 64-bit integer denoting bytes of Dynamic
1990 Processor State returned.
1991
1992 @return R10 Next 8 bytes of Dynamic Processor State.
1993
1994 @return Status 0 - Call completed without error
1995
1996 @return Status -1 - Unimplemented procedure.
1997
1998 @return Status -2 - Invalid argument
1999
2000 @return Status -3 - Call completed with error.
2001
2002
2003 **/
2004 #define PAL_MC_DYNAMIC_STATE 24
2005
2006
2007
2008 //
2009 // Values of PAL_MC_ERROR_INFO.InfoIndex.
2010 //
2011 #define PAL_PROCESSOR_ERROR_MAP 0
2012 #define PAL_PROCESSOR_STATE_PARAM 1
2013 #define PAL_STRUCTURE_SPECIFIC_ERROR 2
2014
2015 /**
2016
2017 @param CoreId Bit3:0, Processor core ID (default is 0 for
2018 processors with a single core)
2019
2020 @param ThreadId Bit7:4, Logical thread ID (default is 0 for
2021 processors that execute a single thread)
2022
2023 @param InfoOfInsCache Bit11:8, Error information is
2024 available for 1st, 2nd, 3rd, and 4th
2025 level instruction caches.
2026
2027 @param InfoOfDataCache Bit15:12, Error information is
2028 available for 1st, 2nd, 3rd, and 4th
2029 level data/unified caches.
2030
2031 @param InfoOfInsTlb Bit19:16 Error information is available
2032 for 1st, 2nd, 3rd, and 4th level
2033 instruction TLB.
2034
2035 @param InfoOfDataTlb Bit23:20, Error information is available
2036 for 1st, 2nd, 3rd, and 4th level
2037 data/unified TLB
2038
2039 @param InfoOfProcessorBus Bit27:24 Error information is
2040 available for the 1st, 2nd, 3rd,
2041 and 4th level processor bus
2042 hierarchy.
2043
2044 @param InfoOfRegisterFile Bit31:28 Error information is
2045 available on register file
2046 structures.
2047
2048 @param InfoOfMicroArch Bit47:32, Error information is
2049 available on micro-architectural
2050 structures.
2051
2052 **/
2053 typedef struct {
2054 UINT64 CoreId:4;
2055 UINT64 ThreadId:4;
2056 UINT64 InfoOfInsCache:4;
2057 UINT64 InfoOfDataCache:4;
2058 UINT64 InfoOfInsTlb:4;
2059 UINT64 InfoOfDataTlb:4;
2060 UINT64 InfoOfProcessorBus:4;
2061 UINT64 InfoOfRegisterFile:4;
2062 UINT64 InfoOfMicroArch:4;
2063 UINT64 Reserved:16;
2064 } PAL_MC_ERROR_INFO_LEVEL_INDEX;
2065
2066 //
2067 // Value of PAL_MC_ERROR_INFO.ErrorTypeIndex
2068 //
2069 #define PAL_ERR_INFO_BY_LEVEL_INDEX 0
2070 #define PAL_ERR_INFO_TARGET_ADDRESS 1
2071 #define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2
2072 #define PAL_ERR_INFO_REPONSER_INDENTIFIER 3
2073 #define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4
2074
2075 /**
2076
2077 @param Operation Bit3:0, Type of cache operation that caused
2078 the machine check: 0 - unknown or internal
2079 error 1 - load 2 - store 3 - instruction
2080 fetch or instruction prefetch 4 - data
2081 prefetch (both hardware and software) 5 -
2082 snoop (coherency check) 6 - cast out
2083 (explicit or implicit write-back of a cache
2084 line) 7 - move in (cache line fill)
2085
2086 @param FailedCacheLevel Bit5:4 Level of cache where the
2087 error occurred. A value of 0
2088 indicates the first level of cache.
2089
2090 @param FailedInDataPart Bit8, Failure located in the data
2091 part of the cache line.
2092
2093 @param FailedInTagPart Bit9, Failure located in the tag part
2094 of the cache line.
2095
2096 @param FailedInDataCache Bit10, Failure located in the data
2097 cache
2098
2099 @param FailedInInsCache Bit11, Failure located in the
2100 instruction cache.
2101
2102
2103 @param Mesi Bit14:12, 0 - cache line is invalid. 1 - cache
2104 line is held shared. 2 - cache line is held
2105 exclusive. 3 - cache line is modified. All other
2106 values are reserved.
2107
2108 @param MesiIsValid Bit15, The mesi field in the cache_check
2109 parameter is valid.
2110
2111 @param FailedWay Bit20:16, Failure located in the way of
2112 the cache indicated by this value.
2113
2114 @param WayIndexIsValid Bit21, The way and index field in the
2115 cache_check parameter is valid.
2116
2117 @param MultipleBitsError Bit23, A multiple-bit error was
2118 detected, and data was poisoned for
2119 the corresponding cache line during
2120 castout.
2121
2122 @param IndexOfCacheLineError Bit51:32, Index of the cache
2123 line where the error occurred.
2124
2125 @param InstructionSet Bit54, Instruction set. If this value
2126 is set to zero, the instruction that
2127 generated the machine check was an
2128 Intel Itanium instruction. If this bit
2129 is set to one, the instruction that
2130 generated the machine check was IA-32
2131 instruction.
2132
2133 @param InstructionSetIsValid Bit55, The is field in the
2134 cache_check parameter is valid.
2135
2136 @param PrivilegeLevel Bit57:56, Privilege level. The
2137 privilege level of the instruction
2138 bundle responsible for generating the
2139 machine check.
2140
2141 @param PrivilegeLevelIsValide Bit58, The pl field of the
2142 cache_check parameter is
2143 valid.
2144
2145 @param McCorrected Bit59, Machine check corrected: This bit
2146 is set to one to indicate that the machine
2147 check has been corrected.
2148
2149 @param TargetAddressIsValid Bit60, Target address is valid:
2150 This bit is set to one to
2151 indicate that a valid target
2152 address has been logged.
2153
2154 @param RequesterIdentifier Bit61, Requester identifier: This
2155 bit is set to one to indicate that
2156 a valid requester identifier has
2157 been logged.
2158
2159 @param ResponserIdentifier Bit62, Responder identifier: This
2160 bit is set to one to indicate that
2161 a valid responder identifier has
2162 been logged.
2163
2164 @param PreciseInsPointer Bit63, Precise instruction pointer.
2165 This bit is set to one to indicate
2166 that a valid precise instruction
2167 pointer has been logged.
2168
2169 **/
2170 typedef struct {
2171 UINT64 Operation:4;
2172 UINT64 FailedCacheLevel:2;
2173 UINT64 Reserved1:2;
2174 UINT64 FailedInDataPart:1;
2175 UINT64 FailedInTagPart:1;
2176 UINT64 FailedInDataCache:1;
2177 UINT64 FailedInInsCache:1;
2178 UINT64 Mesi:3;
2179 UINT64 MesiIsValid:1;
2180 UINT64 FailedWay:5;
2181 UINT64 WayIndexIsValid:1;
2182
2183 UINT64 Reserved2:1;
2184 UINT64 MultipleBitsError:1;
2185 UINT64 Reserved3:8;
2186 UINT64 IndexOfCacheLineError:20;
2187 UINT64 Reserved4:2;
2188 UINT64 InstructionSet:1;
2189 UINT64 InstructionSetIsValid:1;
2190
2191 UINT64 PrivilegeLevel:2;
2192 UINT64 PrivilegeLevelIsValide:1;
2193
2194 UINT64 McCorrected:1;
2195
2196 UINT64 TargetAddressIsValid:1;
2197 UINT64 RequesterIdentifier:1;
2198 UINT64 ResponserIdentifier:1;
2199 UINT64 PreciseInsPointer:1;
2200
2201 } PAL_CACHE_CHECK_INFO;
2202
2203 /**
2204
2205 @param FailedSlot Bit7:0, Slot number of the translation
2206 register where the failure occurred.
2207
2208 @param FailedSlotIsValid Bit8, The tr_slot field in the
2209 TLB_check parameter is valid.
2210
2211 @param TlbLevel Bit11:10, The level of the TLB where the
2212 error occurred. A value of 0 indicates the
2213 first level of TLB
2214
2215 @param FailedInDataTr Bit16, Error occurred in the data
2216 translation registers.
2217
2218 @param FailedInInsTr Bit17, Error occurred in the instruction
2219 translation registers
2220
2221 @param FailedInDataTc Bit18, Error occurred in data
2222 translation cache.
2223
2224 @param FailedInInsTc Bit19, Error occurred in the instruction
2225 translation cache.
2226
2227 @param FailedOperation Bit23:20, Type of cache operation that
2228 caused the machine check: 0 - unknown
2229 1 - TLB access due to load instruction
2230 2 - TLB access due to store
2231 instruction 3 - TLB access due to
2232 instruction fetch or instruction
2233 prefetch 4 - TLB access due to data
2234 prefetch (both hardware and software)
2235 5 - TLB shoot down access 6 - TLB
2236 probe instruction (probe, tpa) 7 -
2237 move in (VHPT fill) 8 - purge (insert
2238 operation that purges entries or a TLB
2239 purge instruction) All other values
2240 are reserved.
2241
2242 @param InstructionSet Bit54, Instruction set. If this value
2243 is set to zero, the instruction that
2244 generated the machine check was an
2245 Intel Itanium instruction. If this bit
2246 is set to one, the instruction that
2247 generated the machine check was IA-32
2248 instruction.
2249
2250 @param InstructionSetIsValid Bit55, The is field in the
2251 TLB_check parameter is valid.
2252
2253 @param PrivelegeLevel Bit57:56, Privilege level. The
2254 privilege level of the instruction
2255 bundle responsible for generating the
2256 machine check.
2257
2258 @param PrivelegeLevelIsValid Bit58, The pl field of the
2259 TLB_check parameter is valid.
2260
2261 @param McCorrected Bit59, Machine check corrected: This bit
2262 is set to one to indicate that the machine
2263 check has been corrected.
2264
2265 @param TargetAddressIsValid Bit60, Target address is valid:
2266 This bit is set to one to
2267 indicate that a valid target
2268 address has been logged.
2269
2270 @param RequesterIdentifier Bit61 Requester identifier: This
2271 bit is set to one to indicate that
2272 a valid requester identifier has
2273 been logged.
2274
2275 @param ResponserIdentifier Bit62, Responder identifier: This
2276 bit is set to one to indicate that
2277 a valid responder identifier has
2278 been logged.
2279
2280 @param PreciseInsPointer Bit63 Precise instruction pointer.
2281 This bit is set to one to indicate
2282 that a valid precise instruction
2283 pointer has been logged.
2284 **/
2285 typedef struct {
2286 UINT64 FailedSlot:8;
2287 UINT64 FailedSlotIsValid:1;
2288 UINT64 Reserved1 :1;
2289 UINT64 TlbLevel:2;
2290 UINT64 Reserved2 :4;
2291 UINT64 FailedInDataTr:1;
2292 UINT64 FailedInInsTr:1;
2293 UINT64 FailedInDataTc:1;
2294 UINT64 FailedInInsTc:1;
2295 UINT64 FailedOperation:4;
2296 UINT64 Reserved3:30;
2297 UINT64 InstructionSet:1;
2298 UINT64 InstructionSetIsValid:1;
2299 UINT64 PrivelegeLevel:2;
2300 UINT64 PrivelegeLevelIsValid:1;
2301 UINT64 McCorrected:1;
2302 UINT64 TargetAddressIsValid:1;
2303 UINT64 RequesterIdentifier:1;
2304 UINT64 ResponserIdentifier:1;
2305 UINT64 PreciseInsPointer:1;
2306 } PAL_TLB_CHECK_INFO;
2307
2308 /**
2309
2310 PAL Procedure - PAL_MC_ERROR_INFO.
2311
2312 Return Processor Machine Check Information and Processor
2313 Static State for logging by SAL. It is required by IPF. The
2314 PAL procedure supports the Static Registers calling
2315 convention. It could be called at physical and virtual mode.
2316
2317 @param Index Index of PAL_MC_ERROR_INFO within the list of PAL
2318 procedures.
2319
2320 @param InfoIndex Unsigned 64-bit integer identifying the
2321 error information that is being requested.
2322 See PAL_MC_ERROR_INFO.InfoIndex.
2323
2324 @param LevelIndex 8-byte formatted value identifying the
2325 structure to return error information
2326 on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.
2327
2328 @param ErrorTypeIndex Unsigned 64-bit integer denoting the
2329 type of error information that is
2330 being requested for the structure
2331 identified in LevelIndex.
2332
2333
2334 @return R9 Error information returned. The format of this
2335 value is dependant on the input values passed.
2336
2337 @return R10 If this value is zero, all the error information
2338 specified by err_type_index has been returned. If
2339 this value is one, more structure-specific error
2340 information is available and the caller needs to
2341 make this procedure call again with level_index
2342 unchanged and err_type_index, incremented.
2343
2344
2345 @return Status 0 - Call completed without error
2346
2347 @return Status -2 - Invalid argument
2348
2349 @return Status -3 - Call completed with error.
2350
2351 @return Status -6 - Argument was valid, but no error
2352 information was available
2353
2354
2355 **/
2356 #define PAL_MC_ERROR_INFO 25
2357
2358 /**
2359
2360 PAL Procedure - PAL_MC_EXPECTED.
2361
2362 Set/Reset Expected Machine Check Indicator. It is required by
2363 IPF. The PAL procedure supports the Static Registers calling
2364 convention. It could be called at physical mode.
2365
2366 @param Index Index of PAL_MC_EXPECTED within the list of PAL
2367 procedures.
2368
2369 @param Expected Unsigned integer with a value of 0 or 1 to
2370 set or reset the hardware resource
2371 PALE_CHECK examines for expected machine
2372 checks.
2373
2374
2375 @return R9 Unsigned integer denoting whether a machine check
2376 was previously expected.
2377
2378
2379 @return Status 0 - Call completed without error
2380
2381 @return Status -2 - Invalid argument
2382
2383 @return Status -3 - Call completed with error.
2384
2385 **/
2386 #define PAL_MC_EXPECTED 23
2387
2388 /**
2389
2390 PAL Procedure - PAL_MC_REGISTER_MEM.
2391
2392 Register min-state save area with PAL for machine checks and
2393 inits. It is required by IPF. The PAL procedure supports the
2394 Static Registers calling convention. It could be called at
2395 physical mode.
2396
2397 @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL
2398 procedures.
2399
2400 @param Address Physical address of the buffer to be
2401 registered with PAL.
2402
2403
2404
2405 @return Status 0 - Call completed without error
2406
2407 @return Status -2 - Invalid argument
2408
2409 @return Status -3 - Call completed with error.
2410
2411 **/
2412 #define PAL_MC_REGISTER_MEM 27
2413
2414 /**
2415
2416 PAL Procedure - PAL_MC_RESUME.
2417
2418 Restore minimal architected state and return to interrupted
2419 process. It is required by IPF. The PAL procedure supports the
2420 Static Registers calling convention. It could be called at
2421 physical mode.
2422
2423 @param Index Index of PAL_MC_RESUME within the list of PAL
2424 procedures.
2425
2426 @param SetCmci Unsigned 64 bit integer denoting whether to
2427 set the CMC interrupt. A value of 0 indicates
2428 not to set the interrupt, a value of 1
2429 indicated to set the interrupt, and all other
2430 values are reserved.
2431
2432 @param SavePtr Physical address of min-state save area used
2433 to used to restore processor state.
2434
2435 @param NewContext Unsigned 64-bit integer denoting whether
2436 the caller is returning to a new context.
2437 A value of 0 indicates the caller is
2438 returning to the interrupted context, a
2439 value of 1 indicates that the caller is
2440 returning to a new context.
2441
2442
2443
2444 @return Status -2 - Invalid argument
2445
2446 @return Status -3 - Call completed with error.
2447
2448 **/
2449 #define PAL_MC_RESUME 26
2450
2451 /**
2452
2453 PAL Procedure - PAL_HALT.
2454
2455 Enter the low-power HALT state or an implementation-dependent
2456 low-power state. It is optinal. The PAL procedure supports the
2457 Static Registers calling convention. It could be called at
2458 physical mode.
2459
2460 @param Index Index of PAL_HALT within the list of PAL
2461 procedures.
2462
2463 @param HaltState Unsigned 64-bit integer denoting low power
2464 state requested.
2465
2466 @param IoDetailPtr 8-byte aligned physical address pointer to
2467 information on the type of I/O
2468 (load/store) requested.
2469
2470
2471 @return R9 Value returned if a load instruction is requested
2472 in the io_detail_ptr
2473
2474
2475 @return Status 0 - Call completed without error
2476
2477 @return Status -1 - Unimplemented procedure
2478
2479 @return Status -2 - Invalid argument
2480
2481 @return Status -3 - Call completed with error.
2482
2483 **/
2484 #define PAL_HALT 28
2485
2486
2487 /**
2488
2489 PAL Procedure - PAL_HALT_INFO.
2490
2491 Return the low power capabilities of the processor. It is
2492 required by IPF. The PAL procedure supports the
2493 Stacked Registers calling convention. It could be called at
2494 physical and virtual mode.
2495
2496 @param Index Index of PAL_HALT_INFO within the list of PAL
2497 procedures.
2498
2499 @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned
2500 on an 8-byte boundary.
2501
2502
2503
2504 @return Status 0 - Call completed without error
2505
2506 @return Status -2 - Invalid argument
2507
2508 @return Status -3 - Call completed with error.
2509
2510 **/
2511 #define PAL_HALT_INFO 257
2512
2513
2514 /**
2515
2516 PAL Procedure - PAL_HALT_LIGHT.
2517
2518 Enter the low power LIGHT HALT state. It is required by
2519 IPF. The PAL procedure supports the Static Registers calling
2520 convention. It could be called at physical and virtual mode.
2521
2522 @param Index Index of PAL_HALT_LIGHT within the list of PAL
2523 procedures.
2524
2525
2526 @return Status 0 - Call completed without error
2527
2528 @return Status -2 - Invalid argument
2529
2530 @return Status -3 - Call completed with error.
2531
2532 **/
2533 #define PAL_HALT_LIGHT 29
2534
2535 /**
2536
2537 PAL Procedure - PAL_CACHE_LINE_INIT.
2538
2539 Initialize tags and data of a cache line for processor
2540 testing. It is required by IPF. The PAL procedure supports the
2541 Static Registers calling convention. It could be called at
2542 physical and virtual mode.
2543
2544 @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL
2545 procedures.
2546
2547 @param Address Unsigned 64-bit integer value denoting the
2548 physical address from which the physical page
2549 number is to be generated. The address must be
2550 an implemented physical address, bit 63 must
2551 be zero.
2552
2553 @param DataValue 64-bit data value which is used to
2554 initialize the cache line.
2555
2556
2557 @return Status 0 - Call completed without error
2558
2559 @return Status -2 - Invalid argument
2560
2561 @return Status -3 - Call completed with error.
2562
2563 **/
2564 #define PAL_CACHE_LINE_INIT 31
2565
2566 /**
2567
2568 PAL Procedure - PAL_CACHE_READ.
2569
2570 Read tag and data of a cache line for diagnostic testing. It
2571 is optional. The PAL procedure supports the
2572 Satcked Registers calling convention. It could be called at
2573 physical mode.
2574
2575 @param Index Index of PAL_CACHE_READ within the list of PAL
2576 procedures.
2577
2578 @param LineId 8-byte formatted value describing where in the
2579 cache to read the data.
2580
2581 @param Address 64-bit 8-byte aligned physical address from
2582 which to read the data. The address must be an
2583 implemented physical address on the processor
2584 model with bit 63 set to zero.
2585
2586 @return R9 Right-justified value returned from the cache
2587 line.
2588
2589 @return R10 The number of bits returned in data.
2590
2591 @return R11 The status of the cache line.
2592
2593
2594
2595 @return Status 1 - The word at address was found in the
2596 cache, but the line was invalid.
2597
2598 @return Status 0 - Call completed without error
2599
2600 @return Status -2 - Invalid argument
2601
2602 @return Status -3 - Call completed with error.
2603
2604 @return Status -5 - The word at address was not found in the
2605 cache.
2606
2607 @return Status -7 - The operation requested is not supported
2608 for this cache_type and level.
2609
2610 **/
2611 #define PAL_CACHE_READ 259
2612
2613
2614 /**
2615
2616 Write tag and data of a cache for diagnostic testing. It is
2617 optional. The PAL procedure supports the Satcked Registers
2618 calling convention. It could be called at physical mode.
2619
2620 @param Index Index of PAL_CACHE_WRITE within the list of PAL
2621 procedures.
2622
2623 @param LineId 8-byte formatted value describing where in the
2624 cache to write the data.
2625
2626 @param Address 64-bit 8-byte aligned physical address at
2627 which the data should be written. The address
2628 must be an implemented physical address on the
2629 processor model with bit 63 set to 0.
2630
2631 @param Data Unsigned 64-bit integer value to write into
2632 the specified part of the cache.
2633
2634
2635 @return Status 0 - Call completed without error
2636
2637 @return Status -2 - Invalid argument
2638
2639 @return Status -3 - Call completed with error.
2640
2641
2642 @return Status -7 - The operation requested is not supported
2643 for this cache_type and level.
2644
2645 **/
2646 #define PAL_CACHE_WRITE 260
2647
2648 /**
2649
2650 PAL Procedure - PAL_TEST_INFO.
2651
2652 Returns alignment and size requirements needed for the memory
2653 buffer passed to the PAL_TEST_PROC procedure as well as
2654 information on self-test control words for the processor self
2655 tests. It is required by IPF. The PAL procedure supports the
2656 Static Registers calling convention. It could be called at
2657 physical mode.
2658
2659 @param Index Index of PAL_TEST_INFO within the list of PAL
2660 procedures.
2661
2662 @param TestPhase Unsigned integer that specifies which phase
2663 of the processor self-test information is
2664 being requested on. A value of 0 indicates
2665 the phase two of the processor self-test and
2666 a value of 1 indicates phase one of the
2667 processor self-test. All other values are
2668 reserved.
2669
2670 @return R9 Unsigned 64-bit integer denoting the number of
2671 bytes of main memory needed to perform the second
2672 phase of processor self-test.
2673
2674 @return R10 Unsigned 64-bit integer denoting the alignment
2675 required for the memory buffer.
2676
2677 @return R11 48-bit wide bit-field indicating if control of
2678 the processor self-tests is supported and which
2679 bits of the test_control field are defined for
2680 use.
2681
2682
2683 @return Status 0 - Call completed without error
2684
2685 @return Status -2 - Invalid argument
2686
2687 @return Status -3 - Call completed with error.
2688
2689
2690 **/
2691 #define PAL_TEST_INFO 37
2692
2693 /**
2694
2695 @param BufferSize Indicates the size in bytes of the memory
2696 buffer that is passed to this procedure.
2697 BufferSize must be greater than or equal in
2698 size to the bytes_needed return value from
2699 PAL_TEST_INFO, otherwise this procedure will
2700 return with an invalid argument return
2701 value.
2702
2703 @param TestPhase Defines which phase of the processor
2704 self-tests are requested to be run. A value
2705 of zero indicates to run phase two of the
2706 processor self-tests. Phase two of the
2707 processor self-tests are ones that require
2708 external memory to execute correctly. A
2709 value of one indicates to run phase one of
2710 the processor self-tests. Phase one of the
2711 processor self-tests are tests run during
2712 PALE_RESET and do not depend on external
2713 memory to run correctly. When the caller
2714 requests to have phase one of the processor
2715 self-test run via this procedure call, a
2716 memory buffer may be needed to save and
2717 restore state as required by the PAL calling
2718 conventions. The procedure PAL_TEST_INFO
2719 informs the caller about the requirements of
2720 the memory buffer.
2721
2722 **/
2723 typedef struct {
2724 UINT64 BufferSize:56;
2725 UINT64 TestPhase:8;
2726 } PAL_TEST_INFO_INFO;
2727
2728 /**
2729
2730 @param TestControl This is an ordered implementation-specific
2731 control word that allows the user control
2732 over the length and runtime of the
2733 processor self-tests. This control word is
2734 ordered from the longest running tests up
2735 to the shortest running tests with bit 0
2736 controlling the longest running test. PAL
2737 may not implement all 47-bits of the
2738 test_control word. PAL communicates if a
2739 bit provides control by placing a zero in
2740 that bit. If a bit provides no control,
2741 PAL will place a one in it. PAL will have
2742 two sets of test_control bits for the two
2743 phases of the processor self-test. PAL
2744 provides information about implemented
2745 test_control bits at the hand-off from PAL
2746 to SAL for the firmware recovery check.
2747 These test_control bits provide control
2748 for phase one of processor self-test. It
2749 also provides this information via the PAL
2750 procedure call PAL_TEST_INFO for both the
2751 phase one and phase two processor tests
2752 depending on which information the caller
2753 is requesting. PAL interprets these bits
2754 as input parameters on two occasions. The
2755 first time is when SAL passes control back
2756 to PAL after the firmware recovery check.
2757 The second time is when a call to
2758 PAL_TEST_PROC is made. When PAL interprets
2759 these bits it will only interpret
2760 implemented test_control bits and will
2761 ignore the values located in the
2762 unimplemented test_control bits. PAL
2763 interprets the implemented bits such that
2764 if a bit contains a zero, this indicates
2765 to run the test. If a bit contains a one,
2766 this indicates to PAL to skip the test. If
2767 the cs bit indicates that control is not
2768 available, the test_control bits will be
2769 ignored or generate an illegal argument in
2770 procedure calls if the caller sets these
2771 bits.
2772
2773 @param ControlSupport This bit defines if an implementation
2774 supports control of the PAL self-tests
2775 via the self-test control word. If
2776 this bit is 0, the implementation does
2777 not support control of the processor
2778 self-tests via the self-test control
2779 word. If this bit is 1, the
2780 implementation does support control of
2781 the processor self-tests via the
2782 self-test control word. If control is
2783 not supported, GR37 will be ignored at
2784 the hand-off between SAL and PAL after
2785 the firmware recovery check and the
2786 PAL procedures related to the
2787 processor self-tests may return
2788 illegal arguments if a user tries to
2789 use the self-test control features.
2790
2791 **/
2792 typedef struct {
2793 UINT64 TestControl:47;
2794 UINT64 ControlSupport:1;
2795 UINT64 Reserved:16;
2796 } PAL_SELF_TEST_CONTROL;
2797
2798 /**
2799
2800 @param Attributes Specifies the memory attributes that are
2801 allowed to be used with the memory buffer
2802 passed to this procedure. The attributes
2803 parameter is a vector where each bit
2804 represents one of the virtual memory
2805 attributes defined by the architecture.See
2806 MEMORY_AATRIBUTES. The caller is required
2807 to support the cacheable attribute for the
2808 memory buffer, otherwise an invalid
2809 argument will be returned.
2810
2811
2812 @param TestControl Is the self-test control word
2813 corresponding to the test_phase passed.
2814 This test_control directs the coverage and
2815 runtime of the processor self-tests
2816 specified by the test_phase input
2817 argument. Information on if this
2818 feature is implemented and the number of
2819 bits supported can be obtained by the
2820 PAL_TEST_INFO procedure call. If this
2821 feature is implemented by the processor,
2822 the caller can selectively skip parts of
2823 the processor self-test by setting
2824 test_control bits to a one. If a bit has a
2825 zero, this test will be run. The values in
2826 the unimplemented bits are ignored. If
2827 PAL_TEST_INFO indicated that the self-test
2828 control word is not implemented, this
2829 procedure will return with an invalid
2830 argument status if the caller sets any of
2831 the test_control bits. See
2832 PAL_SELF_TEST_CONTROL.
2833 **/
2834 typedef struct {
2835 UINT64 Attributes:8;
2836 UINT64 Reserved:8;
2837 UINT64 TestControl:48;
2838 } PAL_TEST_CONTROL;
2839
2840 /**
2841
2842 PAL Procedure - PAL_TEST_PROC.
2843
2844 Perform late processor self test. It is required by IPF. The
2845 PAL procedure supports the Static Registers calling
2846 convention. It could be called at physical mode.
2847
2848 @param Index Index of PAL_TEST_PROC within the list of PAL
2849 procedures.
2850
2851 @param TestAddress 64-bit physical address of main memory
2852 area to be used by processor self-test.
2853 The memory region passed must be
2854 cacheable, bit 63 must be zero.
2855
2856 @param TestInfo Input argument specifying the size of the
2857 memory buffer passed and the phase of the
2858 processor self-test that should be run. See
2859 PAL_TEST_INFO.
2860
2861 @param TestParam Input argument specifying the self-test
2862 control word and the allowable memory
2863 attributes that can be used with the memory
2864 buffer. See PAL_TEST_CONTROL.
2865
2866 @return R9 Formatted 8-byte value denoting the state of the
2867 processor after self-test
2868
2869
2870
2871 @return Status 1 - Call completed without error, but hardware
2872 failures occurred during self-test.
2873
2874 @return Status 0 - Call completed without error
2875
2876 @return Status -2 - Invalid argument
2877
2878 @return Status -3 - Call completed with error.
2879
2880
2881 **/
2882 #define PAL_TEST_PROC 258
2883
2884 /**
2885
2886 @param NumberOfInterruptControllers Number of interrupt
2887 controllers currently
2888 enabled on the system.
2889
2890 @param NumberOfProcessors Number of processors currently
2891 enabled on the system.
2892
2893 **/
2894 typedef struct {
2895 UINT32 NumberOfInterruptControllers;
2896 UINT32 NumberOfProcessors;
2897 } PAL_PLATFORM_INFO;
2898
2899 /**
2900
2901 PAL Procedure - PAL_COPY_INFO.
2902
2903 Return information needed to relocate PAL procedures and PAL
2904 PMI code to memory. It is required by IPF. The PAL procedure
2905 supports the Static Registers calling convention. It could be
2906 called at physical mode.
2907
2908 @param Index Index of PAL_COPY_INFO within the list of PAL
2909 procedures.
2910
2911 @param CopyType Unsigned integer denoting type of procedures
2912 for which copy information is requested.
2913
2914 @param PlatformInfo 8-byte formatted value describing the
2915 number of processors and the number of
2916 interrupt controllers currently enabled
2917 on the system. See PAL_PLATFORM_INFO.
2918
2919
2920 @param McaProcStateInfo Unsigned integer denoting the number
2921 of bytes that SAL needs for the
2922 min-state save area for each
2923 processor.
2924
2925
2926
2927 @return R9 Unsigned integer denoting the number of bytes of
2928 PAL information that must be copied to main
2929 memory.
2930
2931 @return R10 Unsigned integer denoting the starting alignment
2932 of the data to be copied.
2933
2934 @return Status 0 - Call completed without error
2935
2936 @return Status -2 - Invalid argument
2937
2938 @return Status -3 - Call completed with error.
2939
2940
2941 **/
2942 #define PAL_COPY_INFO 30
2943
2944 /**
2945
2946 PAL Procedure - PAL_COPY_PAL.
2947
2948 Relocate PAL procedures and PAL PMI code to memory. It is
2949 required by IPF. The PAL procedure supports the Stacked
2950 Registers calling convention. It could be called at physical
2951 mode.
2952
2953 @param Index Index of PAL_COPY_PAL within the list of PAL
2954 procedures.
2955
2956 @param TargetAddress Physical address of a memory buffer to
2957 copy relocatable PAL procedures and PAL
2958 PMI code.
2959
2960 @param AllocSize Unsigned integer denoting the size of the
2961 buffer passed by SAL for the copy operation.
2962
2963
2964 @param CopyOption Unsigned integer indicating whether
2965 relocatable PAL code and PAL PMI code
2966 should be copied from firmware address
2967 space to main memory.
2968
2969
2970 @return R9 Unsigned integer denoting the offset of PAL_PROC
2971 in the relocatable segment copied.
2972
2973 @return Status 0 - Call completed without error
2974
2975 @return Status -2 - Invalid argument
2976
2977 @return Status -3 - Call completed with error.
2978
2979
2980 **/
2981 #define PAL_COPY_PAL 256
2982
2983 /**
2984
2985 PAL Procedure - PAL_ENTER_IA_32_ENV.
2986
2987 Enter IA-32 System environment. It is optional. The PAL
2988 procedure supports the Static Registers calling convention.
2989 It could be called at physical mode.
2990
2991 Note: Since this is a special call, it does not follow the PAL
2992 static register calling convention. GR28 contains the index of
2993 PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other
2994 input arguments including GR29-GR31 are setup by SAL to values
2995 as required by the IA-32 operating system defined in Table
2996 11-67. The registers that are designated as preserved, scratch,
2997 input arguments and procedure return values by the static
2998 procedure calling convention are not followed by this call. For
2999 instance, GR5 and GR6 need not be preserved since these are
3000 regarded as scratch by the IA-32 operating system. Note: In an
3001 MP system, this call must be COMPLETED on the first CPU to enter
3002 the IA-32 System Environment (may or may not be the BSP) prior
3003 to being called on the remaining processors in the MP system.
3004
3005 @param Index GR28 contains the index of the
3006 PAL_ENTER_IA_32_ENV call within the list of PAL
3007 procedures.
3008
3009
3010 @return Status The status is returned in GR4.
3011 -1 - Un-implemented procedure 0 JMPE detected
3012 at privilege level
3013
3014 0 - 1 SAL allocated buffer for IA-32 System
3015 Environment operation is too small
3016
3017 2 - IA-32 Firmware Checksum Error
3018
3019 3 - SAL allocated buffer for IA-32 System
3020 Environment operation is not properly aligned
3021
3022 4 - Error in SAL MP Info Table
3023
3024 5 - Error in SAL Memory Descriptor Table
3025
3026 6 - Error in SAL System Table
3027
3028 7 - Inconsistent IA-32 state
3029
3030 8 - IA-32 Firmware Internal Error
3031
3032 9 - IA-32 Soft Reset (Note: remaining register
3033 state is undefined for this termination
3034 reason)
3035
3036 10 - Machine Check Error
3037
3038 11 - Error in SAL I/O Intercept Table
3039
3040 12 - Processor exit due to other processor in
3041 MP system terminating the IA32 system
3042 environment. (Note: remaining register state
3043 is undefined for this termination reason.)
3044
3045 13 - Itanium architecture-based state
3046 corruption by either SAL PMI handler or I/O
3047 Intercept callback function.
3048
3049
3050 **/
3051 #define PAL_ENTER_IA_32_ENV 33
3052
3053 /**
3054
3055 PAL Procedure - PAL_PMI_ENTRYPOINT.
3056
3057 Register PMI memory entrypoints with processor. It is required
3058 by IPF. The PAL procedure supports the Stacked Registers
3059 calling convention. It could be called at physical mode.
3060
3061 @param Index Index of PAL_PMI_ENTRYPOINT within the list of
3062 PAL procedures.
3063
3064 @param SalPmiEntry 256-byte aligned physical address of SAL
3065 PMI entrypoint in memory.
3066
3067
3068 @return Status 0 - Call completed without error
3069
3070 @return Status -2 - Invalid argument
3071
3072 @return Status -3 - Call completed with error.
3073
3074
3075 **/
3076 #define PAL_PMI_ENTRYPOINT 32
3077
3078
3079 /**
3080
3081 The ASCII brand identification string will be copied to the
3082 address specified in the address input argument. The processor
3083 brand identification string is defined to be a maximum of 128
3084 characters long; 127 bytes will contain characters and the 128th
3085 byte is defined to be NULL (0). A processor may return less than
3086 the 127 ASCII characters as long as the string is null
3087 terminated. The string length will be placed in the brand_info
3088 return argument.
3089
3090 **/
3091 #define PAL_BRAND_INFO_ID_REQUEST 0
3092
3093 /**
3094
3095 PAL Procedure - PAL_BRAND_INFO.
3096
3097 Provides processor branding information. It is optional by
3098 IPF. The PAL procedure supports the Stacked Registers calling
3099 convention. It could be called at physical and Virtual mode.
3100
3101
3102 @param Index Index of PAL_BRAND_INFO within the list of PAL
3103 procedures.
3104
3105 @param InfoRequest Unsigned 64-bit integer specifying the
3106 information that is being requested. (See
3107 PAL_BRAND_INFO_ID_REQUEST)
3108
3109 @param Address Unsigned 64-bit integer specifying the
3110 address of the 128-byte block to which the
3111 processor brand string shall be written.
3112
3113
3114 @reture R9 Brand information returned. The format of this
3115 value is dependent on the input values passed.
3116
3117
3118 @return Status 0 - Call completed without error
3119
3120 @return Status -1 - Unimplemented procedure
3121
3122 @return Status -2 - Invalid argument
3123
3124 @return Status -3 - Call completed with error.
3125
3126 @return Status -6 - Input argument is not implemented.
3127
3128 **/
3129 #define PAL_BRAND_INFO 274
3130
3131 /**
3132
3133 PAL Procedure - PAL_GET_HW_POLICY.
3134
3135 Returns the current hardware resource sharing policy of the
3136 processor. It is optional by IPF. The PAL procedure supports
3137 the Static Registers calling convention. It could be called at
3138 physical and Virtual mode.
3139
3140
3141 @param Index Index of PAL_GET_HW_POLICY within the list of PAL
3142 procedures.
3143
3144 @param ProcessorNumber Unsigned 64-bit integer that specifies
3145 for which logical processor
3146 information is being requested. This
3147 input argument must be zero for the
3148 first call to this procedure and can
3149 be a maximum value of one less than
3150 the number of logical processors
3151 impacted by the hardware resource
3152 sharing policy, which is returned by
3153 the R10 return value.
3154
3155
3156 @reture R9 Unsigned 64-bit integer representing the current
3157 hardware resource sharing policy.
3158
3159 @return R10 Unsigned 64-bit integer that returns the number
3160 of logical processors impacted by the policy
3161 input argument.
3162
3163 @return R11 Unsigned 64-bit integer containing the logical
3164 address of one of the logical processors
3165 impacted by policy modification.
3166
3167
3168 @return Status 0 - Call completed without error
3169
3170 @return Status -1 - Unimplemented procedure
3171
3172 @return Status -2 - Invalid argument
3173
3174 @return Status -3 - Call completed with error.
3175
3176 @return Status -9 - Call requires PAL memory buffer.
3177
3178 **/
3179 #define PAL_GET_HW_POLICY 48
3180
3181
3182 //
3183 // Value of PAL_SET_HW_POLICY.Policy
3184 //
3185 #define PAL_SET_HW_POLICY_PERFORMANCE 0
3186 #define PAL_SET_HW_POLICY_FAIRNESS 1
3187 #define PAL_SET_HW_POLICY_HIGH_PRIORITY 2
3188 #define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3
3189
3190 /**
3191
3192 PAL Procedure - PAL_SET_HW_POLICY.
3193
3194 Sets the current hardware resource sharing policy of the
3195 processor. It is optional by IPF. The PAL procedure supports
3196 the Static Registers calling convention. It could be called at
3197 physical and Virtual mode.
3198
3199
3200 @param Index Index of PAL_SET_HW_POLICY within the list of PAL
3201 procedures.
3202
3203 @param Policy Unsigned 64-bit integer specifying the hardware
3204 resource sharing policy the caller is setting.
3205 See Value of PAL_SET_HW_POLICY.Policy above.
3206
3207
3208 @return Status 1 - Call completed successfully but could not
3209 change the hardware policy since a
3210 competing logical processor is set in
3211 exclusive high priority.
3212
3213 @return Status 0 - Call completed without error
3214
3215 @return Status -1 - Unimplemented procedure
3216
3217 @return Status -2 - Invalid argument
3218
3219 @return Status -3 - Call completed with error.
3220
3221 @return Status -9 - Call requires PAL memory buffer.
3222
3223 **/
3224 #define PAL_SET_HW_POLICY 49
3225
3226
3227 /**
3228
3229 @param Mode Bit2:0, Indicates the mode of operation for this
3230 procedure: 0 - Query mode 1 ¨C Error inject mode
3231 (err_inj should also be specified) 2 - Cancel
3232 outstanding trigger. All other fields in
3233 PAL_MC_ERROR_TYPE_INFO,
3234 PAL_MC_ERROR_STRUCTURE_INFO and
3235 PAL_MC_ERROR_DATA_BUFFER are ignored. All other
3236 values are reserved.
3237
3238 @param ErrorInjection Bit5:3, indicates the mode of error
3239 injection: 0 - Error inject only (no
3240 error consumption) 1 - Error inject
3241 and consume All other values are
3242 reserved.
3243
3244
3245 @param ErrorSeverity Bit7:6, indicates the severity desired
3246 for error injection/query. Definitions
3247 of the different error severity types
3248 0 - Corrected error 1 - Recoverable
3249 error 2 - Fatal error 3 - Reserved
3250
3251
3252 @param ErrorStructure Bit12:8, Indicates the structure
3253 identification for error
3254 injection/query: 0 - Any structure
3255 (cannot be used during query mode).
3256 When selected, the structure type used
3257 for error injection is determined by
3258 PAL. 1 - Cache 2 - TLB 3 - Register
3259 file 4 - Bus/System interconnect 5-15
3260 - Reserved 16-31 - Processor
3261 specific error injection
3262 capabilities.ErrorDataBuffer is used
3263 to specify error types. Please refer
3264 to the processor specific
3265 documentation for additional details.
3266
3267 @param StructureHierarchy Bit15:13, Indicates the structure
3268 hierarchy for error
3269 injection/query: 0 - Any level of
3270 hierarchy (cannot be used during
3271 query mode). When selected, the
3272 structure hierarchy used for error
3273 injection is determined by PAL. 1
3274 - Error structure hierarchy
3275 level-1 2 - Error structure
3276 hierarchy level-2 3 - Error
3277 structure hierarchy level-3 4 -
3278 Error structure hierarchy level-4
3279 All other values are reserved.
3280 Reserved 63:16 Reserved
3281
3282 **/
3283 typedef struct {
3284 UINT64 Mode:3;
3285 UINT64 ErrorInjection:3;
3286 UINT64 ErrorSeverity:2;
3287 UINT64 ErrorStructure:5;
3288 UINT64 StructureHierarchy:3;
3289 UINT64 Reserved:48;
3290 } PAL_MC_ERROR_TYPE_INFO;
3291
3292 /**
3293
3294 @param StructInfoIsValid Bit0 When 1, indicates that the
3295 structure information fields
3296 (c_t,cl_p,cl_id) are valid and
3297 should be used for error injection.
3298 When 0, the structure information
3299 fields are ignored, and the values
3300 of these fields used for error
3301 injection are
3302 implementation-specific.
3303
3304 @param CacheType Bit2:1 Indicates which cache should be used
3305 for error injection: 0 - Reserved 1 -
3306 Instruction cache 2 - Data or unified cache
3307 3 - Reserved
3308
3309
3310 @param PortionOfCacheLine Bit5:3 Indicates the portion of the
3311 cache line where the error should
3312 be injected: 0 - Reserved 1 - Tag
3313 2 - Data 3 - mesi All other
3314 values are reserved.
3315
3316 @param Mechanism Bit8:6 Indicates which mechanism is used to
3317 identify the cache line to be used for error
3318 injection: 0 - Reserved 1 - Virtual address
3319 provided in the inj_addr field of the buffer
3320 pointed to by err_data_buffer should be used
3321 to identify the cache line for error
3322 injection. 2 - Physical address provided in
3323 the inj_addr field of the buffer pointed to
3324 by err_data_buffershould be used to identify
3325 the cache line for error injection. 3 - way
3326 and index fields provided in err_data_buffer
3327 should be used to identify the cache line
3328 for error injection. All other values are
3329 reserved.
3330
3331 @param DataPoisonOfCacheLine Bit9 When 1, indicates that a
3332 multiple bit, non-correctable
3333 error should be injected in the
3334 cache line specified by cl_id.
3335 If this injected error is not
3336 consumed, it may eventually
3337 cause a data-poisoning event
3338 resulting in a corrected error
3339 signal, when the associated
3340 cache line is cast out (implicit
3341 or explicit write-back of the
3342 cache line). The error severity
3343 specified by err_sev in
3344 err_type_info must be set to 0
3345 (corrected error) when this bit
3346 is set.
3347
3348
3349 @param TrigerInfoIsValid Bit32 When 1, indicates that the
3350 trigger information fields (trigger,
3351 trigger_pl) are valid and should be
3352 used for error injection. When 0,
3353 the trigger information fields are
3354 ignored and error injection is
3355 performed immediately.
3356
3357 @param Triger Bit36:33 Indicates the operation type to be
3358 used as the error trigger condition. The
3359 address corresponding to the trigger is
3360 specified in the trigger_addr field of the
3361 buffer pointed to by err_data_buffer: 0 -
3362 Instruction memory access. The trigger match
3363 conditions for this operation type are similar
3364 to the IBR address breakpoint match conditions
3365 1 - Data memory access. The trigger match
3366 conditions for this operation type are similar
3367 to the DBR address breakpoint match conditions
3368 All other values are reserved.
3369
3370 @param PrivilegeOfTriger Bit39:37 Indicates the privilege
3371 level of the context during which
3372 the error should be injected: 0 -
3373 privilege level 0 1 - privilege
3374 level 1 2 - privilege level 2 3 -
3375 privilege level 3 All other values
3376 are reserved. If the implementation
3377 does not support privilege level
3378 qualifier for triggers (i.e. if
3379 trigger_pl is 0 in the capabilities
3380 vector), this field is ignored and
3381 triggers can be taken at any
3382 privilege level.
3383
3384 **/
3385 typedef struct {
3386 UINT64 StructInfoIsValid:1;
3387 UINT64 CacheType:2;
3388 UINT64 PortionOfCacheLine:3;
3389 UINT64 Mechanism:3;
3390 UINT64 DataPoisonOfCacheLine:1;
3391 UINT64 Reserved1:22;
3392 UINT64 TrigerInfoIsValid:1;
3393 UINT64 Triger:4;
3394 UINT64 PrivilegeOfTriger:3;
3395 UINT64 Reserved2:24;
3396 } PAL_MC_ERROR_STRUCT_INFO;
3397
3398 /**
3399
3400 Buffer Pointed to by err_data_buffer ¨C TLB
3401
3402 **/
3403 typedef struct {
3404 UINT64 TrigerAddress;
3405 UINT64 VirtualPageNumber:52;
3406 UINT64 Reserved1:8;
3407 UINT64 RegionId:24;
3408 UINT64 Reserved2:40;
3409 } PAL_MC_ERROR_DATA_BUFFER_TLB;
3410
3411 /**
3412
3413 PAL Procedure - PAL_MC_ERROR_INJECT.
3414
3415 Injects the requested processor error or returns information
3416 on the supported injection capabilities for this particular
3417 processor implementation. It is optional by IPF. The PAL
3418 procedure supports the Stacked Registers calling convention.
3419 It could be called at physical and Virtual mode.
3420
3421
3422 @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL
3423 procedures.
3424
3425 @param ErrorTypeInfo Unsigned 64-bit integer specifying the
3426 first level error information which
3427 identifies the error structure and
3428 corresponding structure hierarchy, and
3429 the error severity.
3430
3431 @param ErrorStructInfo Unsigned 64-bit integer identifying
3432 the optional structure specific
3433 information that provides the second
3434 level details for the requested error.
3435
3436 @param ErrorDataBuffer 64-bit physical address of a buffer
3437 providing additional parameters for
3438 the requested error. The address of
3439 this buffer must be 8-byte aligned.
3440
3441 @return R9 64-bit vector specifying the supported error
3442 injection capabilities for the input argument
3443 combination of struct_hier, err_struct and
3444 err_sev fields in ErrorTypeInfo.
3445
3446 @return R10 64-bit vector specifying the architectural
3447 resources that are used by the procedure.
3448
3449
3450 @return Status 0 - Call completed without error
3451
3452 @return Status -1 - Unimplemented procedure
3453
3454 @return Status -2 - Invalid argument
3455
3456 @return Status -3 - Call completed with error.
3457
3458 @return Status -4 - Call completed with error; the requested
3459 error could not be injected due to failure in
3460 locating the target location in the specified
3461 structure.
3462
3463 @return Status -5 - Argument was valid, but requested error
3464 injection capability is not supported.
3465
3466 @return Status -9 - Call requires PAL memory buffer.
3467
3468 **/
3469 #define PAL_MC_ERROR_INJECT 276
3470
3471
3472 //
3473 // Types of PAL_GET_PSTATE.Type
3474 //
3475 #define PAL_GET_PSTATE_RECENT 0
3476 #define PAL_GET_PSTATE_AVERAGE_NEW_START 1
3477 #define PAL_GET_PSTATE_AVERAGE 2
3478 #define PAL_GET_PSTATE_NOW 3
3479
3480 /**
3481
3482 PAL Procedure - PAL_GET_PSTATE.
3483
3484 Returns the performance index of the processor. It is optional
3485 by IPF. The PAL procedure supports the Stacked Registers
3486 calling convention. It could be called at physical and Virtual
3487 mode.
3488
3489
3490 @param Index Index of PAL_GET_PSTATE within the list of PAL
3491 procedures.
3492
3493 @param Type Type of performance_index value to be returned
3494 by this procedure.See PAL_GET_PSTATE.Type above.
3495
3496
3497 @return R9 Unsigned integer denoting the processor
3498 performance for the time duration since the last
3499 PAL_GET_PSTATE procedure call was made. The
3500 value returned is between 0 and 100, and is
3501 relative to the performance index of the highest
3502 available P-state.
3503
3504 @return Status 1 - Call completed without error, but accuracy
3505 of performance index has been impacted by a
3506 thermal throttling event, or a
3507 hardware-initiated event.
3508
3509 @return Status 0 - Call completed without error
3510
3511 @return Status -1 - Unimplemented procedure
3512
3513 @return Status -2 - Invalid argument
3514
3515 @return Status -3 - Call completed with error.
3516
3517 @return Status -9 - Call requires PAL memory buffer.
3518
3519 **/
3520 #define PAL_GET_PSTATE 262
3521
3522 /**
3523
3524 Layout of PAL_PSTATE_INFO.PStateBuffer
3525
3526 **/
3527 typedef struct {
3528 UINT32 PerformanceIndex:7;
3529 UINT32 Reserved1:5;
3530 UINT32 TypicalPowerDissipation:20;
3531 UINT32 TransitionLatency1;
3532 UINT32 TransitionLatency2;
3533 UINT32 Reserved2;
3534 } PAL_PSTATE_INFO_BUFFER;
3535
3536
3537 /**
3538
3539 PAL Procedure - PAL_PSTATE_INFO.
3540
3541 Returns information about the P-states supported by the
3542 processor. It is optional by IPF. The PAL procedure supports
3543 the Static Registers calling convention. It could be called
3544 at physical and Virtual mode.
3545
3546
3547 @param Index Index of PAL_PSTATE_INFO within the list of PAL
3548 procedures.
3549
3550 @param PStateBuffer 64-bit pointer to a 256-byte buffer
3551 aligned on an 8-byte boundary. See