Omap35xxPkg/Include/Omap3530/Omap3530MMCHS.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __OMAP3530SDIO_H__
  16 #define __OMAP3530SDIO_H__
  17
  18 //MMC/SD/SDIO1 register definitions.
  19 #define MMCHS1BASE        0x4809C000
  20 #define MMC_REFERENCE_CLK (96000000)
  21
  22 #define MMCHS_SYSCONFIG   (MMCHS1BASE + 0x10)
  23 #define SOFTRESET         BIT1
  24 #define ENAWAKEUP         BIT2
  25
  26 #define MMCHS_SYSSTATUS   (MMCHS1BASE + 0x14)
  27 #define RESETDONE_MASK    BIT0
  28 #define RESETDONE         BIT0
  29
  30 #define MMCHS_CSRE        (MMCHS1BASE + 0x24)
  31 #define MMCHS_SYSTEST     (MMCHS1BASE + 0x28)
  32
  33 #define MMCHS_CON         (MMCHS1BASE + 0x2C)
  34 #define OD                BIT0
  35 #define NOINIT            (0x0UL << 1)
  36 #define INIT              BIT1
  37 #define HR                BIT2
  38 #define STR               BIT3
  39 #define MODE              BIT4
  40 #define DW8_1_4_BIT       (0x0UL << 5)
  41 #define DW8_8_BIT         BIT5
  42 #define MIT               BIT6
  43 #define CDP               BIT7
  44 #define WPP               BIT8
  45 #define CTPL              BIT11
  46 #define CEATA_OFF         (0x0UL << 12)
  47 #define CEATA_ON          BIT12
  48
  49 #define MMCHS_PWCNT       (MMCHS1BASE + 0x30)
  50
  51 #define MMCHS_BLK         (MMCHS1BASE + 0x104)
  52 #define BLEN_512BYTES     (0x200UL << 0)
  53
  54 #define MMCHS_ARG         (MMCHS1BASE + 0x108)
  55
  56 #define MMCHS_CMD         (MMCHS1BASE + 0x10C)
  57 #define DE_ENABLE         BIT0
  58 #define BCE_ENABLE        BIT1
  59 #define ACEN_ENABLE       BIT2
  60 #define DDIR_READ         BIT4
  61 #define DDIR_WRITE        (0x0UL << 4)
  62 #define MSBS_SGLEBLK      (0x0UL << 5)
  63 #define MSBS_MULTBLK      BIT5
  64 #define RSP_TYPE_MASK     (0x3UL << 16)
  65 #define RSP_TYPE_136BITS  BIT16
  66 #define RSP_TYPE_48BITS   (0x2UL << 16)
  67 #define CCCE_ENABLE       BIT19
  68 #define CICE_ENABLE       BIT20
  69 #define DP_ENABLE         BIT21
  70 #define INDX(CMD_INDX)    ((CMD_INDX & 0x3F) << 24)
  71
  72 #define MMCHS_RSP10       (MMCHS1BASE + 0x110)
  73 #define MMCHS_RSP32       (MMCHS1BASE + 0x114)
  74 #define MMCHS_RSP54       (MMCHS1BASE + 0x118)
  75 #define MMCHS_RSP76       (MMCHS1BASE + 0x11C)
  76 #define MMCHS_DATA        (MMCHS1BASE + 0x120)
  77
  78 #define MMCHS_PSTATE      (MMCHS1BASE + 0x124)
  79 #define CMDI_MASK         BIT0
  80 #define CMDI_ALLOWED      (0x0UL << 0)
  81 #define CMDI_NOT_ALLOWED  BIT0
  82 #define DATI_MASK         BIT1
  83 #define DATI_ALLOWED      (0x0UL << 1)
  84 #define DATI_NOT_ALLOWED  BIT1
  85
  86 #define MMCHS_HCTL        (MMCHS1BASE + 0x128)
  87 #define DTW_1_BIT         (0x0UL << 1)
  88 #define DTW_4_BIT         BIT1
  89 #define SDBP_MASK         BIT8
  90 #define SDBP_OFF          (0x0UL << 8)
  91 #define SDBP_ON           BIT8
  92 #define SDVS_1_8_V        (0x5UL << 9)
  93 #define SDVS_3_0_V        (0x6UL << 9)
  94 #define IWE               BIT24
  95
  96 #define MMCHS_SYSCTL      (MMCHS1BASE + 0x12C)
  97 #define ICE               BIT0
  98 #define ICS_MASK          BIT1
  99 #define ICS               BIT1
 100 #define CEN               BIT2
 101 #define CLKD_MASK         (0x3FFUL << 6)
 102 #define CLKD_80KHZ        (0x258UL) //(96*1000/80)/2
 103 #define CLKD_400KHZ       (0xF0UL)
 104 #define DTO_MASK          (0xFUL << 16)
 105 #define DTO_VAL           (0xEUL << 16)
 106 #define SRA               BIT24
 107 #define SRC_MASK          BIT25
 108 #define SRC               BIT25
 109 #define SRD               BIT26
 110
 111 #define MMCHS_STAT        (MMCHS1BASE + 0x130)
 112 #define CC                BIT0
 113 #define TC                BIT1
 114 #define BWR               BIT4
 115 #define BRR               BIT5
 116 #define ERRI              BIT15
 117 #define CTO               BIT16
 118 #define DTO               BIT20
 119 #define DCRC              BIT21
 120 #define DEB               BIT22
 121
 122 #define MMCHS_IE          (MMCHS1BASE + 0x134)
 123 #define CC_EN             BIT0
 124 #define TC_EN             BIT1
 125 #define BWR_EN            BIT4
 126 #define BRR_EN            BIT5
 127 #define CTO_EN            BIT16
 128 #define CCRC_EN           BIT17
 129 #define CEB_EN            BIT18
 130 #define CIE_EN            BIT19
 131 #define DTO_EN            BIT20
 132 #define DCRC_EN           BIT21
 133 #define DEB_EN            BIT22
 134 #define CERR_EN           BIT28
 135 #define BADA_EN           BIT29
 136
 137 #define MMCHS_ISE         (MMCHS1BASE + 0x138)
 138 #define CC_SIGEN          BIT0
 139 #define TC_SIGEN          BIT1
 140 #define BWR_SIGEN         BIT4
 141 #define BRR_SIGEN         BIT5
 142 #define CTO_SIGEN         BIT16
 143 #define CCRC_SIGEN        BIT17
 144 #define CEB_SIGEN         BIT18
 145 #define CIE_SIGEN         BIT19
 146 #define DTO_SIGEN         BIT20
 147 #define DCRC_SIGEN        BIT21
 148 #define DEB_SIGEN         BIT22
 149 #define CERR_SIGEN        BIT28
 150 #define BADA_SIGEN        BIT29
 151
 152 #define MMCHS_AC12        (MMCHS1BASE + 0x13C)
 153
 154 #define MMCHS_CAPA        (MMCHS1BASE + 0x140)
 155 #define VS30              BIT25
 156 #define VS18              BIT26
 157
 158 #define MMCHS_CUR_CAPA    (MMCHS1BASE + 0x148)
 159 #define MMCHS_REV         (MMCHS1BASE + 0x1FC)
 160
 161 #define CMD0              INDX(0)
 162 #define CMD0_INT_EN       (CC_EN | CEB_EN)
 163
 164 #define CMD1              (INDX(1) | RSP_TYPE_48BITS)
 165 #define CMD1_INT_EN       (CC_EN | CEB_EN | CTO_EN)
 166
 167 #define CMD2              (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS)
 168 #define CMD2_INT_EN       (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
 169
 170 #define CMD3              (INDX(3) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
 171 #define CMD3_INT_EN       (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
 172
 173 #define CMD5              (INDX(5) | RSP_TYPE_48BITS)
 174 #define CMD5_INT_EN       (CC_EN | CEB_EN | CTO_EN)
 175
 176 #define CMD7              (INDX(7) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
 177 #define CMD7_INT_EN       (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
 178
 179 #define CMD8              (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
 180 #define CMD8_INT_EN       (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
 181 //Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE
 182 #define CMD8_ARG          (0x0UL << 12 | BIT8 | 0xCEUL << 0)
 183
 184 #define CMD9              (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS)
 185 #define CMD9_INT_EN       (CCRC_EN | CC_EN | CEB_EN | CTO_EN)
 186
 187 #define CMD16             (INDX(16) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
 188 #define CMD16_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
 189
 190 #define CMD17             (INDX(17) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_READ)
 191 #define CMD17_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
 192
 193 #define CMD18             (INDX(18) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
 194 #define CMD18_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
 195
 196 #define CMD23             (INDX(23) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
 197 #define CMD23_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
 198
 199 #define CMD24             (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE)
 200 #define CMD24_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
 201
 202 #define CMD55             (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
 203 #define CMD55_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
 204
 205 #define ACMD41            (INDX(41) | RSP_TYPE_48BITS)
 206 #define ACMD41_INT_EN     (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
 207
 208 #define ACMD6             (INDX(6) | RSP_TYPE_48BITS)
 209 #define ACMD6_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
 210
 211 #endif //__OMAP3530SDIO_H__