3 Copyright (c) 2008-2009, Apple Inc. All rights reserved.
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "PciEmulation.h"
16 #include <Omap3530/Omap3530.h>
18 EFI_CPU_ARCH_PROTOCOL
*gCpu
;
19 EMBEDDED_EXTERNAL_DEVICE
*gTPS65950
;
21 #define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44
24 ACPI_HID_DEVICE_PATH AcpiDevicePath
;
25 PCI_DEVICE_PATH PciDevicePath
;
26 EFI_DEVICE_PATH_PROTOCOL EndDevicePath
;
27 } EFI_PCI_IO_DEVICE_PATH
;
31 EFI_PCI_IO_DEVICE_PATH DevicePath
;
32 EFI_PCI_IO_PROTOCOL PciIoProtocol
;
33 PCI_TYPE00
*ConfigSpace
;
34 PCI_ROOT_BRIDGE RootBridge
;
36 } EFI_PCI_IO_PRIVATE_DATA
;
38 #define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o')
39 #define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)
41 EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate
=
44 { ACPI_DEVICE_PATH
, ACPI_DP
, sizeof (ACPI_HID_DEVICE_PATH
), 0},
45 EISA_PNP_ID(0x0A03), // HID
49 { HARDWARE_DEVICE_PATH
, HW_PCI_DP
, sizeof (PCI_DEVICE_PATH
), 0},
53 { END_DEVICE_PATH_TYPE
, END_ENTIRE_DEVICE_PATH_SUBTYPE
, sizeof (EFI_DEVICE_PATH_PROTOCOL
), 0}
65 // Take USB host out of force-standby mode
66 MmioWrite32 (UHH_SYSCONFIG
, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
67 | UHH_SYSCONFIG_CLOCKACTIVITY_ON
68 | UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
69 | UHH_SYSCONFIG_ENAWAKEUP_ENABLE
70 | UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN
);
71 MmioWrite32 (UHH_HOSTCONFIG
, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
72 | UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
73 | UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
74 | UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
75 | UHH_HOSTCONFIG_ENA_INCR16_ENABLE
76 | UHH_HOSTCONFIG_ENA_INCR8_ENABLE
77 | UHH_HOSTCONFIG_ENA_INCR4_ENABLE
78 | UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON
79 | UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE
);
81 // USB reset (GPIO 147 - Port 5 pin 19) output high
82 MmioAnd32(GPIO5_BASE
+ GPIO_OE
, ~BIT19
);
83 MmioWrite32 (GPIO5_BASE
+ GPIO_SETDATAOUT
, BIT19
);
85 // Get the Power IC protocol.
86 Status
= gBS
->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid
, NULL
, (VOID
**)&gTPS65950
);
87 ASSERT_EFI_ERROR(Status
);
89 //Enable power to the USB host.
90 Status
= gTPS65950
->Read(gTPS65950
, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3
, LEDEN
), 1, &Data
);
91 ASSERT_EFI_ERROR(Status
);
93 //LEDAON & LEDAPWM control the power to the USB host so enable those bits.
94 Data
|= (LEDAON
| LEDAPWM
);
96 Status
= gTPS65950
->Write(gTPS65950
, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3
, LEDEN
), 1, &Data
);
97 ASSERT_EFI_ERROR(Status
);
103 IN EFI_PCI_IO_PROTOCOL
*This
,
104 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
114 return EFI_UNSUPPORTED
;
119 IN EFI_PCI_IO_PROTOCOL
*This
,
120 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
130 return EFI_UNSUPPORTED
;
135 IN EFI_PCI_IO_PROTOCOL
*This
,
136 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
143 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
145 return PciRootBridgeIoMemRead (&Private
->RootBridge
.Io
,
146 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) Width
,
147 Private
->ConfigSpace
->Device
.Bar
[BarIndex
] + Offset
,
155 IN EFI_PCI_IO_PROTOCOL
*This
,
156 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
163 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
165 return PciRootBridgeIoMemWrite (&Private
->RootBridge
.Io
,
166 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) Width
,
167 Private
->ConfigSpace
->Device
.Bar
[BarIndex
] + Offset
,
175 IN EFI_PCI_IO_PROTOCOL
*This
,
176 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
184 return EFI_UNSUPPORTED
;
189 IN EFI_PCI_IO_PROTOCOL
*This
,
190 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
198 return EFI_UNSUPPORTED
;
203 IN EFI_PCI_IO_PROTOCOL
*This
,
204 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
210 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
212 return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
)Width
,
217 (PTR
)(UINTN
)(((UINT8
*)Private
->ConfigSpace
) + Offset
)
223 IN EFI_PCI_IO_PROTOCOL
*This
,
224 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
230 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
232 return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) Width
,
235 (PTR
)(UINTN
)(((UINT8
*)Private
->ConfigSpace
) + Offset
),
243 IN EFI_PCI_IO_PROTOCOL
*This
,
244 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
245 IN UINT8 DestBarIndex
,
246 IN UINT64 DestOffset
,
247 IN UINT8 SrcBarIndex
,
253 return EFI_UNSUPPORTED
;
258 IN EFI_PCI_IO_PROTOCOL
*This
,
259 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation
,
260 IN VOID
*HostAddress
,
261 IN OUT UINTN
*NumberOfBytes
,
262 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
266 MAP_INFO_INSTANCE
*Map
;
269 if ( HostAddress
== NULL
|| NumberOfBytes
== NULL
||
270 DeviceAddress
== NULL
|| Mapping
== NULL
) {
272 return EFI_INVALID_PARAMETER
;
276 if (Operation
>= EfiPciOperationMaximum
) {
277 return EFI_INVALID_PARAMETER
;
280 *DeviceAddress
= ConvertToPhysicalAddress (HostAddress
);
282 // Data cache flush (HostAddress, NumberOfBytes);
284 // Remember range so we can flush on the other side
285 Status
= gBS
->AllocatePool (EfiBootServicesData
, sizeof (PCI_DMA_MAP
), (VOID
**) &Map
);
286 if (EFI_ERROR(Status
)) {
287 return EFI_OUT_OF_RESOURCES
;
292 Map
->HostAddress
= (UINTN
)HostAddress
;
293 Map
->DeviceAddress
= *DeviceAddress
;
294 Map
->NumberOfBytes
= *NumberOfBytes
;
295 Map
->Operation
= Operation
;
297 // EfiCpuFlushTypeWriteBack, EfiCpuFlushTypeInvalidate
298 gCpu
->FlushDataCache (gCpu
, (EFI_PHYSICAL_ADDRESS
)(UINTN
)HostAddress
, *NumberOfBytes
, EfiCpuFlushTypeWriteBackInvalidate
);
305 IN EFI_PCI_IO_PROTOCOL
*This
,
311 if (Mapping
== NULL
) {
313 return EFI_INVALID_PARAMETER
;
316 Map
= (PCI_DMA_MAP
*)Mapping
;
317 if (Map
->Operation
== EfiPciOperationBusMasterWrite
) {
319 // Make sure we read buffer from uncached memory and not the cache
321 gCpu
->FlushDataCache (gCpu
, Map
->HostAddress
, Map
->NumberOfBytes
, EfiCpuFlushTypeInvalidate
);
330 PciIoAllocateBuffer (
331 IN EFI_PCI_IO_PROTOCOL
*This
,
332 IN EFI_ALLOCATE_TYPE Type
,
333 IN EFI_MEMORY_TYPE MemoryType
,
335 OUT VOID
**HostAddress
,
339 if (Attributes
& EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER
) {
340 return EFI_UNSUPPORTED
;
343 if (HostAddress
== NULL
) {
344 return EFI_INVALID_PARAMETER
;
348 // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
350 // We used uncached memory to keep coherency
352 if (MemoryType
== EfiBootServicesData
) {
353 *HostAddress
= UncachedAllocatePages (Pages
);
354 } else if (MemoryType
!= EfiRuntimeServicesData
) {
355 *HostAddress
= UncachedAllocateRuntimePages (Pages
);
357 return EFI_INVALID_PARAMETER
;
365 IN EFI_PCI_IO_PROTOCOL
*This
,
370 if (HostAddress
== NULL
) {
371 return EFI_INVALID_PARAMETER
;
374 UncachedFreePages (HostAddress
, Pages
);
381 IN EFI_PCI_IO_PROTOCOL
*This
389 IN EFI_PCI_IO_PROTOCOL
*This
,
390 OUT UINTN
*SegmentNumber
,
391 OUT UINTN
*BusNumber
,
392 OUT UINTN
*DeviceNumber
,
393 OUT UINTN
*FunctionNumber
396 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
398 if (SegmentNumber
!= NULL
) {
399 *SegmentNumber
= Private
->Segment
;
402 if (BusNumber
!= NULL
) {
406 if (DeviceNumber
!= NULL
) {
410 if (FunctionNumber
!= NULL
) {
419 IN EFI_PCI_IO_PROTOCOL
*This
,
420 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation
,
421 IN UINT64 Attributes
,
422 OUT UINT64
*Result OPTIONAL
426 case EfiPciIoAttributeOperationGet
:
427 case EfiPciIoAttributeOperationSupported
:
428 if (Result
== NULL
) {
429 return EFI_INVALID_PARAMETER
;
431 // We are not a real PCI device so just say things we kind of do
432 *Result
= EFI_PCI_IO_ATTRIBUTE_MEMORY
| EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
| EFI_PCI_DEVICE_ENABLE
;
435 case EfiPciIoAttributeOperationSet
:
436 case EfiPciIoAttributeOperationEnable
:
437 case EfiPciIoAttributeOperationDisable
:
438 // Since we are not a real PCI device no enable/set or disable operations exist.
443 return EFI_INVALID_PARAMETER
;
449 PciIoGetBarAttributes (
450 IN EFI_PCI_IO_PROTOCOL
*This
,
452 OUT UINT64
*Supports
, OPTIONAL
453 OUT VOID
**Resources OPTIONAL
457 return EFI_UNSUPPORTED
;
461 PciIoSetBarAttributes (
462 IN EFI_PCI_IO_PROTOCOL
*This
,
463 IN UINT64 Attributes
,
465 IN OUT UINT64
*Offset
,
466 IN OUT UINT64
*Length
470 return EFI_UNSUPPORTED
;
473 EFI_PCI_IO_PROTOCOL PciIoTemplate
=
491 PciIoGetBarAttributes
,
492 PciIoSetBarAttributes
,
499 PciEmulationEntryPoint (
500 IN EFI_HANDLE ImageHandle
,
501 IN EFI_SYSTEM_TABLE
*SystemTable
506 EFI_PCI_IO_PRIVATE_DATA
*Private
;
507 UINT8 CapabilityLength
;
511 // Get the Cpu protocol for later use
512 Status
= gBS
->LocateProtocol(&gEfiCpuArchProtocolGuid
, NULL
, (VOID
**)&gCpu
);
513 ASSERT_EFI_ERROR(Status
);
515 //Configure USB host for OMAP3530.
518 // Create a private structure
519 Private
= AllocatePool(sizeof(EFI_PCI_IO_PRIVATE_DATA
));
520 if (Private
== NULL
) {
521 Status
= EFI_OUT_OF_RESOURCES
;
525 Private
->Signature
= EFI_PCI_IO_PRIVATE_DATA_SIGNATURE
; // Fill in signature
526 Private
->RootBridge
.Signature
= PCI_ROOT_BRIDGE_SIGNATURE
; // Fake Root Bridge structure needs a signature too
527 Private
->RootBridge
.MemoryStart
= USB_EHCI_HCCAPBASE
; // Get the USB capability register base
528 Private
->Segment
= 0; // Default to segment zero
530 // Find out the capability register length and number of physical ports.
531 CapabilityLength
= MmioRead8(Private
->RootBridge
.MemoryStart
);
532 PhysicalPorts
= (MmioRead32 (Private
->RootBridge
.MemoryStart
+ 0x4)) & 0x0000000F;
534 // Calculate the total size of the USB registers.
535 Private
->RootBridge
.MemorySize
= CapabilityLength
+ (HOST_CONTROLLER_OPERATION_REG_SIZE
+ ((4 * PhysicalPorts
) - 1));
537 // Enable Port Power bit in Port status and control registers in EHCI register space.
538 // Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates
539 // host controller implementation includes port power control.
540 for (Count
= 0; Count
< PhysicalPorts
; Count
++) {
541 MmioOr32 ((Private
->RootBridge
.MemoryStart
+ CapabilityLength
+ HOST_CONTROLLER_OPERATION_REG_SIZE
+ 4*Count
), 0x00001000);
544 // Create fake PCI config space.
545 Private
->ConfigSpace
= AllocateZeroPool(sizeof(PCI_TYPE00
));
546 if (Private
->ConfigSpace
== NULL
) {
547 Status
= EFI_OUT_OF_RESOURCES
;
552 // Configure PCI config space
553 Private
->ConfigSpace
->Hdr
.VendorId
= 0x3530;
554 Private
->ConfigSpace
->Hdr
.DeviceId
= 0x3530;
555 Private
->ConfigSpace
->Hdr
.ClassCode
[0] = 0x20;
556 Private
->ConfigSpace
->Hdr
.ClassCode
[1] = 0x03;
557 Private
->ConfigSpace
->Hdr
.ClassCode
[2] = 0x0C;
558 Private
->ConfigSpace
->Device
.Bar
[0] = Private
->RootBridge
.MemoryStart
;
562 // Unique device path.
563 CopyMem(&Private
->DevicePath
, &PciIoDevicePathTemplate
, sizeof(PciIoDevicePathTemplate
));
564 Private
->DevicePath
.AcpiDevicePath
.UID
= 0;
566 // Copy protocol structure
567 CopyMem(&Private
->PciIoProtocol
, &PciIoTemplate
, sizeof(PciIoTemplate
));
569 Status
= gBS
->InstallMultipleProtocolInterfaces(&Handle
,
570 &gEfiPciIoProtocolGuid
, &Private
->PciIoProtocol
,
571 &gEfiDevicePathProtocolGuid
, &Private
->DevicePath
,
573 if (EFI_ERROR(Status
)) {
574 DEBUG((EFI_D_ERROR
, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces() failed.\n"));