3 Copyright (c) 2008-2009, Apple Inc. All rights reserved.
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "PciEmulation.h"
16 #include <Omap3530/Omap3530.h>
18 EFI_CPU_ARCH_PROTOCOL
*gCpu
;
19 EMBEDDED_EXTERNAL_DEVICE
*gTPS65950
;
21 #define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44
24 ACPI_HID_DEVICE_PATH AcpiDevicePath
;
25 PCI_DEVICE_PATH PciDevicePath
;
26 EFI_DEVICE_PATH_PROTOCOL EndDevicePath
;
27 } EFI_PCI_IO_DEVICE_PATH
;
31 EFI_PCI_IO_DEVICE_PATH DevicePath
;
32 EFI_PCI_IO_PROTOCOL PciIoProtocol
;
33 PCI_TYPE00
*ConfigSpace
;
34 PCI_ROOT_BRIDGE RootBridge
;
36 } EFI_PCI_IO_PRIVATE_DATA
;
38 #define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o')
39 #define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)
41 EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate
=
44 { ACPI_DEVICE_PATH
, ACPI_DP
, sizeof (ACPI_HID_DEVICE_PATH
), 0},
45 EISA_PNP_ID(0x0A03), // HID
49 { HARDWARE_DEVICE_PATH
, HW_PCI_DP
, sizeof (PCI_DEVICE_PATH
), 0},
53 { END_DEVICE_PATH_TYPE
, END_ENTIRE_DEVICE_PATH_SUBTYPE
, sizeof (EFI_DEVICE_PATH_PROTOCOL
), 0}
65 // Get the Power IC protocol.
66 Status
= gBS
->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid
, NULL
, (VOID
**)&gTPS65950
);
67 ASSERT_EFI_ERROR(Status
);
69 //Enable power to the USB host.
70 Status
= gTPS65950
->Read(gTPS65950
, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3
, LEDEN
), 1, &Data
);
71 ASSERT_EFI_ERROR(Status
);
73 //LEDAON & LEDAPWM control the power to the USB host so enable those bits.
74 Data
|= (LEDAON
| LEDAPWM
);
76 Status
= gTPS65950
->Write(gTPS65950
, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3
, LEDEN
), 1, &Data
);
77 ASSERT_EFI_ERROR(Status
);
79 // USB reset (GPIO 147 - Port 5 pin 19) output low
80 MmioAnd32 (GPIO5_BASE
+ GPIO_OE
, ~BIT19
);
81 MmioWrite32 (GPIO5_BASE
+ GPIO_CLEARDATAOUT
, BIT19
);
83 // Turn on functional & interface clocks to the USBHOST power domain
84 MmioOr32 (CM_FCLKEN_USBHOST
, CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE
| CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE
);
85 MmioOr32 (CM_ICLKEN_USBHOST
, CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE
);
86 // Wait for clock to become active
87 while (0 == (MmioRead32 (CM_CLKSTST_USBHOST
) & 1));
91 // Take USB host out of force-standby mode
92 MmioWrite32 (UHH_SYSCONFIG
, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
93 | UHH_SYSCONFIG_CLOCKACTIVITY_ON
94 | UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
95 | UHH_SYSCONFIG_ENAWAKEUP_ENABLE
96 | UHH_SYSCONFIG_SOFTRESET
98 while ((MmioRead32 (UHH_SYSSTATUS
) & UHH_SYSSTATUS_RESETDONE
) == UHH_SYSSTATUS_RESETDONE
);
100 MmioWrite32 (UHH_SYSCONFIG
, UHH_SYSCONFIG_CLOCKACTIVITY_ON
101 | UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
102 | UHH_SYSCONFIG_ENAWAKEUP_ENABLE
106 MmioWrite32 (UHH_HOSTCONFIG
, UHH_HOSTCONFIG_ENA_INCR16_ENABLE
107 | UHH_HOSTCONFIG_ENA_INCR8_ENABLE
108 | UHH_HOSTCONFIG_ENA_INCR4_ENABLE
111 // USB reset output high
112 MmioWrite32 (GPIO5_BASE
+ GPIO_SETDATAOUT
, BIT19
);
118 IN EFI_PCI_IO_PROTOCOL
*This
,
119 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
129 return EFI_UNSUPPORTED
;
134 IN EFI_PCI_IO_PROTOCOL
*This
,
135 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
145 return EFI_UNSUPPORTED
;
150 IN EFI_PCI_IO_PROTOCOL
*This
,
151 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
158 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
160 return PciRootBridgeIoMemRead (&Private
->RootBridge
.Io
,
161 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) Width
,
162 Private
->ConfigSpace
->Device
.Bar
[BarIndex
] + Offset
,
170 IN EFI_PCI_IO_PROTOCOL
*This
,
171 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
178 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
180 return PciRootBridgeIoMemWrite (&Private
->RootBridge
.Io
,
181 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) Width
,
182 Private
->ConfigSpace
->Device
.Bar
[BarIndex
] + Offset
,
190 IN EFI_PCI_IO_PROTOCOL
*This
,
191 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
199 return EFI_UNSUPPORTED
;
204 IN EFI_PCI_IO_PROTOCOL
*This
,
205 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
213 return EFI_UNSUPPORTED
;
218 IN EFI_PCI_IO_PROTOCOL
*This
,
219 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
225 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
227 return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
)Width
,
232 (PTR
)(UINTN
)(((UINT8
*)Private
->ConfigSpace
) + Offset
)
238 IN EFI_PCI_IO_PROTOCOL
*This
,
239 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
245 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
247 return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) Width
,
250 (PTR
)(UINTN
)(((UINT8
*)Private
->ConfigSpace
) + Offset
),
258 IN EFI_PCI_IO_PROTOCOL
*This
,
259 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
260 IN UINT8 DestBarIndex
,
261 IN UINT64 DestOffset
,
262 IN UINT8 SrcBarIndex
,
268 return EFI_UNSUPPORTED
;
273 IN EFI_PCI_IO_PROTOCOL
*This
,
274 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation
,
275 IN VOID
*HostAddress
,
276 IN OUT UINTN
*NumberOfBytes
,
277 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
281 MAP_INFO_INSTANCE
*Map
;
284 if ( HostAddress
== NULL
|| NumberOfBytes
== NULL
||
285 DeviceAddress
== NULL
|| Mapping
== NULL
) {
287 return EFI_INVALID_PARAMETER
;
291 if (Operation
>= EfiPciOperationMaximum
) {
292 return EFI_INVALID_PARAMETER
;
295 *DeviceAddress
= ConvertToPhysicalAddress (HostAddress
);
297 // Data cache flush (HostAddress, NumberOfBytes);
299 // Remember range so we can flush on the other side
300 Status
= gBS
->AllocatePool (EfiBootServicesData
, sizeof (PCI_DMA_MAP
), (VOID
**) &Map
);
301 if (EFI_ERROR(Status
)) {
302 return EFI_OUT_OF_RESOURCES
;
307 Map
->HostAddress
= (UINTN
)HostAddress
;
308 Map
->DeviceAddress
= *DeviceAddress
;
309 Map
->NumberOfBytes
= *NumberOfBytes
;
310 Map
->Operation
= Operation
;
312 // EfiCpuFlushTypeWriteBack, EfiCpuFlushTypeInvalidate
313 gCpu
->FlushDataCache (gCpu
, (EFI_PHYSICAL_ADDRESS
)(UINTN
)HostAddress
, *NumberOfBytes
, EfiCpuFlushTypeWriteBackInvalidate
);
320 IN EFI_PCI_IO_PROTOCOL
*This
,
326 if (Mapping
== NULL
) {
328 return EFI_INVALID_PARAMETER
;
331 Map
= (PCI_DMA_MAP
*)Mapping
;
332 if (Map
->Operation
== EfiPciOperationBusMasterWrite
) {
334 // Make sure we read buffer from uncached memory and not the cache
336 gCpu
->FlushDataCache (gCpu
, Map
->HostAddress
, Map
->NumberOfBytes
, EfiCpuFlushTypeInvalidate
);
345 PciIoAllocateBuffer (
346 IN EFI_PCI_IO_PROTOCOL
*This
,
347 IN EFI_ALLOCATE_TYPE Type
,
348 IN EFI_MEMORY_TYPE MemoryType
,
350 OUT VOID
**HostAddress
,
354 if (Attributes
& EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER
) {
355 return EFI_UNSUPPORTED
;
358 if (HostAddress
== NULL
) {
359 return EFI_INVALID_PARAMETER
;
363 // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
365 // We used uncached memory to keep coherency
367 if (MemoryType
== EfiBootServicesData
) {
368 *HostAddress
= UncachedAllocatePages (Pages
);
369 } else if (MemoryType
!= EfiRuntimeServicesData
) {
370 *HostAddress
= UncachedAllocateRuntimePages (Pages
);
372 return EFI_INVALID_PARAMETER
;
380 IN EFI_PCI_IO_PROTOCOL
*This
,
385 if (HostAddress
== NULL
) {
386 return EFI_INVALID_PARAMETER
;
389 UncachedFreePages (HostAddress
, Pages
);
396 IN EFI_PCI_IO_PROTOCOL
*This
404 IN EFI_PCI_IO_PROTOCOL
*This
,
405 OUT UINTN
*SegmentNumber
,
406 OUT UINTN
*BusNumber
,
407 OUT UINTN
*DeviceNumber
,
408 OUT UINTN
*FunctionNumber
411 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
413 if (SegmentNumber
!= NULL
) {
414 *SegmentNumber
= Private
->Segment
;
417 if (BusNumber
!= NULL
) {
421 if (DeviceNumber
!= NULL
) {
425 if (FunctionNumber
!= NULL
) {
434 IN EFI_PCI_IO_PROTOCOL
*This
,
435 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation
,
436 IN UINT64 Attributes
,
437 OUT UINT64
*Result OPTIONAL
441 case EfiPciIoAttributeOperationGet
:
442 case EfiPciIoAttributeOperationSupported
:
443 if (Result
== NULL
) {
444 return EFI_INVALID_PARAMETER
;
446 // We are not a real PCI device so just say things we kind of do
447 *Result
= EFI_PCI_IO_ATTRIBUTE_MEMORY
| EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
| EFI_PCI_DEVICE_ENABLE
;
450 case EfiPciIoAttributeOperationSet
:
451 case EfiPciIoAttributeOperationEnable
:
452 case EfiPciIoAttributeOperationDisable
:
453 // Since we are not a real PCI device no enable/set or disable operations exist.
458 return EFI_INVALID_PARAMETER
;
464 PciIoGetBarAttributes (
465 IN EFI_PCI_IO_PROTOCOL
*This
,
467 OUT UINT64
*Supports
, OPTIONAL
468 OUT VOID
**Resources OPTIONAL
472 return EFI_UNSUPPORTED
;
476 PciIoSetBarAttributes (
477 IN EFI_PCI_IO_PROTOCOL
*This
,
478 IN UINT64 Attributes
,
480 IN OUT UINT64
*Offset
,
481 IN OUT UINT64
*Length
485 return EFI_UNSUPPORTED
;
488 EFI_PCI_IO_PROTOCOL PciIoTemplate
=
506 PciIoGetBarAttributes
,
507 PciIoSetBarAttributes
,
514 PciEmulationEntryPoint (
515 IN EFI_HANDLE ImageHandle
,
516 IN EFI_SYSTEM_TABLE
*SystemTable
521 EFI_PCI_IO_PRIVATE_DATA
*Private
;
522 UINT8 CapabilityLength
;
526 // Get the Cpu protocol for later use
527 Status
= gBS
->LocateProtocol(&gEfiCpuArchProtocolGuid
, NULL
, (VOID
**)&gCpu
);
528 ASSERT_EFI_ERROR(Status
);
530 //Configure USB host for OMAP3530.
533 // Create a private structure
534 Private
= AllocatePool(sizeof(EFI_PCI_IO_PRIVATE_DATA
));
535 if (Private
== NULL
) {
536 Status
= EFI_OUT_OF_RESOURCES
;
540 Private
->Signature
= EFI_PCI_IO_PRIVATE_DATA_SIGNATURE
; // Fill in signature
541 Private
->RootBridge
.Signature
= PCI_ROOT_BRIDGE_SIGNATURE
; // Fake Root Bridge structure needs a signature too
542 Private
->RootBridge
.MemoryStart
= USB_EHCI_HCCAPBASE
; // Get the USB capability register base
543 Private
->Segment
= 0; // Default to segment zero
545 // Find out the capability register length and number of physical ports.
546 CapabilityLength
= MmioRead8(Private
->RootBridge
.MemoryStart
);
547 PhysicalPorts
= (MmioRead32(Private
->RootBridge
.MemoryStart
+ 0x4)) & 0x0000000F;
549 // Calculate the total size of the USB registers.
550 Private
->RootBridge
.MemorySize
= CapabilityLength
+ (HOST_CONTROLLER_OPERATION_REG_SIZE
+ ((4 * PhysicalPorts
) - 1));
552 // Enable Port Power bit in Port status and control registers in EHCI register space.
553 // Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates
554 // host controller implementation includes port power control.
555 for (Count
= 0; Count
< PhysicalPorts
; Count
++) {
556 MmioOr32((Private
->RootBridge
.MemoryStart
+ CapabilityLength
+ HOST_CONTROLLER_OPERATION_REG_SIZE
+ 4*Count
), 0x00001000);
559 // Create fake PCI config space.
560 Private
->ConfigSpace
= AllocateZeroPool(sizeof(PCI_TYPE00
));
561 if (Private
->ConfigSpace
== NULL
) {
562 Status
= EFI_OUT_OF_RESOURCES
;
567 // Configure PCI config space
568 Private
->ConfigSpace
->Hdr
.VendorId
= 0x3530;
569 Private
->ConfigSpace
->Hdr
.DeviceId
= 0x3530;
570 Private
->ConfigSpace
->Hdr
.ClassCode
[0] = 0x20;
571 Private
->ConfigSpace
->Hdr
.ClassCode
[1] = 0x03;
572 Private
->ConfigSpace
->Hdr
.ClassCode
[2] = 0x0C;
573 Private
->ConfigSpace
->Device
.Bar
[0] = Private
->RootBridge
.MemoryStart
;
577 // Unique device path.
578 CopyMem(&Private
->DevicePath
, &PciIoDevicePathTemplate
, sizeof(PciIoDevicePathTemplate
));
579 Private
->DevicePath
.AcpiDevicePath
.UID
= 0;
581 // Copy protocol structure
582 CopyMem(&Private
->PciIoProtocol
, &PciIoTemplate
, sizeof(PciIoTemplate
));
584 Status
= gBS
->InstallMultipleProtocolInterfaces(&Handle
,
585 &gEfiPciIoProtocolGuid
, &Private
->PciIoProtocol
,
586 &gEfiDevicePathProtocolGuid
, &Private
->DevicePath
,
588 if (EFI_ERROR(Status
)) {
589 DEBUG((EFI_D_ERROR
, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces() failed.\n"));