OptionRomPkg/UndiRuntimeDxe/E100b.h

   1 /** @file
   2   Definitions for network adapter card.
   3
   4 Copyright (c) 2006 - 2007, Intel Corporation
   5 All rights reserved. This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _E100B_H_
  16 #define _E100B_H_
  17
  18 // pci config offsets:
  19
  20 #define RX_BUFFER_COUNT 32
  21 #define TX_BUFFER_COUNT 32
  22
  23 #define PCI_VENDOR_ID_INTEL 0x8086
  24 #define PCI_DEVICE_ID_INTEL_82557 0x1229
  25 #define D100_VENDOR_ID   0x8086
  26 #define D100_DEVICE_ID   0x1229
  27 #define D102_DEVICE_ID   0x2449
  28
  29 #define ICH3_DEVICE_ID_1   0x1031
  30 #define ICH3_DEVICE_ID_2   0x1032
  31 #define ICH3_DEVICE_ID_3   0x1033
  32 #define ICH3_DEVICE_ID_4   0x1034
  33 #define ICH3_DEVICE_ID_5   0x1035
  34 #define ICH3_DEVICE_ID_6   0x1036
  35 #define ICH3_DEVICE_ID_7   0x1037
  36 #define ICH3_DEVICE_ID_8   0x1038
  37
  38 #define SPEEDO_DEVICE_ID   0x1227
  39 #define SPLASH1_DEVICE_ID   0x1226
  40
  41
  42 // bit fields for the command
  43 #define PCI_COMMAND_MASTER  0x04  // bit 2
  44 #define PCI_COMMAND_IO    0x01  // bit 0
  45 #define PCI_COMMAND  0x04
  46 #define PCI_LATENCY_TIMER  0x0D
  47
  48 #define ETHER_MAC_ADDR_LEN 6
  49 #ifdef AVL_XXX
  50 #define ETHER_HEADER_LEN 14
  51 // media interface type
  52 // #define INTERFACE_TYPE "
  53
  54 // Hardware type values
  55 #define HW_ETHER_TYPE    1
  56 #define HW_EXPERIMENTAL_ETHER_TYPE 2
  57 #define HW_IEEE_TYPE    6
  58 #define HW_ARCNET_TYPE     7
  59
  60 #endif  // AVL_XXX
  61
  62 #define MAX_ETHERNET_PKT_SIZE 1514  // including eth header
  63 #define RX_BUFFER_SIZE 1536  // including crc and padding
  64 #define TX_BUFFER_SIZE 64
  65 #define ETH_MTU 1500  // does not include ethernet header length
  66
  67 #define SPEEDO3_TOTAL_SIZE 0x20
  68
  69 #pragma pack(1)
  70
  71 typedef struct eth {
  72   UINT8 dest_addr[PXE_HWADDR_LEN_ETHER];
  73   UINT8 src_addr[PXE_HWADDR_LEN_ETHER];
  74   UINT16 type;
  75 } EtherHeader;
  76
  77 #pragma pack(1)
  78 typedef struct CONFIG_HEADER {
  79   UINT16 VendorID;
  80   UINT16 DeviceID;
  81   UINT16 Command;
  82   UINT16 Status;
  83   UINT16 RevID;
  84   UINT16 ClassID;
  85   UINT8  CacheLineSize;
  86   UINT8  LatencyTimer;
  87   UINT8  HeaderType;    // must be zero to impose this structure...
  88   UINT8  BIST;  // built-in self test
  89   UINT32 BaseAddressReg_0;  // memory mapped address
  90   UINT32 BaseAddressReg_1;  //io mapped address, Base IO address
  91   UINT32 BaseAddressReg_2;  // option rom address
  92   UINT32 BaseAddressReg_3;
  93   UINT32 BaseAddressReg_4;
  94   UINT32 BaseAddressReg_5;
  95   UINT32 CardBusCISPtr;
  96   UINT16 SubVendorID;
  97   UINT16 SubSystemID;
  98   UINT32 ExpansionROMBaseAddr;
  99   UINT8 CapabilitiesPtr;
 100   UINT8 reserved1;
 101   UINT16 Reserved2;
 102   UINT32 Reserved3;
 103   UINT8 int_line;
 104   UINT8 int_pin;
 105   UINT8 Min_gnt;
 106   UINT8 Max_lat;
 107 } PCI_CONFIG_HEADER;
 108 #pragma pack()
 109
 110 //-------------------------------------------------------------------------
 111 // Offsets to the various registers.
 112 //   All accesses need not be longword aligned.
 113 //-------------------------------------------------------------------------
 114 enum speedo_offsets {
 115   SCBStatus = 0, SCBCmd = 2,     // Rx/Command Unit command and status.
 116   SCBPointer = 4,                // General purpose pointer.
 117   SCBPort = 8,                   // Misc. commands and operands.
 118   SCBflash = 12, SCBeeprom = 14, // EEPROM and flash memory control.
 119   SCBCtrlMDI = 16,               // MDI interface control.
 120   SCBEarlyRx = 20,               // Early receive byte count.
 121   SCBEarlyRxInt = 24, SCBFlowCtrlReg = 25, SCBPmdr = 27,
 122   // offsets for general control registers (GCRs)
 123   SCBGenCtrl = 28, SCBGenStatus = 29, SCBGenCtrl2 = 30, SCBRsvd = 31
 124 };
 125
 126 #define GCR2_EEPROM_ACCESS_SEMAPHORE 0x80 // bit offset into the gcr2
 127
 128 //-------------------------------------------------------------------------
 129 // Action commands - Commands that can be put in a command list entry.
 130 //-------------------------------------------------------------------------
 131 enum commands {
 132   CmdNOp = 0, CmdIASetup = 1, CmdConfigure = 2, CmdMulticastList = 3,
 133   CmdTx = 4, CmdTDR = 5, CmdDump = 6, CmdDiagnose = 7,
 134   CmdSuspend = 0x4000,    /* Suspend after completion. */
 135   CmdIntr = 0x2000,      /* Interrupt after completion. */
 136   CmdTxFlex = 0x0008      /* Use "Flexible mode" for CmdTx command. */
 137 };
 138
 139 //-------------------------------------------------------------------------
 140 // port commands
 141 //-------------------------------------------------------------------------
 142 #define PORT_RESET 0
 143 #define PORT_SELF_TEST 1
 144 #define POR_SELECTIVE_RESET 2
 145 #define PORT_DUMP_POINTER 2
 146
 147 //-------------------------------------------------------------------------
 148 // SCB Command Word bit definitions
 149 //-------------------------------------------------------------------------
 150 //- CUC fields
 151 #define   CU_START    0x0010
 152 #define   CU_RESUME    0x0020
 153 #define   CU_STATSADDR  0x0040
 154 #define   CU_SHOWSTATS  0x0050  /* Dump statistics counters. */
 155 #define   CU_CMD_BASE  0x0060  /* Base address to add to add CU commands. */
 156 #define   CU_DUMPSTATS  0x0070  /* Dump then reset stats counters. */
 157
 158 //- RUC fields
 159 #define   RX_START  0x0001
 160 #define   RX_RESUME  0x0002
 161 #define   RX_ABORT  0x0004
 162 #define   RX_ADDR_LOAD  0x0006  /* load ru_base_reg */
 163 #define   RX_RESUMENR  0x0007
 164
 165 // Interrupt fields (assuming byte addressing)
 166 #define INT_MASK  0x0100
 167 #define DRVR_INT  0x0200    /* Driver generated interrupt. */
 168
 169 //- CB Status Word
 170 #define CMD_STATUS_COMPLETE 0x8000
 171 #define RX_STATUS_COMPLETE 0x8000
 172 #define CMD_STATUS_MASK 0xF000
 173
 174 //-------------------------------------------------------------------------
 175 //- SCB Status bits:
 176 // Interrupts are ACKed by writing to the upper 6 interrupt bits
 177 //-------------------------------------------------------------------------
 178 #define SCB_STATUS_MASK        0xFC00 // bits 2-7 - STATUS/ACK Mask
 179 #define SCB_STATUS_CX_TNO      0x8000 // BIT_15  - CX or TNO Interrupt
 180 #define SCB_STATUS_FR          0x4000 // BIT_14 - FR Interrupt
 181 #define SCB_STATUS_CNA         0x2000 // BIT_13 - CNA Interrupt
 182 #define SCB_STATUS_RNR         0x1000 // BIT_12  - RNR Interrupt
 183 #define SCB_STATUS_MDI         0x0800 // BIT_11  - MDI R/W Done Interrupt
 184 #define SCB_STATUS_SWI         0x0400 // BIT_10  - SWI Interrupt
 185
 186 // CU STATUS: bits 6 & 7
 187 #define SCB_STATUS_CU_MASK     0x00C0 // bits 6 & 7
 188 #define SCB_STATUS_CU_IDLE     0x0000 // 00
 189 #define SCB_STATUS_CU_SUSPEND  0x0040 // 01
 190 #define SCB_STATUS_CU_ACTIVE   0x0080 // 10
 191
 192 // RU STATUS: bits 2-5
 193 #define SCB_RUS_IDLE         0x0000
 194 #define SCB_RUS_SUSPENDED    0x0004  // bit 2
 195 #define SCB_RUS_NO_RESOURCES   0x0008 // bit 3
 196 #define SCB_RUS_READY       0x0010 // bit 4
 197
 198 //-------------------------------------------------------------------------
 199 // Bit Mask definitions
 200 //-------------------------------------------------------------------------
 201 #define BIT_0       0x0001
 202 #define BIT_1       0x0002
 203 #define BIT_2       0x0004
 204 #define BIT_3       0x0008
 205 #define BIT_4       0x0010
 206 #define BIT_5       0x0020
 207 #define BIT_6       0x0040
 208 #define BIT_7       0x0080
 209 #define BIT_8       0x0100
 210 #define BIT_9       0x0200
 211 #define BIT_10      0x0400
 212 #define BIT_11      0x0800
 213 #define BIT_12      0x1000
 214 #define BIT_13      0x2000
 215 #define BIT_14      0x4000
 216 #define BIT_15      0x8000
 217 #define BIT_24      0x01000000
 218 #define BIT_28      0x10000000
 219
 220
 221 //-------------------------------------------------------------------------
 222 // MDI Control register bit definitions
 223 //-------------------------------------------------------------------------
 224 #define MDI_DATA_MASK           BIT_0_15        // MDI Data port
 225 #define MDI_REG_ADDR            BIT_16_20       // which MDI register to read/write
 226 #define MDI_PHY_ADDR            BIT_21_25       // which PHY to read/write
 227 #define MDI_PHY_OPCODE          BIT_26_27       // which PHY to read/write
 228 #define MDI_PHY_READY           BIT_28          // PHY is ready for another MDI cycle
 229 #define MDI_PHY_INT_ENABLE      BIT_29          // Assert INT at MDI cycle completion
 230
 231 #define BIT_0_2     0x0007
 232 #define BIT_0_3     0x000F
 233 #define BIT_0_4     0x001F
 234 #define BIT_0_5     0x003F
 235 #define BIT_0_6     0x007F
 236 #define BIT_0_7     0x00FF
 237 #define BIT_0_8     0x01FF
 238 #define BIT_0_13    0x3FFF
 239 #define BIT_0_15    0xFFFF
 240 #define BIT_1_2     0x0006
 241 #define BIT_1_3     0x000E
 242 #define BIT_2_5     0x003C
 243 #define BIT_3_4     0x0018
 244 #define BIT_4_5     0x0030
 245 #define BIT_4_6     0x0070
 246 #define BIT_4_7     0x00F0
 247 #define BIT_5_7     0x00E0
 248 #define BIT_5_9     0x03E0
 249 #define BIT_5_12    0x1FE0
 250 #define BIT_5_15    0xFFE0
 251 #define BIT_6_7     0x00c0
 252 #define BIT_7_11    0x0F80
 253 #define BIT_8_10    0x0700
 254 #define BIT_9_13    0x3E00
 255 #define BIT_12_15   0xF000
 256
 257 #define BIT_16_20   0x001F0000
 258 #define BIT_21_25   0x03E00000
 259 #define BIT_26_27   0x0C000000
 260
 261 //-------------------------------------------------------------------------
 262 // MDI Control register opcode definitions
 263 //-------------------------------------------------------------------------
 264 #define MDI_WRITE               1               // Phy Write
 265 #define MDI_READ                2               // Phy read
 266
 267 //-------------------------------------------------------------------------
 268 // PHY 100 MDI Register/Bit Definitions
 269 //-------------------------------------------------------------------------
 270 // MDI register set
 271 #define MDI_CONTROL_REG             0x00        // MDI control register
 272 #define MDI_STATUS_REG              0x01        // MDI Status regiser
 273 #define PHY_ID_REG_1                0x02        // Phy indentification reg (word 1)
 274 #define PHY_ID_REG_2                0x03        // Phy indentification reg (word 2)
 275 #define AUTO_NEG_ADVERTISE_REG      0x04        // Auto-negotiation advertisement
 276 #define AUTO_NEG_LINK_PARTNER_REG   0x05        // Auto-negotiation link partner ability
 277 #define AUTO_NEG_EXPANSION_REG      0x06        // Auto-negotiation expansion
 278 #define AUTO_NEG_NEXT_PAGE_REG      0x07        // Auto-negotiation next page transmit
 279 #define EXTENDED_REG_0              0x10        // Extended reg 0 (Phy 100 modes)
 280 #define EXTENDED_REG_1              0x14        // Extended reg 1 (Phy 100 error indications)
 281 #define NSC_CONG_CONTROL_REG        0x17        // National (TX) congestion control
 282 #define NSC_SPEED_IND_REG           0x19        // National (TX) speed indication
 283
 284 // MDI Control register bit definitions
 285 #define MDI_CR_COLL_TEST_ENABLE     BIT_7       // Collision test enable
 286 #define MDI_CR_FULL_HALF            BIT_8       // FDX =1, half duplex =0
 287 #define MDI_CR_RESTART_AUTO_NEG     BIT_9       // Restart auto negotiation
 288 #define MDI_CR_ISOLATE              BIT_10      // Isolate PHY from MII
 289 #define MDI_CR_POWER_DOWN           BIT_11      // Power down
 290 #define MDI_CR_AUTO_SELECT          BIT_12      // Auto speed select enable
 291 #define MDI_CR_10_100               BIT_13      // 0 = 10Mbs, 1 = 100Mbs
 292 #define MDI_CR_LOOPBACK             BIT_14      // 0 = normal, 1 = loopback
 293 #define MDI_CR_RESET                BIT_15      // 0 = normal, 1 = PHY reset
 294
 295 // MDI Status register bit definitions
 296 #define MDI_SR_EXT_REG_CAPABLE      BIT_0       // Extended register capabilities
 297 #define MDI_SR_JABBER_DETECT        BIT_1       // Jabber detected
 298 #define MDI_SR_LINK_STATUS          BIT_2       // Link Status -- 1 = link
 299 #define MDI_SR_AUTO_SELECT_CAPABLE  BIT_3       // Auto speed select capable
 300 #define MDI_SR_REMOTE_FAULT_DETECT  BIT_4       // Remote fault detect
 301 #define MDI_SR_AUTO_NEG_COMPLETE    BIT_5       // Auto negotiation complete
 302 #define MDI_SR_10T_HALF_DPX         BIT_11      // 10BaseT Half Duplex capable
 303 #define MDI_SR_10T_FULL_DPX         BIT_12      // 10BaseT full duplex capable
 304 #define MDI_SR_TX_HALF_DPX          BIT_13      // TX Half Duplex capable
 305 #define MDI_SR_TX_FULL_DPX          BIT_14      // TX full duplex capable
 306 #define MDI_SR_T4_CAPABLE           BIT_15      // T4 capable
 307
 308 // Auto-Negotiation advertisement register bit definitions
 309 #define NWAY_AD_SELCTOR_FIELD       BIT_0_4     // identifies supported protocol
 310 #define NWAY_AD_ABILITY             BIT_5_12    // technologies that are supported
 311 #define NWAY_AD_10T_HALF_DPX        BIT_5       // 10BaseT Half Duplex capable
 312 #define NWAY_AD_10T_FULL_DPX        BIT_6       // 10BaseT full duplex capable
 313 #define NWAY_AD_TX_HALF_DPX         BIT_7       // TX Half Duplex capable
 314 #define NWAY_AD_TX_FULL_DPX         BIT_8       // TX full duplex capable
 315 #define NWAY_AD_T4_CAPABLE          BIT_9       // T4 capable
 316 #define NWAY_AD_REMOTE_FAULT        BIT_13      // indicates local remote fault
 317 #define NWAY_AD_RESERVED            BIT_14      // reserved
 318 #define NWAY_AD_NEXT_PAGE           BIT_15      // Next page (not supported)
 319
 320 // Auto-Negotiation link partner ability register bit definitions
 321 #define NWAY_LP_SELCTOR_FIELD       BIT_0_4     // identifies supported protocol
 322 #define NWAY_LP_ABILITY             BIT_5_9     // technologies that are supported
 323 #define NWAY_LP_REMOTE_FAULT        BIT_13      // indicates partner remote fault
 324 #define NWAY_LP_ACKNOWLEDGE         BIT_14      // acknowledge
 325 #define NWAY_LP_NEXT_PAGE           BIT_15      // Next page (not supported)
 326
 327 // Auto-Negotiation expansion register bit definitions
 328 #define NWAY_EX_LP_NWAY             BIT_0       // link partner is NWAY
 329 #define NWAY_EX_PAGE_RECEIVED       BIT_1       // link code word received
 330 #define NWAY_EX_NEXT_PAGE_ABLE      BIT_2       // local is next page able
 331 #define NWAY_EX_LP_NEXT_PAGE_ABLE   BIT_3       // partner is next page able
 332 #define NWAY_EX_PARALLEL_DET_FLT    BIT_4       // parallel detection fault
 333 #define NWAY_EX_RESERVED            BIT_5_15    // reserved
 334
 335
 336 // PHY 100 Extended Register 0 bit definitions
 337 #define PHY_100_ER0_FDX_INDIC       BIT_0       // 1 = FDX, 0 = half duplex
 338 #define PHY_100_ER0_SPEED_INDIC     BIT_1       // 1 = 100mbs, 0= 10mbs
 339 #define PHY_100_ER0_WAKE_UP         BIT_2       // Wake up DAC
 340 #define PHY_100_ER0_RESERVED        BIT_3_4     // Reserved
 341 #define PHY_100_ER0_REV_CNTRL       BIT_5_7     // Revsion control (A step = 000)
 342 #define PHY_100_ER0_FORCE_FAIL      BIT_8       // Force Fail is enabled
 343 #define PHY_100_ER0_TEST            BIT_9_13    // Revsion control (A step = 000)
 344 #define PHY_100_ER0_LINKDIS         BIT_14      // Link integrity test is disabled
 345 #define PHY_100_ER0_JABDIS          BIT_15      // Jabber function is disabled
 346
 347
 348 // PHY 100 Extended Register 1 bit definitions
 349 #define PHY_100_ER1_RESERVED        BIT_0_8     // Reserved
 350 #define PHY_100_ER1_CH2_DET_ERR     BIT_9       // Channel 2 EOF detection error
 351 #define PHY_100_ER1_MANCH_CODE_ERR  BIT_10      // Manchester code error
 352 #define PHY_100_ER1_EOP_ERR         BIT_11      // EOP error
 353 #define PHY_100_ER1_BAD_CODE_ERR    BIT_12      // bad code error
 354 #define PHY_100_ER1_INV_CODE_ERR    BIT_13      // invalid code error
 355 #define PHY_100_ER1_DC_BAL_ERR      BIT_14      // DC balance error
 356 #define PHY_100_ER1_PAIR_SKEW_ERR   BIT_15      // Pair skew error
 357
 358 // National Semiconductor TX phy congestion control register bit definitions
 359 #define NSC_TX_CONG_TXREADY         BIT_10      // Makes TxReady an input
 360 #define NSC_TX_CONG_ENABLE          BIT_8       // Enables congestion control
 361 #define NSC_TX_CONG_F_CONNECT       BIT_5       // Enables congestion control
 362
 363 // National Semiconductor TX phy speed indication register bit definitions
 364 #define NSC_TX_SPD_INDC_SPEED       BIT_6       // 0 = 100mb, 1=10mb
 365
 366 //-------------------------------------------------------------------------
 367 // Phy related constants
 368 //-------------------------------------------------------------------------
 369 #define PHY_503                 0
 370 #define PHY_100_A               0x000003E0
 371 #define PHY_100_C               0x035002A8
 372 #define PHY_TX_ID               0x015002A8
 373 #define PHY_NSC_TX              0x5c002000
 374 #define PHY_OTHER               0xFFFF
 375
 376 #define PHY_MODEL_REV_ID_MASK   0xFFF0FFFF
 377 #define PARALLEL_DETECT         0
 378 #define N_WAY                   1
 379
 380 #define RENEGOTIATE_TIME        35 // (3.5 Seconds)
 381
 382 #define CONNECTOR_AUTO          0
 383 #define CONNECTOR_TPE           1
 384 #define CONNECTOR_MII           2
 385
 386 //-------------------------------------------------------------------------
 387
 388 /* The Speedo3 Rx and Tx frame/buffer descriptors. */
 389 #pragma pack(1)
 390 struct CB_Header {      /* A generic descriptor. */
 391   UINT16 status;    /* Offset 0. */
 392   UINT16 command;    /* Offset 2. */
 393   UINT32 link;          /* struct descriptor *  */
 394 };
 395
 396 /* transmit command block structure */
 397 #pragma pack(1)
 398 typedef struct s_TxCB {
 399   struct CB_Header cb_header;
 400   UINT32 PhysTBDArrayAddres;  /* address of an array that contains
 401                 physical TBD pointers */
 402   UINT16 ByteCount;  /* immediate data count = 0 always */
 403   UINT8 Threshold;
 404   UINT8 TBDCount;
 405   UINT8 ImmediateData[TX_BUFFER_SIZE];
 406   /* following fields are not seen by the 82557 */
 407   struct TBD {
 408     UINT32 phys_buf_addr;
 409     UINT32 buf_len;
 410     } TBDArray[MAX_XMIT_FRAGMENTS];
 411   UINT32 PhysArrayAddr;  /* in case the one in the header is lost */
 412   UINT32 PhysTCBAddress;    /* for this TCB */
 413   struct s_TxCB *NextTCBVirtualLinkPtr;
 414   struct s_TxCB *PrevTCBVirtualLinkPtr;
 415   UINT64 free_data_ptr;  // to be given to the upper layer when this xmit completes1
 416 }TxCB;
 417
 418 /* The Speedo3 Rx and Tx buffer descriptors. */
 419 #pragma pack(1)
 420 typedef struct s_RxFD {          /* Receive frame descriptor. */
 421   struct CB_Header cb_header;
 422   UINT32 rx_buf_addr;      /* VOID * */
 423   UINT16 ActualCount;
 424   UINT16 RFDSize;
 425   UINT8 RFDBuffer[RX_BUFFER_SIZE];
 426   UINT8 forwarded;
 427   UINT8 junk[3];
 428 }RxFD;
 429
 430 /* Elements of the RxFD.status word. */
 431 #define RX_COMPLETE 0x8000
 432 #define RX_FRAME_OK 0x2000
 433
 434 /* Elements of the dump_statistics block. This block must be lword aligned. */
 435 #pragma pack(1)
 436 struct speedo_stats {
 437   UINT32 tx_good_frames;
 438   UINT32 tx_coll16_errs;
 439   UINT32 tx_late_colls;
 440   UINT32 tx_underruns;
 441   UINT32 tx_lost_carrier;
 442   UINT32 tx_deferred;
 443   UINT32 tx_one_colls;
 444   UINT32 tx_multi_colls;
 445   UINT32 tx_total_colls;
 446   UINT32 rx_good_frames;
 447   UINT32 rx_crc_errs;
 448   UINT32 rx_align_errs;
 449   UINT32 rx_resource_errs;
 450   UINT32 rx_overrun_errs;
 451   UINT32 rx_colls_errs;
 452   UINT32 rx_runt_errs;
 453   UINT32 done_marker;
 454 };
 455 #pragma pack()
 456
 457
 458 struct Krn_Mem{
 459   RxFD rx_ring[RX_BUFFER_COUNT];
 460   TxCB tx_ring[TX_BUFFER_COUNT];
 461   struct speedo_stats statistics;
 462 };
 463 #define MEMORY_NEEDED  sizeof(struct Krn_Mem)
 464
 465 /* The parameters for a CmdConfigure operation.
 466    There are so many options that it would be difficult to document each bit.
 467    We mostly use the default or recommended settings.
 468 */
 469
 470 /*
 471  *--------------------------------------------------------------------------
 472  * Configuration CB Parameter Bit Definitions
 473  *--------------------------------------------------------------------------
 474  */
 475 // - Byte 0  (Default Value = 16h)
 476 #define CFIG_BYTE_COUNT    0x16       // 22 Configuration Bytes
 477
 478 //- Byte 1  (Default Value = 88h)
 479 #define CFIG_TXRX_FIFO_LIMIT  0x88
 480
 481 //- Byte 2  (Default Value = 0)
 482 #define CFIG_ADAPTIVE_IFS    0
 483
 484 //- Byte 3  (Default Value = 0, ALWAYS. This byte is RESERVED)
 485 #define CFIG_RESERVED        0
 486
 487 //- Byte 4  (Default Value = 0. Default implies that Rx DMA cannot be
 488 //-          preempted).
 489 #define CFIG_RXDMA_BYTE_COUNT      0
 490
 491 //- Byte 5  (Default Value = 80h. Default implies that Tx DMA cannot be
 492 //-          preempted. However, setting these counters is enabled.)
 493 #define CFIG_DMBC_ENABLE            0x80
 494
 495 //- Byte 6  (Default Value = 33h. Late SCB enabled, No TNO interrupts,
 496 //-          CNA interrupts and do not save bad frames.)
 497 #define CFIG_LATE_SCB               1  // BIT 0
 498 #define CFIG_TNO_INTERRUPT          0x4  // BIT 2
 499 #define CFIG_CI_INTERRUPT           0x8  // BIT 3
 500 #define CFIG_SAVE_BAD_FRAMES        0x80  // BIT_7
 501
 502 //- Byte 7  (Default Value = 7h. Discard short frames automatically and
 503 //-          attempt upto 3 retries on transmit.)
 504 #define CFIG_DISCARD_SHORTRX         0x00001
 505 #define CFIG_URUN_RETRY              BIT_1 OR BIT_2
 506
 507 //- Byte 8  (Default Value = 1. Enable MII mode.)
 508 #define CFIG_503_MII              BIT_0
 509
 510 //- Byte 9  (Default Value = 0, ALWAYS)
 511
 512 //- Byte 10 (Default Value = 2Eh)
 513 #define CFIG_NSAI                   BIT_3
 514 #define CFIG_PREAMBLE_LENGTH         BIT_5      ;- Bit 5-4  = 1-0
 515 #define CFIG_NO_LOOPBACK             0
 516 #define CFIG_INTERNAL_LOOPBACK       BIT_6
 517 #define CFIG_EXT_LOOPBACK            BIT_7
 518 #define CFIG_EXT_PIN_LOOPBACK        BIT_6 OR BIT_7
 519
 520 //- Byte 11 (Default Value = 0)
 521 #define CFIG_LINEAR_PRIORITY         0
 522
 523 //- Byte 12 (Default Value = 60h)
 524 #define CFIG_LPRIORITY_MODE          0
 525 #define CFIG_IFS                     6          ;- 6 * 16 = 96
 526
 527 //- Byte 13 (Default Value = 0, ALWAYS)
 528
 529 //- Byte 14 (Default Value = 0F2h, ALWAYS)
 530
 531 //- Byte 15 (Default Value = E8h)
 532 #define CFIG_PROMISCUOUS_MODE        BIT_0
 533 #define CFIG_BROADCAST_DISABLE       BIT_1
 534 #define CFIG_CRS_CDT                 BIT_7
 535
 536 //- Byte 16 (Default Value = 0, ALWAYS)
 537
 538 //- Byte 17 (Default Value = 40h, ALWAYS)
 539
 540 //- Byte 18 (Default Value = F2h)
 541 #define CFIG_STRIPPING               BIT_0
 542 #define CFIG_PADDING                 BIT_1
 543 #define CFIG_RX_CRC_TRANSFER         BIT_2
 544
 545 //- Byte 19 (Default Value = 80h)
 546 #define CFIG_FORCE_FDX               BIT_6
 547 #define CFIG_FDX_PIN_ENABLE          BIT_7
 548
 549 //- Byte 20 (Default Value = 3Fh)
 550 #define CFIG_MULTI_IA                BIT_6
 551
 552 //- Byte 21 (Default Value = 05)
 553 #define CFIG_MC_ALL                  BIT_3
 554
 555 /*-----------------------------------------------------------------------*/
 556 #define D102_REVID 0x0b
 557
 558 #define HALF_DUPLEX 1
 559 #define FULL_DUPLEX 2
 560
 561 typedef struct s_data_instance {
 562
 563   UINT16 State;  // stopped, started or initialized
 564   UINT16 Bus;
 565   UINT8 Device;
 566   UINT8 Function;
 567   UINT16 VendorID;
 568   UINT16 DeviceID;
 569   UINT16 RevID;
 570   UINT16 SubVendorID;
 571   UINT16 SubSystemID;
 572
 573   UINT8 PermNodeAddress[PXE_MAC_LENGTH];
 574   UINT8 CurrentNodeAddress[PXE_MAC_LENGTH];
 575   UINT8 BroadcastNodeAddress[PXE_MAC_LENGTH];
 576   UINT32 Config[MAX_PCI_CONFIG_LEN];
 577   UINT32 NVData[MAX_EEPROM_LEN];
 578
 579   UINT32 ioaddr;
 580   UINT32 flash_addr;
 581
 582   UINT16 LinkSpeed;     // actual link speed setting
 583   UINT16 LinkSpeedReq;  // requested (forced) link speed
 584   UINT8  DuplexReq;     // requested duplex
 585   UINT8  Duplex;        // Duplex set
 586   UINT8  CableDetect;   // 1 to detect and 0 not to detect the cable
 587   UINT8  LoopBack;
 588
 589   UINT16 TxBufCnt;
 590   UINT16 TxBufSize;
 591   UINT16 RxBufCnt;
 592   UINT16 RxBufSize;
 593   UINT32 RxTotals;
 594   UINT32 TxTotals;
 595
 596   UINT16 int_mask;
 597   UINT16 Int_Status;
 598   UINT16 PhyRecord[2];  // primary and secondary PHY record registers from eeprom
 599   UINT8  PhyAddress;
 600   UINT8  int_num;
 601   UINT16 NVData_Len;
 602   UINT32 MemoryLength;
 603
 604   RxFD *rx_ring;  // array of rx buffers
 605   TxCB *tx_ring;  // array of tx buffers
 606   struct speedo_stats *statistics;
 607   TxCB *FreeTxHeadPtr;
 608   TxCB *FreeTxTailPtr;
 609   RxFD *RFDTailPtr;
 610
 611   UINT64 rx_phy_addr;  // physical addresses
 612   UINT64 tx_phy_addr;
 613   UINT64 stat_phy_addr;
 614   UINT64 MemoryPtr;
 615   UINT64 Mapped_MemoryPtr;
 616
 617   UINT64 xmit_done[TX_BUFFER_COUNT << 1]; // circular buffer
 618   UINT16 xmit_done_head;  // index into the xmit_done array
 619   UINT16 xmit_done_tail;  // where are we filling now (index into xmit_done)
 620   UINT16 cur_rx_ind;  // current RX Q head index
 621   UINT16 FreeCBCount;
 622
 623   BOOLEAN in_interrupt;
 624   BOOLEAN in_transmit;
 625   BOOLEAN Receive_Started;
 626   UINT8 Rx_Filter;
 627   UINT8 VersionFlag;  // UNDI30 or UNDI31??
 628   UINT8 rsvd[3];
 629
 630   struct mc{
 631     UINT16 reserved [3]; // padding for this structure to make it 8 byte aligned
 632     UINT16 list_len;
 633     UINT8 mc_list[MAX_MCAST_ADDRESS_CNT][PXE_MAC_LENGTH]; // 8*32 is the size
 634   } mcast_list;
 635
 636   UINT64 Unique_ID;
 637
 638   EFI_PCI_IO_PROTOCOL   *Io_Function;
 639   //
 640   // Original PCI attributes
 641   //
 642   UINT64                OriginalPciAttributes;
 643
 644   VOID (*Delay_30)(UINTN);  // call back routine
 645   VOID (*Virt2Phys_30)(UINT64 virtual_addr, UINT64 physical_ptr);  // call back routine
 646   VOID (*Block_30)(UINT32 enable);  // call back routine
 647   VOID (*Mem_Io_30)(UINT8 read_write, UINT8 len, UINT64 port, UINT64 buf_addr);
 648   VOID (*Delay)(UINT64, UINTN);  // call back routine
 649   VOID (*Virt2Phys)(UINT64 unq_id, UINT64 virtual_addr, UINT64 physical_ptr);  // call back routine
 650   VOID (*Block)(UINT64 unq_id, UINT32 enable);  // call back routine
 651   VOID (*Mem_Io)(UINT64 unq_id, UINT8 read_write, UINT8 len, UINT64 port,
 652           UINT64 buf_addr);
 653   VOID (*Map_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
 654                    UINT32 Direction, UINT64 mapped_addr);
 655   VOID (*UnMap_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
 656             UINT32 Direction, UINT64 mapped_addr);
 657   VOID (*Sync_Mem)(UINT64 unq_id, UINT64 virtual_addr,
 658             UINT32 size, UINT32 Direction, UINT64 mapped_addr);
 659 } NIC_DATA_INSTANCE;
 660
 661 #pragma pack(1)
 662 struct MC_CB_STRUCT{
 663   UINT16 count;
 664   UINT8 m_list[MAX_MCAST_ADDRESS_CNT][ETHER_MAC_ADDR_LEN];
 665 };
 666 #pragma pack()
 667
 668 #define FOUR_GIGABYTE (UINT64)0x100000000ULL
 669
 670 #endif
 671