OvmfPkg/Include/IndustryStandard/Q35MchIch9.h

   1 /** @file
   2   Various register numbers and value bits based on the following publications:
   3   - Intel(R) datasheet 316966-002
   4   - Intel(R) datasheet 316972-004
   5
   6   Copyright (C) 2015, Red Hat, Inc.
   7   Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>
   8
   9   This program and the accompanying materials are licensed and made available
  10   under the terms and conditions of the BSD License which accompanies this
  11   distribution.   The full text of the license may be found at
  12   http://opensource.org/licenses/bsd-license.php
  13
  14   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
  15   WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  16 **/
  17
  18 #ifndef __Q35_MCH_ICH9_H__
  19 #define __Q35_MCH_ICH9_H__
  20
  21 #include <Library/PciLib.h>
  22 #include <Uefi/UefiBaseType.h>
  23 #include <Uefi/UefiSpec.h>
  24 #include <Protocol/PciRootBridgeIo.h>
  25
  26 //
  27 // Host Bridge Device ID (DID) value for Q35/MCH
  28 //
  29 #define INTEL_Q35_MCH_DEVICE_ID 0x29C0
  30
  31 //
  32 // B/D/F/Type: 0/0/0/PCI
  33 //
  34 #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
  35
  36 #define MCH_EXT_TSEG_MB       0x50
  37 #define MCH_EXT_TSEG_MB_QUERY   0xFFFF
  38
  39 #define MCH_GGC               0x52
  40 #define MCH_GGC_IVD             BIT1
  41
  42 #define MCH_PCIEXBAR_LOW      0x60
  43 #define MCH_PCIEXBAR_LOWMASK    0x0FFFFFFF
  44 #define MCH_PCIEXBAR_BUS_FF     0
  45 #define MCH_PCIEXBAR_EN         BIT0
  46
  47 #define MCH_PCIEXBAR_HIGH     0x64
  48 #define MCH_PCIEXBAR_HIGHMASK   0xFFFFFFF0
  49
  50 #define MCH_PAM0              0x90
  51 #define MCH_PAM1              0x91
  52 #define MCH_PAM2              0x92
  53 #define MCH_PAM3              0x93
  54 #define MCH_PAM4              0x94
  55 #define MCH_PAM5              0x95
  56 #define MCH_PAM6              0x96
  57
  58 #define MCH_SMRAM             0x9D
  59 #define MCH_SMRAM_D_LCK         BIT4
  60 #define MCH_SMRAM_G_SMRAME      BIT3
  61
  62 #define MCH_ESMRAMC           0x9E
  63 #define MCH_ESMRAMC_H_SMRAME    BIT7
  64 #define MCH_ESMRAMC_E_SMERR     BIT6
  65 #define MCH_ESMRAMC_SM_CACHE    BIT5
  66 #define MCH_ESMRAMC_SM_L1       BIT4
  67 #define MCH_ESMRAMC_SM_L2       BIT3
  68 #define MCH_ESMRAMC_TSEG_EXT    (BIT2 | BIT1)
  69 #define MCH_ESMRAMC_TSEG_8MB    BIT2
  70 #define MCH_ESMRAMC_TSEG_2MB    BIT1
  71 #define MCH_ESMRAMC_TSEG_1MB    0
  72 #define MCH_ESMRAMC_TSEG_MASK   (BIT2 | BIT1)
  73 #define MCH_ESMRAMC_T_EN        BIT0
  74
  75 #define MCH_GBSM              0xA4
  76 #define MCH_GBSM_MB_SHIFT       20
  77
  78 #define MCH_BGSM              0xA8
  79 #define MCH_BGSM_MB_SHIFT       20
  80
  81 #define MCH_TSEGMB            0xAC
  82 #define MCH_TSEGMB_MB_SHIFT     20
  83
  84 #define MCH_TOLUD             0xB0
  85 #define MCH_TOLUD_MB_SHIFT      4
  86
  87 //
  88 // B/D/F/Type: 0/0x1f/0/PCI
  89 //
  90 #define POWER_MGMT_REGISTER_Q35(Offset) \
  91   PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))
  92
  93 #define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) \
  94   EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset))
  95
  96 #define ICH9_PMBASE               0x40
  97 #define ICH9_PMBASE_MASK            (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
  98                                      BIT10 | BIT9  | BIT8  | BIT7)
  99
 100 #define ICH9_ACPI_CNTL            0x44
 101 #define ICH9_ACPI_CNTL_ACPI_EN      BIT7
 102
 103 #define ICH9_GEN_PMCON_1          0xA0
 104 #define ICH9_GEN_PMCON_1_SMI_LOCK   BIT4
 105
 106 #define ICH9_RCBA                 0xF0
 107 #define ICH9_RCBA_EN                BIT0
 108
 109 //
 110 // IO ports
 111 //
 112 #define ICH9_APM_CNT 0xB2
 113 #define ICH9_APM_STS 0xB3
 114
 115 //
 116 // IO ports relative to PMBASE
 117 //
 118 #define ICH9_PMBASE_OFS_SMI_EN 0x30
 119 #define ICH9_SMI_EN_APMC_EN      BIT5
 120 #define ICH9_SMI_EN_GBL_SMI_EN   BIT0
 121
 122 #define ICH9_ROOT_COMPLEX_BASE 0xFED1C000
 123
 124 #endif