OvmfPkg/Include/Register/QemuSmramSaveStateMap.h

   1 /** @file
   2 SMRAM Save State Map Definitions.
   3
   4 SMRAM Save State Map definitions based on contents of the
   5 Intel(R) 64 and IA-32 Architectures Software Developer's Manual
   6   Volume 3C, Section 34.4 SMRAM
   7   Volume 3C, Section 34.5 SMI Handler Execution Environment
   8   Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs
   9
  10 and the AMD64 Architecture Programmer's Manual
  11   Volume 2, Section 10.2 SMM Resources
  12
  13 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
  14 Copyright (c) 2015, Red Hat, Inc.<BR>
  15 SPDX-License-Identifier: BSD-2-Clause-Patent
  16
  17 **/
  18
  19 #ifndef __QEMU_SMRAM_SAVE_STATE_MAP_H__
  20 #define __QEMU_SMRAM_SAVE_STATE_MAP_H__
  21
  22 #pragma pack (1)
  23
  24 ///
  25 /// 32-bit SMRAM Save State Map
  26 ///
  27 typedef struct {
  28   UINT8   Reserved0[0x200]; // 7c00h
  29   UINT8   Reserved1[0xf8];  // 7e00h
  30   UINT32  SMBASE;           // 7ef8h
  31   UINT32  SMMRevId;         // 7efch
  32   UINT16  IORestart;        // 7f00h
  33   UINT16  AutoHALTRestart;  // 7f02h
  34   UINT8   Reserved2[0x9C];  // 7f08h
  35   UINT32  IOMemAddr;        // 7fa0h
  36   UINT32  IOMisc;           // 7fa4h
  37   UINT32  _ES;              // 7fa8h
  38   UINT32  _CS;              // 7fach
  39   UINT32  _SS;              // 7fb0h
  40   UINT32  _DS;              // 7fb4h
  41   UINT32  _FS;              // 7fb8h
  42   UINT32  _GS;              // 7fbch
  43   UINT32  Reserved3;        // 7fc0h
  44   UINT32  _TR;              // 7fc4h
  45   UINT32  _DR7;             // 7fc8h
  46   UINT32  _DR6;             // 7fcch
  47   UINT32  _EAX;             // 7fd0h
  48   UINT32  _ECX;             // 7fd4h
  49   UINT32  _EDX;             // 7fd8h
  50   UINT32  _EBX;             // 7fdch
  51   UINT32  _ESP;             // 7fe0h
  52   UINT32  _EBP;             // 7fe4h
  53   UINT32  _ESI;             // 7fe8h
  54   UINT32  _EDI;             // 7fech
  55   UINT32  _EIP;             // 7ff0h
  56   UINT32  _EFLAGS;          // 7ff4h
  57   UINT32  _CR3;             // 7ff8h
  58   UINT32  _CR0;             // 7ffch
  59 } QEMU_SMRAM_SAVE_STATE_MAP32;
  60
  61 ///
  62 /// 64-bit SMRAM Save State Map
  63 ///
  64 typedef struct {
  65   UINT8   Reserved0[0x200];  // 7c00h
  66
  67   UINT16  _ES;               // 7e00h
  68   UINT16  _ESAccessRights;   // 7e02h
  69   UINT32  _ESLimit;          // 7e04h
  70   UINT64  _ESBase;           // 7e08h
  71
  72   UINT16  _CS;               // 7e10h
  73   UINT16  _CSAccessRights;   // 7e12h
  74   UINT32  _CSLimit;          // 7e14h
  75   UINT64  _CSBase;           // 7e18h
  76
  77   UINT16  _SS;               // 7e20h
  78   UINT16  _SSAccessRights;   // 7e22h
  79   UINT32  _SSLimit;          // 7e24h
  80   UINT64  _SSBase;           // 7e28h
  81
  82   UINT16  _DS;               // 7e30h
  83   UINT16  _DSAccessRights;   // 7e32h
  84   UINT32  _DSLimit;          // 7e34h
  85   UINT64  _DSBase;           // 7e38h
  86
  87   UINT16  _FS;               // 7e40h
  88   UINT16  _FSAccessRights;   // 7e42h
  89   UINT32  _FSLimit;          // 7e44h
  90   UINT64  _FSBase;           // 7e48h
  91
  92   UINT16  _GS;               // 7e50h
  93   UINT16  _GSAccessRights;   // 7e52h
  94   UINT32  _GSLimit;          // 7e54h
  95   UINT64  _GSBase;           // 7e58h
  96
  97   UINT32  _GDTRReserved1;    // 7e60h
  98   UINT16  _GDTRLimit;        // 7e64h
  99   UINT16  _GDTRReserved2;    // 7e66h
 100   UINT64  _GDTRBase;         // 7e68h
 101
 102   UINT16  _LDTR;             // 7e70h
 103   UINT16  _LDTRAccessRights; // 7e72h
 104   UINT32  _LDTRLimit;        // 7e74h
 105   UINT64  _LDTRBase;         // 7e78h
 106
 107   UINT32  _IDTRReserved1;    // 7e80h
 108   UINT16  _IDTRLimit;        // 7e84h
 109   UINT16  _IDTRReserved2;    // 7e86h
 110   UINT64  _IDTRBase;         // 7e88h
 111
 112   UINT16  _TR;               // 7e90h
 113   UINT16  _TRAccessRights;   // 7e92h
 114   UINT32  _TRLimit;          // 7e94h
 115   UINT64  _TRBase;           // 7e98h
 116
 117   UINT64  IO_RIP;            // 7ea0h
 118   UINT64  IO_RCX;            // 7ea8h
 119   UINT64  IO_RSI;            // 7eb0h
 120   UINT64  IO_RDI;            // 7eb8h
 121   UINT32  IO_DWord;          // 7ec0h
 122   UINT8   Reserved1[0x04];   // 7ec4h
 123   UINT8   IORestart;         // 7ec8h
 124   UINT8   AutoHALTRestart;   // 7ec9h
 125   UINT8   Reserved2[0x06];   // 7ecah
 126
 127   UINT64  IA32_EFER;         // 7ed0h
 128   UINT64  SVM_Guest;         // 7ed8h
 129   UINT64  SVM_GuestVMCB;     // 7ee0h
 130   UINT64  SVM_GuestVIntr;    // 7ee8h
 131   UINT8   Reserved3[0x0c];   // 7ef0h
 132
 133   UINT32  SMMRevId;          // 7efch
 134   UINT32  SMBASE;            // 7f00h
 135
 136   UINT8   Reserved4[0x1c];   // 7f04h
 137   UINT64  SVM_GuestPAT;      // 7f20h
 138   UINT64  SVM_HostIA32_EFER; // 7f28h
 139   UINT64  SVM_HostCR4;       // 7f30h
 140   UINT64  SVM_HostCR3;       // 7f38h
 141   UINT64  SVM_HostCR0;       // 7f40h
 142
 143   UINT64  _CR4;              // 7f48h
 144   UINT64  _CR3;              // 7f50h
 145   UINT64  _CR0;              // 7f58h
 146   UINT64  _DR7;              // 7f60h
 147   UINT64  _DR6;              // 7f68h
 148   UINT64  _RFLAGS;           // 7f70h
 149   UINT64  _RIP;              // 7f78h
 150   UINT64  _R15;              // 7f80h
 151   UINT64  _R14;              // 7f88h
 152   UINT64  _R13;              // 7f90h
 153   UINT64  _R12;              // 7f98h
 154   UINT64  _R11;              // 7fa0h
 155   UINT64  _R10;              // 7fa8h
 156   UINT64  _R9;               // 7fb0h
 157   UINT64  _R8;               // 7fb8h
 158   UINT64  _RDI;              // 7fc0h
 159   UINT64  _RSI;              // 7fc8h
 160   UINT64  _RBP;              // 7fd0h
 161   UINT64  _RSP;              // 7fd8h
 162   UINT64  _RBX;              // 7fe0h
 163   UINT64  _RDX;              // 7fe8h
 164   UINT64  _RCX;              // 7ff0h
 165   UINT64  _RAX;              // 7ff8h
 166 } QEMU_SMRAM_SAVE_STATE_MAP64;
 167
 168 ///
 169 /// Union of 32-bit and 64-bit SMRAM Save State Maps
 170 ///
 171 typedef union  {
 172   QEMU_SMRAM_SAVE_STATE_MAP32  x86;
 173   QEMU_SMRAM_SAVE_STATE_MAP64  x64;
 174 } QEMU_SMRAM_SAVE_STATE_MAP;
 175
 176 #pragma pack ()
 177
 178 #endif