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1 /** @file
2
3 Virtual Memory Management Services to set or clear the memory encryption bit
4
5 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
6 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
7
8 This program and the accompanying materials are licensed and made available
9 under the terms and conditions of the BSD License which accompanies this
10 distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
14 WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
17
18 **/
19
20 #include <Library/CpuLib.h>
21 #include <Register/Amd/Cpuid.h>
22 #include <Register/Cpuid.h>
23
24 #include "VirtualMemory.h"
25
26 STATIC BOOLEAN mAddressEncMaskChecked = FALSE;
27 STATIC UINT64 mAddressEncMask;
28 STATIC PAGE_TABLE_POOL *mPageTablePool = NULL;
29
30 typedef enum {
31 SetCBit,
32 ClearCBit
33 } MAP_RANGE_MODE;
34
35 /**
36 Get the memory encryption mask
37
38 @param[out] EncryptionMask contains the pte mask.
39
40 **/
41 STATIC
42 UINT64
43 GetMemEncryptionAddressMask (
44 VOID
45 )
46 {
47 UINT64 EncryptionMask;
48 CPUID_MEMORY_ENCRYPTION_INFO_EBX Ebx;
49
50 if (mAddressEncMaskChecked) {
51 return mAddressEncMask;
52 }
53
54 //
55 // CPUID Fn8000_001F[EBX] Bit 0:5 (memory encryption bit position)
56 //
57 AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, NULL, &Ebx.Uint32, NULL, NULL);
58 EncryptionMask = LShiftU64 (1, Ebx.Bits.PtePosBits);
59
60 mAddressEncMask = EncryptionMask & PAGING_1G_ADDRESS_MASK_64;
61 mAddressEncMaskChecked = TRUE;
62
63 return mAddressEncMask;
64 }
65
66 /**
67 Initialize a buffer pool for page table use only.
68
69 To reduce the potential split operation on page table, the pages reserved for
70 page table should be allocated in the times of PAGE_TABLE_POOL_UNIT_PAGES and
71 at the boundary of PAGE_TABLE_POOL_ALIGNMENT. So the page pool is always
72 initialized with number of pages greater than or equal to the given
73 PoolPages.
74
75 Once the pages in the pool are used up, this method should be called again to
76 reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. Usually this won't
77 happen often in practice.
78
79 @param[in] PoolPages The least page number of the pool to be created.
80
81 @retval TRUE The pool is initialized successfully.
82 @retval FALSE The memory is out of resource.
83 **/
84 STATIC
85 BOOLEAN
86 InitializePageTablePool (
87 IN UINTN PoolPages
88 )
89 {
90 VOID *Buffer;
91
92 //
93 // Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for
94 // header.
95 //
96 PoolPages += 1; // Add one page for header.
97 PoolPages = ((PoolPages - 1) / PAGE_TABLE_POOL_UNIT_PAGES + 1) *
98 PAGE_TABLE_POOL_UNIT_PAGES;
99 Buffer = AllocateAlignedPages (PoolPages, PAGE_TABLE_POOL_ALIGNMENT);
100 if (Buffer == NULL) {
101 DEBUG ((DEBUG_ERROR, "ERROR: Out of aligned pages\r\n"));
102 return FALSE;
103 }
104
105 //
106 // Link all pools into a list for easier track later.
107 //
108 if (mPageTablePool == NULL) {
109 mPageTablePool = Buffer;
110 mPageTablePool->NextPool = mPageTablePool;
111 } else {
112 ((PAGE_TABLE_POOL *)Buffer)->NextPool = mPageTablePool->NextPool;
113 mPageTablePool->NextPool = Buffer;
114 mPageTablePool = Buffer;
115 }
116
117 //
118 // Reserve one page for pool header.
119 //
120 mPageTablePool->FreePages = PoolPages - 1;
121 mPageTablePool->Offset = EFI_PAGES_TO_SIZE (1);
122
123 return TRUE;
124 }
125
126 /**
127 This API provides a way to allocate memory for page table.
128
129 This API can be called more than once to allocate memory for page tables.
130
131 Allocates the number of 4KB pages and returns a pointer to the allocated
132 buffer. The buffer returned is aligned on a 4KB boundary.
133
134 If Pages is 0, then NULL is returned.
135 If there is not enough memory remaining to satisfy the request, then NULL is
136 returned.
137
138 @param Pages The number of 4 KB pages to allocate.
139
140 @return A pointer to the allocated buffer or NULL if allocation fails.
141
142 **/
143 STATIC
144 VOID *
145 EFIAPI
146 AllocatePageTableMemory (
147 IN UINTN Pages
148 )
149 {
150 VOID *Buffer;
151
152 if (Pages == 0) {
153 return NULL;
154 }
155
156 //
157 // Renew the pool if necessary.
158 //
159 if (mPageTablePool == NULL ||
160 Pages > mPageTablePool->FreePages) {
161 if (!InitializePageTablePool (Pages)) {
162 return NULL;
163 }
164 }
165
166 Buffer = (UINT8 *)mPageTablePool + mPageTablePool->Offset;
167
168 mPageTablePool->Offset += EFI_PAGES_TO_SIZE (Pages);
169 mPageTablePool->FreePages -= Pages;
170
171 DEBUG ((
172 DEBUG_VERBOSE,
173 "%a:%a: Buffer=0x%Lx Pages=%ld\n",
174 gEfiCallerBaseName,
175 __FUNCTION__,
176 Buffer,
177 Pages
178 ));
179
180 return Buffer;
181 }
182
183
184 /**
185 Split 2M page to 4K.
186
187 @param[in] PhysicalAddress Start physical address the 2M page
188 covered.
189 @param[in, out] PageEntry2M Pointer to 2M page entry.
190 @param[in] StackBase Stack base address.
191 @param[in] StackSize Stack size.
192
193 **/
194 STATIC
195 VOID
196 Split2MPageTo4K (
197 IN PHYSICAL_ADDRESS PhysicalAddress,
198 IN OUT UINT64 *PageEntry2M,
199 IN PHYSICAL_ADDRESS StackBase,
200 IN UINTN StackSize
201 )
202 {
203 PHYSICAL_ADDRESS PhysicalAddress4K;
204 UINTN IndexOfPageTableEntries;
205 PAGE_TABLE_4K_ENTRY *PageTableEntry, *PageTableEntry1;
206 UINT64 AddressEncMask;
207
208 PageTableEntry = AllocatePageTableMemory(1);
209
210 PageTableEntry1 = PageTableEntry;
211
212 AddressEncMask = GetMemEncryptionAddressMask ();
213
214 ASSERT (PageTableEntry != NULL);
215 ASSERT (*PageEntry2M & AddressEncMask);
216
217 PhysicalAddress4K = PhysicalAddress;
218 for (IndexOfPageTableEntries = 0;
219 IndexOfPageTableEntries < 512;
220 (IndexOfPageTableEntries++,
221 PageTableEntry++,
222 PhysicalAddress4K += SIZE_4KB)) {
223 //
224 // Fill in the Page Table entries
225 //
226 PageTableEntry->Uint64 = (UINT64) PhysicalAddress4K | AddressEncMask;
227 PageTableEntry->Bits.ReadWrite = 1;
228 PageTableEntry->Bits.Present = 1;
229 if ((PhysicalAddress4K >= StackBase) &&
230 (PhysicalAddress4K < StackBase + StackSize)) {
231 //
232 // Set Nx bit for stack.
233 //
234 PageTableEntry->Bits.Nx = 1;
235 }
236 }
237
238 //
239 // Fill in 2M page entry.
240 //
241 *PageEntry2M = ((UINT64)(UINTN)PageTableEntry1 |
242 IA32_PG_P | IA32_PG_RW | AddressEncMask);
243 }
244
245 /**
246 Set one page of page table pool memory to be read-only.
247
248 @param[in] PageTableBase Base address of page table (CR3).
249 @param[in] Address Start address of a page to be set as read-only.
250 @param[in] Level4Paging Level 4 paging flag.
251
252 **/
253 STATIC
254 VOID
255 SetPageTablePoolReadOnly (
256 IN UINTN PageTableBase,
257 IN EFI_PHYSICAL_ADDRESS Address,
258 IN BOOLEAN Level4Paging
259 )
260 {
261 UINTN Index;
262 UINTN EntryIndex;
263 UINT64 AddressEncMask;
264 EFI_PHYSICAL_ADDRESS PhysicalAddress;
265 UINT64 *PageTable;
266 UINT64 *NewPageTable;
267 UINT64 PageAttr;
268 UINT64 LevelSize[5];
269 UINT64 LevelMask[5];
270 UINTN LevelShift[5];
271 UINTN Level;
272 UINT64 PoolUnitSize;
273
274 ASSERT (PageTableBase != 0);
275
276 //
277 // Since the page table is always from page table pool, which is always
278 // located at the boundary of PcdPageTablePoolAlignment, we just need to
279 // set the whole pool unit to be read-only.
280 //
281 Address = Address & PAGE_TABLE_POOL_ALIGN_MASK;
282
283 LevelShift[1] = PAGING_L1_ADDRESS_SHIFT;
284 LevelShift[2] = PAGING_L2_ADDRESS_SHIFT;
285 LevelShift[3] = PAGING_L3_ADDRESS_SHIFT;
286 LevelShift[4] = PAGING_L4_ADDRESS_SHIFT;
287
288 LevelMask[1] = PAGING_4K_ADDRESS_MASK_64;
289 LevelMask[2] = PAGING_2M_ADDRESS_MASK_64;
290 LevelMask[3] = PAGING_1G_ADDRESS_MASK_64;
291 LevelMask[4] = PAGING_1G_ADDRESS_MASK_64;
292
293 LevelSize[1] = SIZE_4KB;
294 LevelSize[2] = SIZE_2MB;
295 LevelSize[3] = SIZE_1GB;
296 LevelSize[4] = SIZE_512GB;
297
298 AddressEncMask = GetMemEncryptionAddressMask() &
299 PAGING_1G_ADDRESS_MASK_64;
300 PageTable = (UINT64 *)(UINTN)PageTableBase;
301 PoolUnitSize = PAGE_TABLE_POOL_UNIT_SIZE;
302
303 for (Level = (Level4Paging) ? 4 : 3; Level > 0; --Level) {
304 Index = ((UINTN)RShiftU64 (Address, LevelShift[Level]));
305 Index &= PAGING_PAE_INDEX_MASK;
306
307 PageAttr = PageTable[Index];
308 if ((PageAttr & IA32_PG_PS) == 0) {
309 //
310 // Go to next level of table.
311 //
312 PageTable = (UINT64 *)(UINTN)(PageAttr & ~AddressEncMask &
313 PAGING_4K_ADDRESS_MASK_64);
314 continue;
315 }
316
317 if (PoolUnitSize >= LevelSize[Level]) {
318 //
319 // Clear R/W bit if current page granularity is not larger than pool unit
320 // size.
321 //
322 if ((PageAttr & IA32_PG_RW) != 0) {
323 while (PoolUnitSize > 0) {
324 //
325 // PAGE_TABLE_POOL_UNIT_SIZE and PAGE_TABLE_POOL_ALIGNMENT are fit in
326 // one page (2MB). Then we don't need to update attributes for pages
327 // crossing page directory. ASSERT below is for that purpose.
328 //
329 ASSERT (Index < EFI_PAGE_SIZE/sizeof (UINT64));
330
331 PageTable[Index] &= ~(UINT64)IA32_PG_RW;
332 PoolUnitSize -= LevelSize[Level];
333
334 ++Index;
335 }
336 }
337
338 break;
339
340 } else {
341 //
342 // The smaller granularity of page must be needed.
343 //
344 ASSERT (Level > 1);
345
346 NewPageTable = AllocatePageTableMemory (1);
347 ASSERT (NewPageTable != NULL);
348
349 PhysicalAddress = PageAttr & LevelMask[Level];
350 for (EntryIndex = 0;
351 EntryIndex < EFI_PAGE_SIZE/sizeof (UINT64);
352 ++EntryIndex) {
353 NewPageTable[EntryIndex] = PhysicalAddress | AddressEncMask |
354 IA32_PG_P | IA32_PG_RW;
355 if (Level > 2) {
356 NewPageTable[EntryIndex] |= IA32_PG_PS;
357 }
358 PhysicalAddress += LevelSize[Level - 1];
359 }
360
361 PageTable[Index] = (UINT64)(UINTN)NewPageTable | AddressEncMask |
362 IA32_PG_P | IA32_PG_RW;
363 PageTable = NewPageTable;
364 }
365 }
366 }
367
368 /**
369 Prevent the memory pages used for page table from been overwritten.
370
371 @param[in] PageTableBase Base address of page table (CR3).
372 @param[in] Level4Paging Level 4 paging flag.
373
374 **/
375 STATIC
376 VOID
377 EnablePageTableProtection (
378 IN UINTN PageTableBase,
379 IN BOOLEAN Level4Paging
380 )
381 {
382 PAGE_TABLE_POOL *HeadPool;
383 PAGE_TABLE_POOL *Pool;
384 UINT64 PoolSize;
385 EFI_PHYSICAL_ADDRESS Address;
386
387 if (mPageTablePool == NULL) {
388 return;
389 }
390
391 //
392 // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to
393 // remember original one in advance.
394 //
395 HeadPool = mPageTablePool;
396 Pool = HeadPool;
397 do {
398 Address = (EFI_PHYSICAL_ADDRESS)(UINTN)Pool;
399 PoolSize = Pool->Offset + EFI_PAGES_TO_SIZE (Pool->FreePages);
400
401 //
402 // The size of one pool must be multiple of PAGE_TABLE_POOL_UNIT_SIZE,
403 // which is one of page size of the processor (2MB by default). Let's apply
404 // the protection to them one by one.
405 //
406 while (PoolSize > 0) {
407 SetPageTablePoolReadOnly(PageTableBase, Address, Level4Paging);
408 Address += PAGE_TABLE_POOL_UNIT_SIZE;
409 PoolSize -= PAGE_TABLE_POOL_UNIT_SIZE;
410 }
411
412 Pool = Pool->NextPool;
413 } while (Pool != HeadPool);
414
415 }
416
417
418 /**
419 Split 1G page to 2M.
420
421 @param[in] PhysicalAddress Start physical address the 1G page
422 covered.
423 @param[in, out] PageEntry1G Pointer to 1G page entry.
424 @param[in] StackBase Stack base address.
425 @param[in] StackSize Stack size.
426
427 **/
428 STATIC
429 VOID
430 Split1GPageTo2M (
431 IN PHYSICAL_ADDRESS PhysicalAddress,
432 IN OUT UINT64 *PageEntry1G,
433 IN PHYSICAL_ADDRESS StackBase,
434 IN UINTN StackSize
435 )
436 {
437 PHYSICAL_ADDRESS PhysicalAddress2M;
438 UINTN IndexOfPageDirectoryEntries;
439 PAGE_TABLE_ENTRY *PageDirectoryEntry;
440 UINT64 AddressEncMask;
441
442 PageDirectoryEntry = AllocatePageTableMemory(1);
443
444 AddressEncMask = GetMemEncryptionAddressMask ();
445 ASSERT (PageDirectoryEntry != NULL);
446 ASSERT (*PageEntry1G & GetMemEncryptionAddressMask ());
447 //
448 // Fill in 1G page entry.
449 //
450 *PageEntry1G = ((UINT64)(UINTN)PageDirectoryEntry |
451 IA32_PG_P | IA32_PG_RW | AddressEncMask);
452
453 PhysicalAddress2M = PhysicalAddress;
454 for (IndexOfPageDirectoryEntries = 0;
455 IndexOfPageDirectoryEntries < 512;
456 (IndexOfPageDirectoryEntries++,
457 PageDirectoryEntry++,
458 PhysicalAddress2M += SIZE_2MB)) {
459 if ((PhysicalAddress2M < StackBase + StackSize) &&
460 ((PhysicalAddress2M + SIZE_2MB) > StackBase)) {
461 //
462 // Need to split this 2M page that covers stack range.
463 //
464 Split2MPageTo4K (
465 PhysicalAddress2M,
466 (UINT64 *)PageDirectoryEntry,
467 StackBase,
468 StackSize
469 );
470 } else {
471 //
472 // Fill in the Page Directory entries
473 //
474 PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress2M | AddressEncMask;
475 PageDirectoryEntry->Bits.ReadWrite = 1;
476 PageDirectoryEntry->Bits.Present = 1;
477 PageDirectoryEntry->Bits.MustBe1 = 1;
478 }
479 }
480 }
481
482
483 /**
484 Set or Clear the memory encryption bit
485
486 @param[in] PagetablePoint Page table entry pointer (PTE).
487 @param[in] Mode Set or Clear encryption bit
488
489 **/
490 STATIC VOID
491 SetOrClearCBit(
492 IN OUT UINT64* PageTablePointer,
493 IN MAP_RANGE_MODE Mode
494 )
495 {
496 UINT64 AddressEncMask;
497
498 AddressEncMask = GetMemEncryptionAddressMask ();
499
500 if (Mode == SetCBit) {
501 *PageTablePointer |= AddressEncMask;
502 } else {
503 *PageTablePointer &= ~AddressEncMask;
504 }
505
506 }
507
508 /**
509 Check the WP status in CR0 register. This bit is used to lock or unlock write
510 access to pages marked as read-only.
511
512 @retval TRUE Write protection is enabled.
513 @retval FALSE Write protection is disabled.
514 **/
515 STATIC
516 BOOLEAN
517 IsReadOnlyPageWriteProtected (
518 VOID
519 )
520 {
521 return ((AsmReadCr0 () & BIT16) != 0);
522 }
523
524
525 /**
526 Disable Write Protect on pages marked as read-only.
527 **/
528 STATIC
529 VOID
530 DisableReadOnlyPageWriteProtect (
531 VOID
532 )
533 {
534 AsmWriteCr0 (AsmReadCr0() & ~BIT16);
535 }
536
537 /**
538 Enable Write Protect on pages marked as read-only.
539 **/
540 VOID
541 EnableReadOnlyPageWriteProtect (
542 VOID
543 )
544 {
545 AsmWriteCr0 (AsmReadCr0() | BIT16);
546 }
547
548
549 /**
550 This function either sets or clears memory encryption bit for the memory
551 region specified by PhysicalAddress and Length from the current page table
552 context.
553
554 The function iterates through the PhysicalAddress one page at a time, and set
555 or clears the memory encryption mask in the page table. If it encounters
556 that a given physical address range is part of large page then it attempts to
557 change the attribute at one go (based on size), otherwise it splits the
558 large pages into smaller (e.g 2M page into 4K pages) and then try to set or
559 clear the encryption bit on the smallest page size.
560
561 @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use
562 current CR3)
563 @param[in] PhysicalAddress The physical address that is the start
564 address of a memory region.
565 @param[in] Length The length of memory region
566 @param[in] Mode Set or Clear mode
567 @param[in] CacheFlush Flush the caches before applying the
568 encryption mask
569
570 @retval RETURN_SUCCESS The attributes were cleared for the
571 memory region.
572 @retval RETURN_INVALID_PARAMETER Number of pages is zero.
573 @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute
574 is not supported
575 **/
576
577 STATIC
578 RETURN_STATUS
579 EFIAPI
580 SetMemoryEncDec (
581 IN PHYSICAL_ADDRESS Cr3BaseAddress,
582 IN PHYSICAL_ADDRESS PhysicalAddress,
583 IN UINTN Length,
584 IN MAP_RANGE_MODE Mode,
585 IN BOOLEAN CacheFlush
586 )
587 {
588 PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry;
589 PAGE_MAP_AND_DIRECTORY_POINTER *PageUpperDirectoryPointerEntry;
590 PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;
591 PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
592 PAGE_TABLE_ENTRY *PageDirectory2MEntry;
593 PAGE_TABLE_4K_ENTRY *PageTableEntry;
594 UINT64 PgTableMask;
595 UINT64 AddressEncMask;
596 BOOLEAN IsWpEnabled;
597 RETURN_STATUS Status;
598
599 //
600 // Set PageMapLevel4Entry to suppress incorrect compiler/analyzer warnings.
601 //
602 PageMapLevel4Entry = NULL;
603
604 DEBUG ((
605 DEBUG_VERBOSE,
606 "%a:%a: Cr3Base=0x%Lx Physical=0x%Lx Length=0x%Lx Mode=%a CacheFlush=%u\n",
607 gEfiCallerBaseName,
608 __FUNCTION__,
609 Cr3BaseAddress,
610 PhysicalAddress,
611 (UINT64)Length,
612 (Mode == SetCBit) ? "Encrypt" : "Decrypt",
613 (UINT32)CacheFlush
614 ));
615
616 //
617 // Check if we have a valid memory encryption mask
618 //
619 AddressEncMask = GetMemEncryptionAddressMask ();
620 if (!AddressEncMask) {
621 return RETURN_ACCESS_DENIED;
622 }
623
624 PgTableMask = AddressEncMask | EFI_PAGE_MASK;
625
626 if (Length == 0) {
627 return RETURN_INVALID_PARAMETER;
628 }
629
630 //
631 // We are going to change the memory encryption attribute from C=0 -> C=1 or
632 // vice versa Flush the caches to ensure that data is written into memory
633 // with correct C-bit
634 //
635 if (CacheFlush) {
636 WriteBackInvalidateDataCacheRange((VOID*) (UINTN)PhysicalAddress, Length);
637 }
638
639 //
640 // Make sure that the page table is changeable.
641 //
642 IsWpEnabled = IsReadOnlyPageWriteProtected ();
643 if (IsWpEnabled) {
644 DisableReadOnlyPageWriteProtect ();
645 }
646
647 Status = EFI_SUCCESS;
648
649 while (Length)
650 {
651 //
652 // If Cr3BaseAddress is not specified then read the current CR3
653 //
654 if (Cr3BaseAddress == 0) {
655 Cr3BaseAddress = AsmReadCr3();
656 }
657
658 PageMapLevel4Entry = (VOID*) (Cr3BaseAddress & ~PgTableMask);
659 PageMapLevel4Entry += PML4_OFFSET(PhysicalAddress);
660 if (!PageMapLevel4Entry->Bits.Present) {
661 DEBUG ((
662 DEBUG_ERROR,
663 "%a:%a: bad PML4 for Physical=0x%Lx\n",
664 gEfiCallerBaseName,
665 __FUNCTION__,
666 PhysicalAddress
667 ));
668 Status = RETURN_NO_MAPPING;
669 goto Done;
670 }
671
672 PageDirectory1GEntry = (VOID *)(
673 (PageMapLevel4Entry->Bits.PageTableBaseAddress <<
674 12) & ~PgTableMask
675 );
676 PageDirectory1GEntry += PDP_OFFSET(PhysicalAddress);
677 if (!PageDirectory1GEntry->Bits.Present) {
678 DEBUG ((
679 DEBUG_ERROR,
680 "%a:%a: bad PDPE for Physical=0x%Lx\n",
681 gEfiCallerBaseName,
682 __FUNCTION__,
683 PhysicalAddress
684 ));
685 Status = RETURN_NO_MAPPING;
686 goto Done;
687 }
688
689 //
690 // If the MustBe1 bit is not 1, it's not actually a 1GB entry
691 //
692 if (PageDirectory1GEntry->Bits.MustBe1) {
693 //
694 // Valid 1GB page
695 // If we have at least 1GB to go, we can just update this entry
696 //
697 if (!(PhysicalAddress & (BIT30 - 1)) && Length >= BIT30) {
698 SetOrClearCBit(&PageDirectory1GEntry->Uint64, Mode);
699 DEBUG ((
700 DEBUG_VERBOSE,
701 "%a:%a: updated 1GB entry for Physical=0x%Lx\n",
702 gEfiCallerBaseName,
703 __FUNCTION__,
704 PhysicalAddress
705 ));
706 PhysicalAddress += BIT30;
707 Length -= BIT30;
708 } else {
709 //
710 // We must split the page
711 //
712 DEBUG ((
713 DEBUG_VERBOSE,
714 "%a:%a: splitting 1GB page for Physical=0x%Lx\n",
715 gEfiCallerBaseName,
716 __FUNCTION__,
717 PhysicalAddress
718 ));
719 Split1GPageTo2M (
720 (UINT64)PageDirectory1GEntry->Bits.PageTableBaseAddress << 30,
721 (UINT64 *)PageDirectory1GEntry,
722 0,
723 0
724 );
725 continue;
726 }
727 } else {
728 //
729 // Actually a PDP
730 //
731 PageUpperDirectoryPointerEntry =
732 (PAGE_MAP_AND_DIRECTORY_POINTER *)PageDirectory1GEntry;
733 PageDirectory2MEntry =
734 (VOID *)(
735 (PageUpperDirectoryPointerEntry->Bits.PageTableBaseAddress <<
736 12) & ~PgTableMask
737 );
738 PageDirectory2MEntry += PDE_OFFSET(PhysicalAddress);
739 if (!PageDirectory2MEntry->Bits.Present) {
740 DEBUG ((
741 DEBUG_ERROR,
742 "%a:%a: bad PDE for Physical=0x%Lx\n",
743 gEfiCallerBaseName,
744 __FUNCTION__,
745 PhysicalAddress
746 ));
747 Status = RETURN_NO_MAPPING;
748 goto Done;
749 }
750 //
751 // If the MustBe1 bit is not a 1, it's not a 2MB entry
752 //
753 if (PageDirectory2MEntry->Bits.MustBe1) {
754 //
755 // Valid 2MB page
756 // If we have at least 2MB left to go, we can just update this entry
757 //
758 if (!(PhysicalAddress & (BIT21-1)) && Length >= BIT21) {
759 SetOrClearCBit (&PageDirectory2MEntry->Uint64, Mode);
760 PhysicalAddress += BIT21;
761 Length -= BIT21;
762 } else {
763 //
764 // We must split up this page into 4K pages
765 //
766 DEBUG ((
767 DEBUG_VERBOSE,
768 "%a:%a: splitting 2MB page for Physical=0x%Lx\n",
769 gEfiCallerBaseName,
770 __FUNCTION__,
771 PhysicalAddress
772 ));
773 Split2MPageTo4K (
774 (UINT64)PageDirectory2MEntry->Bits.PageTableBaseAddress << 21,
775 (UINT64 *)PageDirectory2MEntry,
776 0,
777 0
778 );
779 continue;
780 }
781 } else {
782 PageDirectoryPointerEntry =
783 (PAGE_MAP_AND_DIRECTORY_POINTER *)PageDirectory2MEntry;
784 PageTableEntry =
785 (VOID *)(
786 (PageDirectoryPointerEntry->Bits.PageTableBaseAddress <<
787 12) & ~PgTableMask
788 );
789 PageTableEntry += PTE_OFFSET(PhysicalAddress);
790 if (!PageTableEntry->Bits.Present) {
791 DEBUG ((
792 DEBUG_ERROR,
793 "%a:%a: bad PTE for Physical=0x%Lx\n",
794 gEfiCallerBaseName,
795 __FUNCTION__,
796 PhysicalAddress
797 ));
798 Status = RETURN_NO_MAPPING;
799 goto Done;
800 }
801 SetOrClearCBit (&PageTableEntry->Uint64, Mode);
802 PhysicalAddress += EFI_PAGE_SIZE;
803 Length -= EFI_PAGE_SIZE;
804 }
805 }
806 }
807
808 //
809 // Protect the page table by marking the memory used for page table to be
810 // read-only.
811 //
812 if (IsWpEnabled) {
813 EnablePageTableProtection ((UINTN)PageMapLevel4Entry, TRUE);
814 }
815
816 //
817 // Flush TLB
818 //
819 CpuFlushTlb();
820
821 Done:
822 //
823 // Restore page table write protection, if any.
824 //
825 if (IsWpEnabled) {
826 EnableReadOnlyPageWriteProtect ();
827 }
828
829 return Status;
830 }
831
832 /**
833 This function clears memory encryption bit for the memory region specified by
834 PhysicalAddress and Length from the current page table context.
835
836 @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use
837 current CR3)
838 @param[in] PhysicalAddress The physical address that is the start
839 address of a memory region.
840 @param[in] Length The length of memory region
841 @param[in] Flush Flush the caches before applying the
842 encryption mask
843
844 @retval RETURN_SUCCESS The attributes were cleared for the
845 memory region.
846 @retval RETURN_INVALID_PARAMETER Number of pages is zero.
847 @retval RETURN_UNSUPPORTED Clearing the memory encyrption attribute
848 is not supported
849 **/
850 RETURN_STATUS
851 EFIAPI
852 InternalMemEncryptSevSetMemoryDecrypted (
853 IN PHYSICAL_ADDRESS Cr3BaseAddress,
854 IN PHYSICAL_ADDRESS PhysicalAddress,
855 IN UINTN Length,
856 IN BOOLEAN Flush
857 )
858 {
859
860 return SetMemoryEncDec (
861 Cr3BaseAddress,
862 PhysicalAddress,
863 Length,
864 ClearCBit,
865 Flush
866 );
867 }
868
869 /**
870 This function sets memory encryption bit for the memory region specified by
871 PhysicalAddress and Length from the current page table context.
872
873 @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use
874 current CR3)
875 @param[in] PhysicalAddress The physical address that is the start
876 address of a memory region.
877 @param[in] Length The length of memory region
878 @param[in] Flush Flush the caches before applying the
879 encryption mask
880
881 @retval RETURN_SUCCESS The attributes were set for the memory
882 region.
883 @retval RETURN_INVALID_PARAMETER Number of pages is zero.
884 @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute
885 is not supported
886 **/
887 RETURN_STATUS
888 EFIAPI
889 InternalMemEncryptSevSetMemoryEncrypted (
890 IN PHYSICAL_ADDRESS Cr3BaseAddress,
891 IN PHYSICAL_ADDRESS PhysicalAddress,
892 IN UINTN Length,
893 IN BOOLEAN Flush
894 )
895 {
896 return SetMemoryEncDec (
897 Cr3BaseAddress,
898 PhysicalAddress,
899 Length,
900 SetCBit,
901 Flush
902 );
903 }
EFI Development Kit II mirror for PVE