OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h

   1 /** @file
   2
   3   Virtual Memory Management Services to set or clear the memory encryption bit
   4
   5 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   6 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
   7
   8 This program and the accompanying materials
   9 are licensed and made available under the terms and conditions of the BSD License
  10 which accompanies this distribution.  The full text of the license may be found at
  11 http://opensource.org/licenses/bsd-license.php
  12
  13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15
  16 Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
  17
  18 **/
  19
  20 #ifndef __VIRTUAL_MEMORY__
  21 #define __VIRTUAL_MEMORY__
  22
  23 #include <Uefi.h>
  24 #include <Library/BaseLib.h>
  25 #include <Library/BaseMemoryLib.h>
  26 #include <Library/DebugLib.h>
  27 #include <Library/MemoryAllocationLib.h>
  28
  29 #include <Library/CacheMaintenanceLib.h>
  30 #define SYS_CODE64_SEL 0x38
  31
  32 #pragma pack(1)
  33
  34 //
  35 // Page-Map Level-4 Offset (PML4) and
  36 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  37 //
  38
  39 typedef union {
  40   struct {
  41     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  42     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  43     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  44     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  45     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  46     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  47     UINT64  Reserved:1;               // Reserved
  48     UINT64  MustBeZero:2;             // Must Be Zero
  49     UINT64  Available:3;              // Available for use by system software
  50     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  51     UINT64  AvabilableHigh:11;        // Available for use by system software
  52     UINT64  Nx:1;                     // No Execute bit
  53   } Bits;
  54   UINT64    Uint64;
  55 } PAGE_MAP_AND_DIRECTORY_POINTER;
  56
  57 //
  58 // Page Table Entry 4KB
  59 //
  60 typedef union {
  61   struct {
  62     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  63     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  64     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  65     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  66     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  67     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  68     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
  69     UINT64  PAT:1;                    //
  70     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  71     UINT64  Available:3;              // Available for use by system software
  72     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  73     UINT64  AvabilableHigh:11;        // Available for use by system software
  74     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
  75   } Bits;
  76   UINT64    Uint64;
  77 } PAGE_TABLE_4K_ENTRY;
  78
  79 //
  80 // Page Table Entry 2MB
  81 //
  82 typedef union {
  83   struct {
  84     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  85     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  86     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  87     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  88     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  89     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  90     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
  91     UINT64  MustBe1:1;                // Must be 1
  92     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  93     UINT64  Available:3;              // Available for use by system software
  94     UINT64  PAT:1;                    //
  95     UINT64  MustBeZero:8;             // Must be zero;
  96     UINT64  PageTableBaseAddress:31;  // Page Table Base Address
  97     UINT64  AvabilableHigh:11;        // Available for use by system software
  98     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
  99   } Bits;
 100   UINT64    Uint64;
 101 } PAGE_TABLE_ENTRY;
 102
 103 //
 104 // Page Table Entry 1GB
 105 //
 106 typedef union {
 107   struct {
 108     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
 109     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
 110     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
 111     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
 112     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
 113     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
 114     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
 115     UINT64  MustBe1:1;                // Must be 1
 116     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
 117     UINT64  Available:3;              // Available for use by system software
 118     UINT64  PAT:1;                    //
 119     UINT64  MustBeZero:17;            // Must be zero;
 120     UINT64  PageTableBaseAddress:22;  // Page Table Base Address
 121     UINT64  AvabilableHigh:11;        // Available for use by system software
 122     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
 123   } Bits;
 124   UINT64    Uint64;
 125 } PAGE_TABLE_1G_ENTRY;
 126
 127 #pragma pack()
 128
 129 #define IA32_PG_P                   BIT0
 130 #define IA32_PG_RW                  BIT1
 131
 132 #define PAGETABLE_ENTRY_MASK        ((1UL << 9) - 1)
 133 #define PML4_OFFSET(x)              ( (x >> 39) & PAGETABLE_ENTRY_MASK)
 134 #define PDP_OFFSET(x)               ( (x >> 30) & PAGETABLE_ENTRY_MASK)
 135 #define PDE_OFFSET(x)               ( (x >> 21) & PAGETABLE_ENTRY_MASK)
 136 #define PTE_OFFSET(x)               ( (x >> 12) & PAGETABLE_ENTRY_MASK)
 137 #define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull
 138
 139 /**
 140   This function clears memory encryption bit for the memory region specified by PhysicalAddress
 141   and length from the current page table context.
 142
 143   @param[in]  PhysicalAddress         The physical address that is the start address of a memory region.
 144   @param[in]  Length                  The length of memory region
 145   @param[in]  Flush                   Flush the caches before applying the encryption mask
 146
 147   @retval RETURN_SUCCESS              The attributes were cleared for the memory region.
 148   @retval RETURN_INVALID_PARAMETER    Number of pages is zero.
 149   @retval RETURN_UNSUPPORTED          Setting the memory encyrption attribute is not supported
 150 **/
 151 RETURN_STATUS
 152 EFIAPI
 153 InternalMemEncryptSevSetMemoryDecrypted (
 154   IN  PHYSICAL_ADDRESS     Cr3BaseAddress,
 155   IN  PHYSICAL_ADDRESS     PhysicalAddress,
 156   IN  UINT64               Length,
 157   IN  BOOLEAN              CacheFlush
 158   );
 159
 160 /**
 161   This function sets memory encryption bit for the memory region specified by
 162   PhysicalAddress and length from the current page table context.
 163
 164   @param[in]  PhysicalAddress         The physical address that is the start address
 165                                       of a memory region.
 166   @param[in]  Length                  The length of memory region
 167   @param[in]  Flush                   Flush the caches before applying the
 168                                       encryption mask
 169
 170   @retval RETURN_SUCCESS              The attributes were cleared for the memory region.
 171   @retval RETURN_INVALID_PARAMETER    Number of pages is zero.
 172   @retval RETURN_UNSUPPORTED          Setting the memory encyrption attribute is
 173                                       not supported
 174 **/
 175 RETURN_STATUS
 176 EFIAPI
 177 InternalMemEncryptSevSetMemoryEncrypted (
 178   IN  PHYSICAL_ADDRESS     Cr3BaseAddress,
 179   IN  PHYSICAL_ADDRESS     PhysicalAddress,
 180   IN  UINT64               Length,
 181   IN  BOOLEAN              CacheFlush
 182   );
 183
 184 #endif