OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h

   1 /** @file
   2
   3   Virtual Memory Management Services to set or clear the memory encryption bit
   4
   5   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   6   Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
   7
   8   This program and the accompanying materials are licensed and made available
   9   under the terms and conditions of the BSD License which accompanies this
  10   distribution.  The full text of the license may be found at
  11   http://opensource.org/licenses/bsd-license.php
  12
  13   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
  14   WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15
  16   Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
  17
  18 **/
  19
  20 #ifndef __VIRTUAL_MEMORY__
  21 #define __VIRTUAL_MEMORY__
  22
  23 #include <Uefi.h>
  24 #include <Library/BaseLib.h>
  25 #include <Library/BaseMemoryLib.h>
  26 #include <Library/DebugLib.h>
  27 #include <Library/MemoryAllocationLib.h>
  28
  29 #include <Library/CacheMaintenanceLib.h>
  30 #define SYS_CODE64_SEL 0x38
  31
  32 #pragma pack(1)
  33
  34 //
  35 // Page-Map Level-4 Offset (PML4) and
  36 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  37 //
  38
  39 typedef union {
  40   struct {
  41     UINT64  Present:1;                // 0 = Not present in memory,
  42                                       //   1 = Present in memory
  43     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  44     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  45     UINT64  WriteThrough:1;           // 0 = Write-Back caching,
  46                                       //   1 = Write-Through caching
  47     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  48     UINT64  Accessed:1;               // 0 = Not accessed,
  49                                       //   1 = Accessed (set by CPU)
  50     UINT64  Reserved:1;               // Reserved
  51     UINT64  MustBeZero:2;             // Must Be Zero
  52     UINT64  Available:3;              // Available for use by system software
  53     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  54     UINT64  AvabilableHigh:11;        // Available for use by system software
  55     UINT64  Nx:1;                     // No Execute bit
  56   } Bits;
  57   UINT64    Uint64;
  58 } PAGE_MAP_AND_DIRECTORY_POINTER;
  59
  60 //
  61 // Page Table Entry 4KB
  62 //
  63 typedef union {
  64   struct {
  65     UINT64  Present:1;                // 0 = Not present in memory,
  66                                       //   1 = Present in memory
  67     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  68     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  69     UINT64  WriteThrough:1;           // 0 = Write-Back caching,
  70                                       //   1 = Write-Through caching
  71     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  72     UINT64  Accessed:1;               // 0 = Not accessed,
  73                                       //   1 = Accessed (set by CPU)
  74     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by
  75                                       //   processor on access to page
  76     UINT64  PAT:1;                    //
  77     UINT64  Global:1;                 // 0 = Not global page, 1 = global page
  78                                       //   TLB not cleared on CR3 write
  79     UINT64  Available:3;              // Available for use by system software
  80     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  81     UINT64  AvabilableHigh:11;        // Available for use by system software
  82     UINT64  Nx:1;                     // 0 = Execute Code,
  83                                       //   1 = No Code Execution
  84   } Bits;
  85   UINT64    Uint64;
  86 } PAGE_TABLE_4K_ENTRY;
  87
  88 //
  89 // Page Table Entry 2MB
  90 //
  91 typedef union {
  92   struct {
  93     UINT64  Present:1;                // 0 = Not present in memory,
  94                                       //   1 = Present in memory
  95     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  96     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  97     UINT64  WriteThrough:1;           // 0 = Write-Back caching,
  98                                       //   1=Write-Through caching
  99     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
 100     UINT64  Accessed:1;               // 0 = Not accessed,
 101                                       //   1 = Accessed (set by CPU)
 102     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by
 103                                       //   processor on access to page
 104     UINT64  MustBe1:1;                // Must be 1
 105     UINT64  Global:1;                 // 0 = Not global page, 1 = global page
 106                                       //   TLB not cleared on CR3 write
 107     UINT64  Available:3;              // Available for use by system software
 108     UINT64  PAT:1;                    //
 109     UINT64  MustBeZero:8;             // Must be zero;
 110     UINT64  PageTableBaseAddress:31;  // Page Table Base Address
 111     UINT64  AvabilableHigh:11;        // Available for use by system software
 112     UINT64  Nx:1;                     // 0 = Execute Code,
 113                                       //   1 = No Code Execution
 114   } Bits;
 115   UINT64    Uint64;
 116 } PAGE_TABLE_ENTRY;
 117
 118 //
 119 // Page Table Entry 1GB
 120 //
 121 typedef union {
 122   struct {
 123     UINT64  Present:1;                // 0 = Not present in memory,
 124                                       //   1 = Present in memory
 125     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
 126     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
 127     UINT64  WriteThrough:1;           // 0 = Write-Back caching,
 128                                       //   1 = Write-Through caching
 129     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
 130     UINT64  Accessed:1;               // 0 = Not accessed,
 131                                       //   1 = Accessed (set by CPU)
 132     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by
 133                                       //   processor on access to page
 134     UINT64  MustBe1:1;                // Must be 1
 135     UINT64  Global:1;                 // 0 = Not global page, 1 = global page
 136                                       //   TLB not cleared on CR3 write
 137     UINT64  Available:3;              // Available for use by system software
 138     UINT64  PAT:1;                    //
 139     UINT64  MustBeZero:17;            // Must be zero;
 140     UINT64  PageTableBaseAddress:22;  // Page Table Base Address
 141     UINT64  AvabilableHigh:11;        // Available for use by system software
 142     UINT64  Nx:1;                     // 0 = Execute Code,
 143                                       //   1 = No Code Execution
 144   } Bits;
 145   UINT64    Uint64;
 146 } PAGE_TABLE_1G_ENTRY;
 147
 148 #pragma pack()
 149
 150 #define IA32_PG_P                   BIT0
 151 #define IA32_PG_RW                  BIT1
 152 #define IA32_PG_PS                  BIT7
 153
 154 #define PAGING_PAE_INDEX_MASK       0x1FF
 155
 156 #define PAGING_4K_ADDRESS_MASK_64   0x000FFFFFFFFFF000ull
 157 #define PAGING_2M_ADDRESS_MASK_64   0x000FFFFFFFE00000ull
 158 #define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull
 159
 160 #define PAGING_L1_ADDRESS_SHIFT     12
 161 #define PAGING_L2_ADDRESS_SHIFT     21
 162 #define PAGING_L3_ADDRESS_SHIFT     30
 163 #define PAGING_L4_ADDRESS_SHIFT     39
 164
 165 #define PAGING_PML4E_NUMBER         4
 166
 167 #define PAGETABLE_ENTRY_MASK        ((1UL << 9) - 1)
 168 #define PML4_OFFSET(x)              ( (x >> 39) & PAGETABLE_ENTRY_MASK)
 169 #define PDP_OFFSET(x)               ( (x >> 30) & PAGETABLE_ENTRY_MASK)
 170 #define PDE_OFFSET(x)               ( (x >> 21) & PAGETABLE_ENTRY_MASK)
 171 #define PTE_OFFSET(x)               ( (x >> 12) & PAGETABLE_ENTRY_MASK)
 172 #define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull
 173
 174 #define PAGE_TABLE_POOL_ALIGNMENT   BASE_2MB
 175 #define PAGE_TABLE_POOL_UNIT_SIZE   SIZE_2MB
 176 #define PAGE_TABLE_POOL_UNIT_PAGES  \
 177   EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)
 178 #define PAGE_TABLE_POOL_ALIGN_MASK  \
 179   (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))
 180
 181 typedef struct {
 182   VOID            *NextPool;
 183   UINTN           Offset;
 184   UINTN           FreePages;
 185 } PAGE_TABLE_POOL;
 186
 187
 188
 189 /**
 190   This function clears memory encryption bit for the memory region specified by
 191   PhysicalAddress and length from the current page table context.
 192
 193   @param[in]  PhysicalAddress         The physical address that is the start
 194                                       address of a memory region.
 195   @param[in]  Length                  The length of memory region
 196   @param[in]  Flush                   Flush the caches before applying the
 197                                       encryption mask
 198
 199   @retval RETURN_SUCCESS              The attributes were cleared for the
 200                                       memory region.
 201   @retval RETURN_INVALID_PARAMETER    Number of pages is zero.
 202   @retval RETURN_UNSUPPORTED          Setting the memory encyrption attribute
 203                                       is not supported
 204 **/
 205 RETURN_STATUS
 206 EFIAPI
 207 InternalMemEncryptSevSetMemoryDecrypted (
 208   IN  PHYSICAL_ADDRESS     Cr3BaseAddress,
 209   IN  PHYSICAL_ADDRESS     PhysicalAddress,
 210   IN  UINT64               Length,
 211   IN  BOOLEAN              CacheFlush
 212   );
 213
 214 /**
 215   This function sets memory encryption bit for the memory region specified by
 216   PhysicalAddress and length from the current page table context.
 217
 218   @param[in]  PhysicalAddress         The physical address that is the start
 219                                       address of a memory region.
 220   @param[in]  Length                  The length of memory region
 221   @param[in]  Flush                   Flush the caches before applying the
 222                                       encryption mask
 223
 224   @retval RETURN_SUCCESS              The attributes were cleared for the
 225                                       memory region.
 226   @retval RETURN_INVALID_PARAMETER    Number of pages is zero.
 227   @retval RETURN_UNSUPPORTED          Setting the memory encyrption attribute
 228                                       is not supported
 229 **/
 230 RETURN_STATUS
 231 EFIAPI
 232 InternalMemEncryptSevSetMemoryEncrypted (
 233   IN  PHYSICAL_ADDRESS     Cr3BaseAddress,
 234   IN  PHYSICAL_ADDRESS     PhysicalAddress,
 235   IN  UINT64               Length,
 236   IN  BOOLEAN              CacheFlush
 237   );
 238
 239 #endif