OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c

   1 /** @file
   2   OVMF's instance of the PCI Host Bridge Library.
   3
   4   Copyright (C) 2016, Red Hat, Inc.
   5   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   6
   7   This program and the accompanying materials are licensed and made available
   8   under the terms and conditions of the BSD License which accompanies this
   9   distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php.
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
  13   WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16 #include <PiDxe.h>
  17
  18 #include <IndustryStandard/Pci.h>
  19 #include <IndustryStandard/Q35MchIch9.h>
  20
  21 #include <Protocol/PciHostBridgeResourceAllocation.h>
  22 #include <Protocol/PciRootBridgeIo.h>
  23
  24 #include <Library/BaseMemoryLib.h>
  25 #include <Library/DebugLib.h>
  26 #include <Library/DevicePathLib.h>
  27 #include <Library/MemoryAllocationLib.h>
  28 #include <Library/PciHostBridgeLib.h>
  29 #include <Library/PciLib.h>
  30 #include <Library/QemuFwCfgLib.h>
  31 #include "PciHostBridge.h"
  32
  33
  34 #pragma pack(1)
  35 typedef struct {
  36   ACPI_HID_DEVICE_PATH     AcpiDevicePath;
  37   EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
  38 } OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH;
  39 #pragma pack ()
  40
  41
  42 GLOBAL_REMOVE_IF_UNREFERENCED
  43 CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
  44   L"Mem", L"I/O", L"Bus"
  45 };
  46
  47
  48 STATIC
  49 CONST
  50 OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {
  51   {
  52     {
  53       ACPI_DEVICE_PATH,
  54       ACPI_DP,
  55       {
  56         (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  57         (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  58       }
  59     },
  60     EISA_PNP_ID(0x0A03), // HID
  61     0                    // UID
  62   },
  63
  64   {
  65     END_DEVICE_PATH_TYPE,
  66     END_ENTIRE_DEVICE_PATH_SUBTYPE,
  67     {
  68       END_DEVICE_PATH_LENGTH,
  69       0
  70     }
  71   }
  72 };
  73
  74 STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };
  75
  76 /**
  77   Initialize a PCI_ROOT_BRIDGE structure.
  78
  79   @param[in]  Supports         Supported attributes.
  80
  81   @param[in]  Attributes       Initial attributes.
  82
  83   @param[in]  AllocAttributes  Allocation attributes.
  84
  85   @param[in]  RootBusNumber    The bus number to store in RootBus.
  86
  87   @param[in]  MaxSubBusNumber  The inclusive maximum bus number that can be
  88                                assigned to any subordinate bus found behind any
  89                                PCI bridge hanging off this root bus.
  90
  91                                The caller is repsonsible for ensuring that
  92                                RootBusNumber <= MaxSubBusNumber. If
  93                                RootBusNumber equals MaxSubBusNumber, then the
  94                                root bus has no room for subordinate buses.
  95
  96   @param[in]  Io               IO aperture.
  97
  98   @param[in]  Mem              MMIO aperture.
  99
 100   @param[in]  MemAbove4G       MMIO aperture above 4G.
 101
 102   @param[in]  PMem             Prefetchable MMIO aperture.
 103
 104   @param[in]  PMemAbove4G      Prefetchable MMIO aperture above 4G.
 105
 106   @param[out] RootBus          The PCI_ROOT_BRIDGE structure (allocated by the
 107                                caller) that should be filled in by this
 108                                function.
 109
 110   @retval EFI_SUCCESS           Initialization successful. A device path
 111                                 consisting of an ACPI device path node, with
 112                                 UID = RootBusNumber, has been allocated and
 113                                 linked into RootBus.
 114
 115   @retval EFI_OUT_OF_RESOURCES  Memory allocation failed.
 116 **/
 117 EFI_STATUS
 118 InitRootBridge (
 119   IN  UINT64                   Supports,
 120   IN  UINT64                   Attributes,
 121   IN  UINT64                   AllocAttributes,
 122   IN  UINT8                    RootBusNumber,
 123   IN  UINT8                    MaxSubBusNumber,
 124   IN  PCI_ROOT_BRIDGE_APERTURE *Io,
 125   IN  PCI_ROOT_BRIDGE_APERTURE *Mem,
 126   IN  PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
 127   IN  PCI_ROOT_BRIDGE_APERTURE *PMem,
 128   IN  PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
 129   OUT PCI_ROOT_BRIDGE          *RootBus
 130   )
 131 {
 132   OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
 133
 134   //
 135   // Be safe if other fields are added to PCI_ROOT_BRIDGE later.
 136   //
 137   ZeroMem (RootBus, sizeof *RootBus);
 138
 139   RootBus->Segment = 0;
 140
 141   RootBus->Supports   = Supports;
 142   RootBus->Attributes = Attributes;
 143
 144   RootBus->DmaAbove4G = FALSE;
 145
 146   RootBus->AllocationAttributes = AllocAttributes;
 147   RootBus->Bus.Base  = RootBusNumber;
 148   RootBus->Bus.Limit = MaxSubBusNumber;
 149   CopyMem (&RootBus->Io, Io, sizeof (*Io));
 150   CopyMem (&RootBus->Mem, Mem, sizeof (*Mem));
 151   CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G));
 152   CopyMem (&RootBus->PMem, PMem, sizeof (*PMem));
 153   CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G));
 154
 155   RootBus->NoExtendedConfigSpace = (PcdGet16 (PcdOvmfHostBridgePciDevId) !=
 156                                     INTEL_Q35_MCH_DEVICE_ID);
 157
 158   DevicePath = AllocateCopyPool (sizeof mRootBridgeDevicePathTemplate,
 159                  &mRootBridgeDevicePathTemplate);
 160   if (DevicePath == NULL) {
 161     DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));
 162     return EFI_OUT_OF_RESOURCES;
 163   }
 164   DevicePath->AcpiDevicePath.UID = RootBusNumber;
 165   RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;
 166
 167   DEBUG ((EFI_D_INFO,
 168     "%a: populated root bus %d, with room for %d subordinate bus(es)\n",
 169     __FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));
 170   return EFI_SUCCESS;
 171 }
 172
 173
 174 /**
 175   Uninitialize a PCI_ROOT_BRIDGE structure set up with InitRootBridge().
 176
 177   param[in] RootBus  The PCI_ROOT_BRIDGE structure, allocated by the caller and
 178                      initialized with InitRootBridge(), that should be
 179                      uninitialized. This function doesn't free RootBus.
 180 **/
 181 STATIC
 182 VOID
 183 UninitRootBridge (
 184   IN PCI_ROOT_BRIDGE *RootBus
 185   )
 186 {
 187   FreePool (RootBus->DevicePath);
 188 }
 189
 190
 191 /**
 192   Return all the root bridge instances in an array.
 193
 194   @param Count  Return the count of root bridge instances.
 195
 196   @return All the root bridge instances in an array.
 197           The array should be passed into PciHostBridgeFreeRootBridges()
 198           when it's not used.
 199 **/
 200 PCI_ROOT_BRIDGE *
 201 EFIAPI
 202 PciHostBridgeGetRootBridges (
 203   UINTN *Count
 204   )
 205 {
 206   EFI_STATUS           Status;
 207   FIRMWARE_CONFIG_ITEM FwCfgItem;
 208   UINTN                FwCfgSize;
 209   UINT64               ExtraRootBridges;
 210   PCI_ROOT_BRIDGE      *Bridges;
 211   UINTN                Initialized;
 212   UINTN                LastRootBridgeNumber;
 213   UINTN                RootBridgeNumber;
 214   UINT64               Attributes;
 215   UINT64               AllocationAttributes;
 216   PCI_ROOT_BRIDGE_APERTURE Io;
 217   PCI_ROOT_BRIDGE_APERTURE Mem;
 218   PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
 219
 220   if (PcdGetBool (PcdPciDisableBusEnumeration)) {
 221     return ScanForRootBridges (Count);
 222   }
 223
 224   ZeroMem (&Io, sizeof (Io));
 225   ZeroMem (&Mem, sizeof (Mem));
 226   ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
 227
 228   Attributes = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
 229     EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
 230     EFI_PCI_ATTRIBUTE_ISA_IO_16 |
 231     EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
 232     EFI_PCI_ATTRIBUTE_VGA_MEMORY |
 233     EFI_PCI_ATTRIBUTE_VGA_IO_16 |
 234     EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
 235
 236   AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;
 237   if (PcdGet64 (PcdPciMmio64Size) > 0) {
 238     AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
 239     MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base);
 240     MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) +
 241                        PcdGet64 (PcdPciMmio64Size) - 1;
 242   } else {
 243     CopyMem (&MemAbove4G, &mNonExistAperture, sizeof (mNonExistAperture));
 244   }
 245
 246   Io.Base = PcdGet64 (PcdPciIoBase);
 247   Io.Limit = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1);
 248   Mem.Base = PcdGet64 (PcdPciMmio32Base);
 249   Mem.Limit = PcdGet64 (PcdPciMmio32Base) + (PcdGet64 (PcdPciMmio32Size) - 1);
 250
 251   *Count = 0;
 252
 253   //
 254   // QEMU provides the number of extra root buses, shortening the exhaustive
 255   // search below. If there is no hint, the feature is missing.
 256   //
 257   Status = QemuFwCfgFindFile ("etc/extra-pci-roots", &FwCfgItem, &FwCfgSize);
 258   if (EFI_ERROR (Status) || FwCfgSize != sizeof ExtraRootBridges) {
 259     ExtraRootBridges = 0;
 260   } else {
 261     QemuFwCfgSelectItem (FwCfgItem);
 262     QemuFwCfgReadBytes (FwCfgSize, &ExtraRootBridges);
 263
 264     if (ExtraRootBridges > PCI_MAX_BUS) {
 265       DEBUG ((EFI_D_ERROR, "%a: invalid count of extra root buses (%Lu) "
 266         "reported by QEMU\n", __FUNCTION__, ExtraRootBridges));
 267       return NULL;
 268     }
 269     DEBUG ((EFI_D_INFO, "%a: %Lu extra root buses reported by QEMU\n",
 270       __FUNCTION__, ExtraRootBridges));
 271   }
 272
 273   //
 274   // Allocate the "main" root bridge, and any extra root bridges.
 275   //
 276   Bridges = AllocatePool ((1 + (UINTN)ExtraRootBridges) * sizeof *Bridges);
 277   if (Bridges == NULL) {
 278     DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));
 279     return NULL;
 280   }
 281   Initialized = 0;
 282
 283   //
 284   // The "main" root bus is always there.
 285   //
 286   LastRootBridgeNumber = 0;
 287
 288   //
 289   // Scan all other root buses. If function 0 of any device on a bus returns a
 290   // VendorId register value different from all-bits-one, then that bus is
 291   // alive.
 292   //
 293   for (RootBridgeNumber = 1;
 294        RootBridgeNumber <= PCI_MAX_BUS && Initialized < ExtraRootBridges;
 295        ++RootBridgeNumber) {
 296     UINTN Device;
 297
 298     for (Device = 0; Device <= PCI_MAX_DEVICE; ++Device) {
 299       if (PciRead16 (PCI_LIB_ADDRESS (RootBridgeNumber, Device, 0,
 300                        PCI_VENDOR_ID_OFFSET)) != MAX_UINT16) {
 301         break;
 302       }
 303     }
 304     if (Device <= PCI_MAX_DEVICE) {
 305       //
 306       // Found the next root bus. We can now install the *previous* one,
 307       // because now we know how big a bus number range *that* one has, for any
 308       // subordinate buses that might exist behind PCI bridges hanging off it.
 309       //
 310       Status = InitRootBridge (
 311         Attributes,
 312         Attributes,
 313         AllocationAttributes,
 314         (UINT8) LastRootBridgeNumber,
 315         (UINT8) (RootBridgeNumber - 1),
 316         &Io,
 317         &Mem,
 318         &MemAbove4G,
 319         &mNonExistAperture,
 320         &mNonExistAperture,
 321         &Bridges[Initialized]
 322         );
 323       if (EFI_ERROR (Status)) {
 324         goto FreeBridges;
 325       }
 326       ++Initialized;
 327       LastRootBridgeNumber = RootBridgeNumber;
 328     }
 329   }
 330
 331   //
 332   // Install the last root bus (which might be the only, ie. main, root bus, if
 333   // we've found no extra root buses).
 334   //
 335   Status = InitRootBridge (
 336     Attributes,
 337     Attributes,
 338     AllocationAttributes,
 339     (UINT8) LastRootBridgeNumber,
 340     PCI_MAX_BUS,
 341     &Io,
 342     &Mem,
 343     &MemAbove4G,
 344     &mNonExistAperture,
 345     &mNonExistAperture,
 346     &Bridges[Initialized]
 347     );
 348   if (EFI_ERROR (Status)) {
 349     goto FreeBridges;
 350   }
 351   ++Initialized;
 352
 353   *Count = Initialized;
 354   return Bridges;
 355
 356 FreeBridges:
 357   while (Initialized > 0) {
 358     --Initialized;
 359     UninitRootBridge (&Bridges[Initialized]);
 360   }
 361
 362   FreePool (Bridges);
 363   return NULL;
 364 }
 365
 366
 367 /**
 368   Free the root bridge instances array returned from
 369   PciHostBridgeGetRootBridges().
 370
 371   @param  The root bridge instances array.
 372   @param  The count of the array.
 373 **/
 374 VOID
 375 EFIAPI
 376 PciHostBridgeFreeRootBridges (
 377   PCI_ROOT_BRIDGE *Bridges,
 378   UINTN           Count
 379   )
 380 {
 381   if (Bridges == NULL && Count == 0) {
 382     return;
 383   }
 384   ASSERT (Bridges != NULL && Count > 0);
 385
 386   do {
 387     --Count;
 388     UninitRootBridge (&Bridges[Count]);
 389   } while (Count > 0);
 390
 391   FreePool (Bridges);
 392 }
 393
 394
 395 /**
 396   Inform the platform that the resource conflict happens.
 397
 398   @param HostBridgeHandle Handle of the Host Bridge.
 399   @param Configuration    Pointer to PCI I/O and PCI memory resource
 400                           descriptors. The Configuration contains the resources
 401                           for all the root bridges. The resource for each root
 402                           bridge is terminated with END descriptor and an
 403                           additional END is appended indicating the end of the
 404                           entire resources. The resource descriptor field
 405                           values follow the description in
 406                           EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
 407                           .SubmitResources().
 408 **/
 409 VOID
 410 EFIAPI
 411 PciHostBridgeResourceConflict (
 412   EFI_HANDLE                        HostBridgeHandle,
 413   VOID                              *Configuration
 414   )
 415 {
 416   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
 417   UINTN                             RootBridgeIndex;
 418   DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n"));
 419
 420   RootBridgeIndex = 0;
 421   Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
 422   while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
 423     DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
 424     for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
 425       ASSERT (Descriptor->ResType <
 426               ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)
 427               );
 428       DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
 429               mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
 430               Descriptor->AddrLen, Descriptor->AddrRangeMax
 431               ));
 432       if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
 433         DEBUG ((EFI_D_ERROR, "     Granularity/SpecificFlag = %ld / %02x%s\n",
 434                 Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
 435                 ((Descriptor->SpecificFlag &
 436                   EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
 437                   ) != 0) ? L" (Prefetchable)" : L""
 438                 ));
 439       }
 440     }
 441     //
 442     // Skip the END descriptor for root bridge
 443     //
 444     ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
 445     Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
 446                    (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
 447                    );
 448   }
 449 }