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1 /** @file
2 The CPU specific programming for PiSmmCpuDxeSmm module.
3
4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
5
6 This program and the accompanying materials are licensed and made available
7 under the terms and conditions of the BSD License which accompanies this
8 distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
12 WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 **/
14
15 #include <Library/BaseLib.h>
16 #include <Library/BaseMemoryLib.h>
17 #include <Library/DebugLib.h>
18 #include <Library/SmmCpuFeaturesLib.h>
19 #include <Library/SmmServicesTableLib.h>
20 #include <PiSmm.h>
21 #include <Register/QemuSmramSaveStateMap.h>
22
23 //
24 // EFER register LMA bit
25 //
26 #define LMA BIT10
27
28 /**
29 The constructor function
30
31 @param[in] ImageHandle The firmware allocated handle for the EFI image.
32 @param[in] SystemTable A pointer to the EFI System Table.
33
34 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
35
36 **/
37 EFI_STATUS
38 EFIAPI
39 SmmCpuFeaturesLibConstructor (
40 IN EFI_HANDLE ImageHandle,
41 IN EFI_SYSTEM_TABLE *SystemTable
42 )
43 {
44 //
45 // No need to program SMRRs on our virtual platform.
46 //
47 return EFI_SUCCESS;
48 }
49
50 /**
51 Called during the very first SMI into System Management Mode to initialize
52 CPU features, including SMBASE, for the currently executing CPU. Since this
53 is the first SMI, the SMRAM Save State Map is at the default address of
54 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
55 CPU is specified by CpuIndex and CpuIndex can be used to access information
56 about the currently executing CPU in the ProcessorInfo array and the
57 HotPlugCpuData data structure.
58
59 @param[in] CpuIndex The index of the CPU to initialize. The value
60 must be between 0 and the NumberOfCpus field in
61 the System Management System Table (SMST).
62 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
63 was elected as monarch during System Management
64 Mode initialization.
65 FALSE if the CpuIndex is not the index of the CPU
66 that was elected as monarch during System
67 Management Mode initialization.
68 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
69 structures. ProcessorInfo[CpuIndex] contains the
70 information for the currently executing CPU.
71 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
72 contains the ApidId and SmBase arrays.
73 **/
74 VOID
75 EFIAPI
76 SmmCpuFeaturesInitializeProcessor (
77 IN UINTN CpuIndex,
78 IN BOOLEAN IsMonarch,
79 IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,
80 IN CPU_HOT_PLUG_DATA *CpuHotPlugData
81 )
82 {
83 QEMU_SMRAM_SAVE_STATE_MAP *CpuState;
84
85 //
86 // Configure SMBASE.
87 //
88 CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(
89 SMM_DEFAULT_SMBASE +
90 SMRAM_SAVE_STATE_MAP_OFFSET
91 );
92 if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {
93 CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
94 } else {
95 CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
96 }
97
98 //
99 // No need to program SMRRs on our virtual platform.
100 //
101 }
102
103 /**
104 This function updates the SMRAM save state on the currently executing CPU
105 to resume execution at a specific address after an RSM instruction. This
106 function must evaluate the SMRAM save state to determine the execution mode
107 the RSM instruction resumes and update the resume execution address with
108 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
109 flag in the SMRAM save state must always be cleared. This function returns
110 the value of the instruction pointer from the SMRAM save state that was
111 replaced. If this function returns 0, then the SMRAM save state was not
112 modified.
113
114 This function is called during the very first SMI on each CPU after
115 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
116 to signal that the SMBASE of each CPU has been updated before the default
117 SMBASE address is used for the first SMI to the next CPU.
118
119 @param[in] CpuIndex The index of the CPU to hook. The value
120 must be between 0 and the NumberOfCpus
121 field in the System Management System
122 Table (SMST).
123 @param[in] CpuState Pointer to SMRAM Save State Map for the
124 currently executing CPU.
125 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
126 32-bit execution mode from 64-bit SMM.
127 @param[in] NewInstructionPointer Instruction pointer to use if resuming to
128 same execution mode as SMM.
129
130 @retval 0 This function did modify the SMRAM save state.
131 @retval > 0 The original instruction pointer value from the SMRAM save state
132 before it was replaced.
133 **/
134 UINT64
135 EFIAPI
136 SmmCpuFeaturesHookReturnFromSmm (
137 IN UINTN CpuIndex,
138 IN SMRAM_SAVE_STATE_MAP *CpuState,
139 IN UINT64 NewInstructionPointer32,
140 IN UINT64 NewInstructionPointer
141 )
142 {
143 UINT64 OriginalInstructionPointer;
144 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
145
146 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;
147 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
148 OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;
149 CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;
150 //
151 // Clear the auto HALT restart flag so the RSM instruction returns
152 // program control to the instruction following the HLT instruction.
153 //
154 if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != 0) {
155 CpuSaveState->x86.AutoHALTRestart &= ~BIT0;
156 }
157 } else {
158 OriginalInstructionPointer = CpuSaveState->x64._RIP;
159 if ((CpuSaveState->x64.IA32_EFER & LMA) == 0) {
160 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer32;
161 } else {
162 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer;
163 }
164 //
165 // Clear the auto HALT restart flag so the RSM instruction returns
166 // program control to the instruction following the HLT instruction.
167 //
168 if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != 0) {
169 CpuSaveState->x64.AutoHALTRestart &= ~BIT0;
170 }
171 }
172 return OriginalInstructionPointer;
173 }
174
175 /**
176 Hook point in normal execution mode that allows the one CPU that was elected
177 as monarch during System Management Mode initialization to perform additional
178 initialization actions immediately after all of the CPUs have processed their
179 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
180 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
181 **/
182 VOID
183 EFIAPI
184 SmmCpuFeaturesSmmRelocationComplete (
185 VOID
186 )
187 {
188 }
189
190 /**
191 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
192 returned, then a custom SMI handler is not provided by this library,
193 and the default SMI handler must be used.
194
195 @retval 0 Use the default SMI handler.
196 @retval > 0 Use the SMI handler installed by
197 SmmCpuFeaturesInstallSmiHandler(). The caller is required to
198 allocate enough SMRAM for each CPU to support the size of the
199 custom SMI handler.
200 **/
201 UINTN
202 EFIAPI
203 SmmCpuFeaturesGetSmiHandlerSize (
204 VOID
205 )
206 {
207 return 0;
208 }
209
210 /**
211 Install a custom SMI handler for the CPU specified by CpuIndex. This
212 function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size
213 is greater than zero and is called by the CPU that was elected as monarch
214 during System Management Mode initialization.
215
216 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
217 The value must be between 0 and the NumberOfCpus field
218 in the System Management System Table (SMST).
219 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
220 @param[in] SmiStack The stack to use when an SMI is processed by the
221 the CPU specified by CpuIndex.
222 @param[in] StackSize The size, in bytes, if the stack used when an SMI is
223 processed by the CPU specified by CpuIndex.
224 @param[in] GdtBase The base address of the GDT to use when an SMI is
225 processed by the CPU specified by CpuIndex.
226 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
227 processed by the CPU specified by CpuIndex.
228 @param[in] IdtBase The base address of the IDT to use when an SMI is
229 processed by the CPU specified by CpuIndex.
230 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
231 processed by the CPU specified by CpuIndex.
232 @param[in] Cr3 The base address of the page tables to use when an SMI
233 is processed by the CPU specified by CpuIndex.
234 **/
235 VOID
236 EFIAPI
237 SmmCpuFeaturesInstallSmiHandler (
238 IN UINTN CpuIndex,
239 IN UINT32 SmBase,
240 IN VOID *SmiStack,
241 IN UINTN StackSize,
242 IN UINTN GdtBase,
243 IN UINTN GdtSize,
244 IN UINTN IdtBase,
245 IN UINTN IdtSize,
246 IN UINT32 Cr3
247 )
248 {
249 }
250
251 /**
252 Determines if MTRR registers must be configured to set SMRAM cache-ability
253 when executing in System Management Mode.
254
255 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
256 @retval FALSE MTRR registers do not need to be configured to set SMRAM
257 cache-ability.
258 **/
259 BOOLEAN
260 EFIAPI
261 SmmCpuFeaturesNeedConfigureMtrrs (
262 VOID
263 )
264 {
265 return FALSE;
266 }
267
268 /**
269 Disable SMRR register if SMRR is supported and
270 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
271 **/
272 VOID
273 EFIAPI
274 SmmCpuFeaturesDisableSmrr (
275 VOID
276 )
277 {
278 //
279 // No SMRR support, nothing to do
280 //
281 }
282
283 /**
284 Enable SMRR register if SMRR is supported and
285 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
286 **/
287 VOID
288 EFIAPI
289 SmmCpuFeaturesReenableSmrr (
290 VOID
291 )
292 {
293 //
294 // No SMRR support, nothing to do
295 //
296 }
297
298 /**
299 Processor specific hook point each time a CPU enters System Management Mode.
300
301 @param[in] CpuIndex The index of the CPU that has entered SMM. The value
302 must be between 0 and the NumberOfCpus field in the
303 System Management System Table (SMST).
304 **/
305 VOID
306 EFIAPI
307 SmmCpuFeaturesRendezvousEntry (
308 IN UINTN CpuIndex
309 )
310 {
311 //
312 // No SMRR support, nothing to do
313 //
314 }
315
316 /**
317 Processor specific hook point each time a CPU exits System Management Mode.
318
319 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value
320 must be between 0 and the NumberOfCpus field in the
321 System Management System Table (SMST).
322 **/
323 VOID
324 EFIAPI
325 SmmCpuFeaturesRendezvousExit (
326 IN UINTN CpuIndex
327 )
328 {
329 }
330
331 /**
332 Check to see if an SMM register is supported by a specified CPU.
333
334 @param[in] CpuIndex The index of the CPU to check for SMM register support.
335 The value must be between 0 and the NumberOfCpus field
336 in the System Management System Table (SMST).
337 @param[in] RegName Identifies the SMM register to check for support.
338
339 @retval TRUE The SMM register specified by RegName is supported by the CPU
340 specified by CpuIndex.
341 @retval FALSE The SMM register specified by RegName is not supported by the
342 CPU specified by CpuIndex.
343 **/
344 BOOLEAN
345 EFIAPI
346 SmmCpuFeaturesIsSmmRegisterSupported (
347 IN UINTN CpuIndex,
348 IN SMM_REG_NAME RegName
349 )
350 {
351 ASSERT (RegName == SmmRegFeatureControl);
352 return FALSE;
353 }
354
355 /**
356 Returns the current value of the SMM register for the specified CPU.
357 If the SMM register is not supported, then 0 is returned.
358
359 @param[in] CpuIndex The index of the CPU to read the SMM register. The
360 value must be between 0 and the NumberOfCpus field in
361 the System Management System Table (SMST).
362 @param[in] RegName Identifies the SMM register to read.
363
364 @return The value of the SMM register specified by RegName from the CPU
365 specified by CpuIndex.
366 **/
367 UINT64
368 EFIAPI
369 SmmCpuFeaturesGetSmmRegister (
370 IN UINTN CpuIndex,
371 IN SMM_REG_NAME RegName
372 )
373 {
374 //
375 // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.
376 // The last of these should actually be SmmRegSmmDisable, so we can just
377 // return FALSE.
378 //
379 return 0;
380 }
381
382 /**
383 Sets the value of an SMM register on a specified CPU.
384 If the SMM register is not supported, then no action is performed.
385
386 @param[in] CpuIndex The index of the CPU to write the SMM register. The
387 value must be between 0 and the NumberOfCpus field in
388 the System Management System Table (SMST).
389 @param[in] RegName Identifies the SMM register to write.
390 registers are read-only.
391 @param[in] Value The value to write to the SMM register.
392 **/
393 VOID
394 EFIAPI
395 SmmCpuFeaturesSetSmmRegister (
396 IN UINTN CpuIndex,
397 IN SMM_REG_NAME RegName,
398 IN UINT64 Value
399 )
400 {
401 ASSERT (FALSE);
402 }
403
404 ///
405 /// Macro used to simplify the lookup table entries of type
406 /// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
407 ///
408 #define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)
409
410 ///
411 /// Macro used to simplify the lookup table entries of type
412 /// CPU_SMM_SAVE_STATE_REGISTER_RANGE
413 ///
414 #define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
415
416 ///
417 /// Structure used to describe a range of registers
418 ///
419 typedef struct {
420 EFI_SMM_SAVE_STATE_REGISTER Start;
421 EFI_SMM_SAVE_STATE_REGISTER End;
422 UINTN Length;
423 } CPU_SMM_SAVE_STATE_REGISTER_RANGE;
424
425 ///
426 /// Structure used to build a lookup table to retrieve the widths and offsets
427 /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
428 ///
429
430 #define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1
431
432 typedef struct {
433 UINT8 Width32;
434 UINT8 Width64;
435 UINT16 Offset32;
436 UINT16 Offset64Lo;
437 UINT16 Offset64Hi;
438 BOOLEAN Writeable;
439 } CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
440
441 ///
442 /// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
443 /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
444 ///
445 STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
446 SMM_REGISTER_RANGE (
447 EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,
448 EFI_SMM_SAVE_STATE_REGISTER_LDTINFO
449 ),
450 SMM_REGISTER_RANGE (
451 EFI_SMM_SAVE_STATE_REGISTER_ES,
452 EFI_SMM_SAVE_STATE_REGISTER_RIP
453 ),
454 SMM_REGISTER_RANGE (
455 EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,
456 EFI_SMM_SAVE_STATE_REGISTER_CR4
457 ),
458 { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }
459 };
460
461 ///
462 /// Lookup table used to retrieve the widths and offsets associated with each
463 /// supported EFI_SMM_SAVE_STATE_REGISTER value
464 ///
465 STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
466 {
467 0, // Width32
468 0, // Width64
469 0, // Offset32
470 0, // Offset64Lo
471 0, // Offset64Hi
472 FALSE // Writeable
473 }, // Reserved
474
475 //
476 // CPU Save State registers defined in PI SMM CPU Protocol.
477 //
478 {
479 0, // Width32
480 8, // Width64
481 0, // Offset32
482 SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo
483 SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi
484 FALSE // Writeable
485 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
486
487 {
488 0, // Width32
489 8, // Width64
490 0, // Offset32
491 SMM_CPU_OFFSET (x64._IDTRBase), // Offset64Lo
492 SMM_CPU_OFFSET (x64._IDTRBase) + 4, // Offset64Hi
493 FALSE // Writeable
494 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
495
496 {
497 0, // Width32
498 8, // Width64
499 0, // Offset32
500 SMM_CPU_OFFSET (x64._LDTRBase), // Offset64Lo
501 SMM_CPU_OFFSET (x64._LDTRBase) + 4, // Offset64Hi
502 FALSE // Writeable
503 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
504
505 {
506 0, // Width32
507 0, // Width64
508 0, // Offset32
509 SMM_CPU_OFFSET (x64._GDTRLimit), // Offset64Lo
510 SMM_CPU_OFFSET (x64._GDTRLimit) + 4, // Offset64Hi
511 FALSE // Writeable
512 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
513
514 {
515 0, // Width32
516 0, // Width64
517 0, // Offset32
518 SMM_CPU_OFFSET (x64._IDTRLimit), // Offset64Lo
519 SMM_CPU_OFFSET (x64._IDTRLimit) + 4, // Offset64Hi
520 FALSE // Writeable
521 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
522
523 {
524 0, // Width32
525 0, // Width64
526 0, // Offset32
527 SMM_CPU_OFFSET (x64._LDTRLimit), // Offset64Lo
528 SMM_CPU_OFFSET (x64._LDTRLimit) + 4, // Offset64Hi
529 FALSE // Writeable
530 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
531
532 {
533 0, // Width32
534 0, // Width64
535 0, // Offset32
536 0, // Offset64Lo
537 0 + 4, // Offset64Hi
538 FALSE // Writeable
539 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
540
541 {
542 4, // Width32
543 4, // Width64
544 SMM_CPU_OFFSET (x86._ES), // Offset32
545 SMM_CPU_OFFSET (x64._ES), // Offset64Lo
546 0, // Offset64Hi
547 FALSE // Writeable
548 }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
549
550 {
551 4, // Width32
552 4, // Width64
553 SMM_CPU_OFFSET (x86._CS), // Offset32
554 SMM_CPU_OFFSET (x64._CS), // Offset64Lo
555 0, // Offset64Hi
556 FALSE // Writeable
557 }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
558
559 {
560 4, // Width32
561 4, // Width64
562 SMM_CPU_OFFSET (x86._SS), // Offset32
563 SMM_CPU_OFFSET (x64._SS), // Offset64Lo
564 0, // Offset64Hi
565 FALSE // Writeable
566 }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
567
568 {
569 4, // Width32
570 4, // Width64
571 SMM_CPU_OFFSET (x86._DS), // Offset32
572 SMM_CPU_OFFSET (x64._DS), // Offset64Lo
573 0, // Offset64Hi
574 FALSE // Writeable
575 }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
576
577 {
578 4, // Width32
579 4, // Width64
580 SMM_CPU_OFFSET (x86._FS), // Offset32
581 SMM_CPU_OFFSET (x64._FS), // Offset64Lo
582 0, // Offset64Hi
583 FALSE // Writeable
584 }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
585
586 {
587 4, // Width32
588 4, // Width64
589 SMM_CPU_OFFSET (x86._GS), // Offset32
590 SMM_CPU_OFFSET (x64._GS), // Offset64Lo
591 0, // Offset64Hi
592 FALSE // Writeable
593 }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
594
595 {
596 0, // Width32
597 4, // Width64
598 0, // Offset32
599 SMM_CPU_OFFSET (x64._LDTR), // Offset64Lo
600 0, // Offset64Hi
601 FALSE // Writeable
602 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
603
604 {
605 4, // Width32
606 4, // Width64
607 SMM_CPU_OFFSET (x86._TR), // Offset32
608 SMM_CPU_OFFSET (x64._TR), // Offset64Lo
609 0, // Offset64Hi
610 FALSE // Writeable
611 }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
612
613 {
614 4, // Width32
615 8, // Width64
616 SMM_CPU_OFFSET (x86._DR7), // Offset32
617 SMM_CPU_OFFSET (x64._DR7), // Offset64Lo
618 SMM_CPU_OFFSET (x64._DR7) + 4, // Offset64Hi
619 FALSE // Writeable
620 }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
621
622 {
623 4, // Width32
624 8, // Width64
625 SMM_CPU_OFFSET (x86._DR6), // Offset32
626 SMM_CPU_OFFSET (x64._DR6), // Offset64Lo
627 SMM_CPU_OFFSET (x64._DR6) + 4, // Offset64Hi
628 FALSE // Writeable
629 }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
630
631 {
632 0, // Width32
633 8, // Width64
634 0, // Offset32
635 SMM_CPU_OFFSET (x64._R8), // Offset64Lo
636 SMM_CPU_OFFSET (x64._R8) + 4, // Offset64Hi
637 TRUE // Writeable
638 }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
639
640 {
641 0, // Width32
642 8, // Width64
643 0, // Offset32
644 SMM_CPU_OFFSET (x64._R9), // Offset64Lo
645 SMM_CPU_OFFSET (x64._R9) + 4, // Offset64Hi
646 TRUE // Writeable
647 }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
648
649 {
650 0, // Width32
651 8, // Width64
652 0, // Offset32
653 SMM_CPU_OFFSET (x64._R10), // Offset64Lo
654 SMM_CPU_OFFSET (x64._R10) + 4, // Offset64Hi
655 TRUE // Writeable
656 }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
657
658 {
659 0, // Width32
660 8, // Width64
661 0, // Offset32
662 SMM_CPU_OFFSET (x64._R11), // Offset64Lo
663 SMM_CPU_OFFSET (x64._R11) + 4, // Offset64Hi
664 TRUE // Writeable
665 }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
666
667 {
668 0, // Width32
669 8, // Width64
670 0, // Offset32
671 SMM_CPU_OFFSET (x64._R12), // Offset64Lo
672 SMM_CPU_OFFSET (x64._R12) + 4, // Offset64Hi
673 TRUE // Writeable
674 }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
675
676 {
677 0, // Width32
678 8, // Width64
679 0, // Offset32
680 SMM_CPU_OFFSET (x64._R13), // Offset64Lo
681 SMM_CPU_OFFSET (x64._R13) + 4, // Offset64Hi
682 TRUE // Writeable
683 }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
684
685 {
686 0, // Width32
687 8, // Width64
688 0, // Offset32
689 SMM_CPU_OFFSET (x64._R14), // Offset64Lo
690 SMM_CPU_OFFSET (x64._R14) + 4, // Offset64Hi
691 TRUE // Writeable
692 }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
693
694 {
695 0, // Width32
696 8, // Width64
697 0, // Offset32
698 SMM_CPU_OFFSET (x64._R15), // Offset64Lo
699 SMM_CPU_OFFSET (x64._R15) + 4, // Offset64Hi
700 TRUE // Writeable
701 }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
702
703 {
704 4, // Width32
705 8, // Width64
706 SMM_CPU_OFFSET (x86._EAX), // Offset32
707 SMM_CPU_OFFSET (x64._RAX), // Offset64Lo
708 SMM_CPU_OFFSET (x64._RAX) + 4, // Offset64Hi
709 TRUE // Writeable
710 }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
711
712 {
713 4, // Width32
714 8, // Width64
715 SMM_CPU_OFFSET (x86._EBX), // Offset32
716 SMM_CPU_OFFSET (x64._RBX), // Offset64Lo
717 SMM_CPU_OFFSET (x64._RBX) + 4, // Offset64Hi
718 TRUE // Writeable
719 }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
720
721 {
722 4, // Width32
723 8, // Width64
724 SMM_CPU_OFFSET (x86._ECX), // Offset32
725 SMM_CPU_OFFSET (x64._RCX), // Offset64Lo
726 SMM_CPU_OFFSET (x64._RCX) + 4, // Offset64Hi
727 TRUE // Writeable
728 }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
729
730 {
731 4, // Width32
732 8, // Width64
733 SMM_CPU_OFFSET (x86._EDX), // Offset32
734 SMM_CPU_OFFSET (x64._RDX), // Offset64Lo
735 SMM_CPU_OFFSET (x64._RDX) + 4, // Offset64Hi
736 TRUE // Writeable
737 }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
738
739 {
740 4, // Width32
741 8, // Width64
742 SMM_CPU_OFFSET (x86._ESP), // Offset32
743 SMM_CPU_OFFSET (x64._RSP), // Offset64Lo
744 SMM_CPU_OFFSET (x64._RSP) + 4, // Offset64Hi
745 TRUE // Writeable
746 }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
747
748 {
749 4, // Width32
750 8, // Width64
751 SMM_CPU_OFFSET (x86._EBP), // Offset32
752 SMM_CPU_OFFSET (x64._RBP), // Offset64Lo
753 SMM_CPU_OFFSET (x64._RBP) + 4, // Offset64Hi
754 TRUE // Writeable
755 }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
756
757 {
758 4, // Width32
759 8, // Width64
760 SMM_CPU_OFFSET (x86._ESI), // Offset32
761 SMM_CPU_OFFSET (x64._RSI), // Offset64Lo
762 SMM_CPU_OFFSET (x64._RSI) + 4, // Offset64Hi
763 TRUE // Writeable
764 }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
765
766 {
767 4, // Width32
768 8, // Width64
769 SMM_CPU_OFFSET (x86._EDI), // Offset32
770 SMM_CPU_OFFSET (x64._RDI), // Offset64Lo
771 SMM_CPU_OFFSET (x64._RDI) + 4, // Offset64Hi
772 TRUE // Writeable
773 }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
774
775 {
776 4, // Width32
777 8, // Width64
778 SMM_CPU_OFFSET (x86._EIP), // Offset32
779 SMM_CPU_OFFSET (x64._RIP), // Offset64Lo
780 SMM_CPU_OFFSET (x64._RIP) + 4, // Offset64Hi
781 TRUE // Writeable
782 }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
783
784 {
785 4, // Width32
786 8, // Width64
787 SMM_CPU_OFFSET (x86._EFLAGS), // Offset32
788 SMM_CPU_OFFSET (x64._RFLAGS), // Offset64Lo
789 SMM_CPU_OFFSET (x64._RFLAGS) + 4, // Offset64Hi
790 TRUE // Writeable
791 }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
792
793 {
794 4, // Width32
795 8, // Width64
796 SMM_CPU_OFFSET (x86._CR0), // Offset32
797 SMM_CPU_OFFSET (x64._CR0), // Offset64Lo
798 SMM_CPU_OFFSET (x64._CR0) + 4, // Offset64Hi
799 FALSE // Writeable
800 }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
801
802 {
803 4, // Width32
804 8, // Width64
805 SMM_CPU_OFFSET (x86._CR3), // Offset32
806 SMM_CPU_OFFSET (x64._CR3), // Offset64Lo
807 SMM_CPU_OFFSET (x64._CR3) + 4, // Offset64Hi
808 FALSE // Writeable
809 }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
810
811 {
812 0, // Width32
813 4, // Width64
814 0, // Offset32
815 SMM_CPU_OFFSET (x64._CR4), // Offset64Lo
816 SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi
817 FALSE // Writeable
818 }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
819 };
820
821 //
822 // No support for I/O restart
823 //
824
825 /**
826 Read information from the CPU save state.
827
828 @param Register Specifies the CPU register to read form the save state.
829
830 @retval 0 Register is not valid
831 @retval >0 Index into mSmmCpuWidthOffset[] associated with Register
832
833 **/
834 STATIC
835 UINTN
836 GetRegisterIndex (
837 IN EFI_SMM_SAVE_STATE_REGISTER Register
838 )
839 {
840 UINTN Index;
841 UINTN Offset;
842
843 for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX;
844 mSmmCpuRegisterRanges[Index].Length != 0;
845 Index++) {
846 if (Register >= mSmmCpuRegisterRanges[Index].Start &&
847 Register <= mSmmCpuRegisterRanges[Index].End) {
848 return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
849 }
850 Offset += mSmmCpuRegisterRanges[Index].Length;
851 }
852 return 0;
853 }
854
855 /**
856 Read a CPU Save State register on the target processor.
857
858 This function abstracts the differences that whether the CPU Save State
859 register is in the IA32 CPU Save State Map or X64 CPU Save State Map.
860
861 This function supports reading a CPU Save State register in SMBase relocation
862 handler.
863
864 @param[in] CpuIndex Specifies the zero-based index of the CPU save
865 state.
866 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
867 @param[in] Width The number of bytes to read from the CPU save
868 state.
869 @param[out] Buffer Upon return, this holds the CPU register value
870 read from the save state.
871
872 @retval EFI_SUCCESS The register was read from Save State.
873 @retval EFI_NOT_FOUND The register is not defined for the Save State
874 of Processor.
875 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
876
877 **/
878 STATIC
879 EFI_STATUS
880 ReadSaveStateRegisterByIndex (
881 IN UINTN CpuIndex,
882 IN UINTN RegisterIndex,
883 IN UINTN Width,
884 OUT VOID *Buffer
885 )
886 {
887 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
888
889 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
890
891 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
892 //
893 // If 32-bit mode width is zero, then the specified register can not be
894 // accessed
895 //
896 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
897 return EFI_NOT_FOUND;
898 }
899
900 //
901 // If Width is bigger than the 32-bit mode width, then the specified
902 // register can not be accessed
903 //
904 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
905 return EFI_INVALID_PARAMETER;
906 }
907
908 //
909 // Write return buffer
910 //
911 ASSERT(CpuSaveState != NULL);
912 CopyMem (
913 Buffer,
914 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,
915 Width
916 );
917 } else {
918 //
919 // If 64-bit mode width is zero, then the specified register can not be
920 // accessed
921 //
922 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
923 return EFI_NOT_FOUND;
924 }
925
926 //
927 // If Width is bigger than the 64-bit mode width, then the specified
928 // register can not be accessed
929 //
930 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
931 return EFI_INVALID_PARAMETER;
932 }
933
934 //
935 // Write lower 32-bits of return buffer
936 //
937 CopyMem (
938 Buffer,
939 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,
940 MIN (4, Width)
941 );
942 if (Width >= 4) {
943 //
944 // Write upper 32-bits of return buffer
945 //
946 CopyMem (
947 (UINT8 *)Buffer + 4,
948 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,
949 Width - 4
950 );
951 }
952 }
953 return EFI_SUCCESS;
954 }
955
956 /**
957 Read an SMM Save State register on the target processor. If this function
958 returns EFI_UNSUPPORTED, then the caller is responsible for reading the
959 SMM Save Sate register.
960
961 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
962 value must be between 0 and the NumberOfCpus field in
963 the System Management System Table (SMST).
964 @param[in] Register The SMM Save State register to read.
965 @param[in] Width The number of bytes to read from the CPU save state.
966 @param[out] Buffer Upon return, this holds the CPU register value read
967 from the save state.
968
969 @retval EFI_SUCCESS The register was read from Save State.
970 @retval EFI_INVALID_PARAMTER Buffer is NULL.
971 @retval EFI_UNSUPPORTED This function does not support reading
972 Register.
973 **/
974 EFI_STATUS
975 EFIAPI
976 SmmCpuFeaturesReadSaveStateRegister (
977 IN UINTN CpuIndex,
978 IN EFI_SMM_SAVE_STATE_REGISTER Register,
979 IN UINTN Width,
980 OUT VOID *Buffer
981 )
982 {
983 UINTN RegisterIndex;
984 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
985
986 //
987 // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
988 //
989 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
990 //
991 // Only byte access is supported for this register
992 //
993 if (Width != 1) {
994 return EFI_INVALID_PARAMETER;
995 }
996
997 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
998
999 //
1000 // Check CPU mode
1001 //
1002 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
1003 *(UINT8 *)Buffer = 32;
1004 } else {
1005 *(UINT8 *)Buffer = 64;
1006 }
1007
1008 return EFI_SUCCESS;
1009 }
1010
1011 //
1012 // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
1013 //
1014 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
1015 return EFI_NOT_FOUND;
1016 }
1017
1018 //
1019 // Convert Register to a register lookup table index. Let
1020 // PiSmmCpuDxeSmm implement other special registers (currently
1021 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
1022 //
1023 RegisterIndex = GetRegisterIndex (Register);
1024 if (RegisterIndex == 0) {
1025 return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?
1026 EFI_NOT_FOUND :
1027 EFI_UNSUPPORTED);
1028 }
1029
1030 return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);
1031 }
1032
1033 /**
1034 Writes an SMM Save State register on the target processor. If this function
1035 returns EFI_UNSUPPORTED, then the caller is responsible for writing the
1036 SMM Save Sate register.
1037
1038 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
1039 value must be between 0 and the NumberOfCpus field in
1040 the System Management System Table (SMST).
1041 @param[in] Register The SMM Save State register to write.
1042 @param[in] Width The number of bytes to write to the CPU save state.
1043 @param[in] Buffer Upon entry, this holds the new CPU register value.
1044
1045 @retval EFI_SUCCESS The register was written to Save State.
1046 @retval EFI_INVALID_PARAMTER Buffer is NULL.
1047 @retval EFI_UNSUPPORTED This function does not support writing
1048 Register.
1049 **/
1050 EFI_STATUS
1051 EFIAPI
1052 SmmCpuFeaturesWriteSaveStateRegister (
1053 IN UINTN CpuIndex,
1054 IN EFI_SMM_SAVE_STATE_REGISTER Register,
1055 IN UINTN Width,
1056 IN CONST VOID *Buffer
1057 )
1058 {
1059 UINTN RegisterIndex;
1060 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
1061
1062 //
1063 // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
1064 //
1065 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
1066 return EFI_SUCCESS;
1067 }
1068
1069 //
1070 // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
1071 //
1072 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
1073 return EFI_NOT_FOUND;
1074 }
1075
1076 //
1077 // Convert Register to a register lookup table index. Let
1078 // PiSmmCpuDxeSmm implement other special registers (currently
1079 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
1080 //
1081 RegisterIndex = GetRegisterIndex (Register);
1082 if (RegisterIndex == 0) {
1083 return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?
1084 EFI_NOT_FOUND :
1085 EFI_UNSUPPORTED);
1086 }
1087
1088 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
1089
1090 //
1091 // Do not write non-writable SaveState, because it will cause exception.
1092 //
1093 if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
1094 return EFI_UNSUPPORTED;
1095 }
1096
1097 //
1098 // Check CPU mode
1099 //
1100 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
1101 //
1102 // If 32-bit mode width is zero, then the specified register can not be
1103 // accessed
1104 //
1105 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
1106 return EFI_NOT_FOUND;
1107 }
1108
1109 //
1110 // If Width is bigger than the 32-bit mode width, then the specified
1111 // register can not be accessed
1112 //
1113 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
1114 return EFI_INVALID_PARAMETER;
1115 }
1116 //
1117 // Write SMM State register
1118 //
1119 ASSERT (CpuSaveState != NULL);
1120 CopyMem (
1121 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,
1122 Buffer,
1123 Width
1124 );
1125 } else {
1126 //
1127 // If 64-bit mode width is zero, then the specified register can not be
1128 // accessed
1129 //
1130 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
1131 return EFI_NOT_FOUND;
1132 }
1133
1134 //
1135 // If Width is bigger than the 64-bit mode width, then the specified
1136 // register can not be accessed
1137 //
1138 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
1139 return EFI_INVALID_PARAMETER;
1140 }
1141
1142 //
1143 // Write lower 32-bits of SMM State register
1144 //
1145 CopyMem (
1146 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,
1147 Buffer,
1148 MIN (4, Width)
1149 );
1150 if (Width >= 4) {
1151 //
1152 // Write upper 32-bits of SMM State register
1153 //
1154 CopyMem (
1155 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,
1156 (UINT8 *)Buffer + 4,
1157 Width - 4
1158 );
1159 }
1160 }
1161 return EFI_SUCCESS;
1162 }
1163
1164 /**
1165 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
1166 notification is completely processed.
1167 **/
1168 VOID
1169 EFIAPI
1170 SmmCpuFeaturesCompleteSmmReadyToLock (
1171 VOID
1172 )
1173 {
1174 }
1175
1176 /**
1177 This API provides a method for a CPU to allocate a specific region for
1178 storing page tables.
1179
1180 This API can be called more once to allocate memory for page tables.
1181
1182 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns
1183 a pointer to the allocated buffer. The buffer returned is aligned on a 4KB
1184 boundary. If Pages is 0, then NULL is returned. If there is not enough
1185 memory remaining to satisfy the request, then NULL is returned.
1186
1187 This function can also return NULL if there is no preference on where the
1188 page tables are allocated in SMRAM.
1189
1190 @param Pages The number of 4 KB pages to allocate.
1191
1192 @return A pointer to the allocated buffer for page tables.
1193 @retval NULL Fail to allocate a specific region for storing page tables,
1194 Or there is no preference on where the page tables are
1195 allocated in SMRAM.
1196
1197 **/
1198 VOID *
1199 EFIAPI
1200 SmmCpuFeaturesAllocatePageTableMemory (
1201 IN UINTN Pages
1202 )
1203 {
1204 return NULL;
1205 }
1206
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