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1 /** @file
2 The CPU specific programming for PiSmmCpuDxeSmm module.
3
4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
5
6 This program and the accompanying materials are licensed and made available
7 under the terms and conditions of the BSD License which accompanies this
8 distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
12 WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 **/
14
15 #include <Library/BaseLib.h>
16 #include <Library/BaseMemoryLib.h>
17 #include <Library/DebugLib.h>
18 #include <Library/MemoryAllocationLib.h>
19 #include <Library/PcdLib.h>
20 #include <Library/SmmCpuFeaturesLib.h>
21 #include <Library/SmmServicesTableLib.h>
22 #include <PiSmm.h>
23 #include <Register/QemuSmramSaveStateMap.h>
24
25 //
26 // EFER register LMA bit
27 //
28 #define LMA BIT10
29
30 /**
31 The constructor function
32
33 @param[in] ImageHandle The firmware allocated handle for the EFI image.
34 @param[in] SystemTable A pointer to the EFI System Table.
35
36 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
37
38 **/
39 EFI_STATUS
40 EFIAPI
41 SmmCpuFeaturesLibConstructor (
42 IN EFI_HANDLE ImageHandle,
43 IN EFI_SYSTEM_TABLE *SystemTable
44 )
45 {
46 //
47 // No need to program SMRRs on our virtual platform.
48 //
49 return EFI_SUCCESS;
50 }
51
52 /**
53 Called during the very first SMI into System Management Mode to initialize
54 CPU features, including SMBASE, for the currently executing CPU. Since this
55 is the first SMI, the SMRAM Save State Map is at the default address of
56 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
57 CPU is specified by CpuIndex and CpuIndex can be used to access information
58 about the currently executing CPU in the ProcessorInfo array and the
59 HotPlugCpuData data structure.
60
61 @param[in] CpuIndex The index of the CPU to initialize. The value
62 must be between 0 and the NumberOfCpus field in
63 the System Management System Table (SMST).
64 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
65 was elected as monarch during System Management
66 Mode initialization.
67 FALSE if the CpuIndex is not the index of the CPU
68 that was elected as monarch during System
69 Management Mode initialization.
70 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
71 structures. ProcessorInfo[CpuIndex] contains the
72 information for the currently executing CPU.
73 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
74 contains the ApidId and SmBase arrays.
75 **/
76 VOID
77 EFIAPI
78 SmmCpuFeaturesInitializeProcessor (
79 IN UINTN CpuIndex,
80 IN BOOLEAN IsMonarch,
81 IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,
82 IN CPU_HOT_PLUG_DATA *CpuHotPlugData
83 )
84 {
85 QEMU_SMRAM_SAVE_STATE_MAP *CpuState;
86
87 //
88 // Configure SMBASE.
89 //
90 CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(
91 SMM_DEFAULT_SMBASE +
92 SMRAM_SAVE_STATE_MAP_OFFSET
93 );
94 if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {
95 CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
96 } else {
97 CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
98 }
99
100 //
101 // No need to program SMRRs on our virtual platform.
102 //
103 }
104
105 /**
106 This function updates the SMRAM save state on the currently executing CPU
107 to resume execution at a specific address after an RSM instruction. This
108 function must evaluate the SMRAM save state to determine the execution mode
109 the RSM instruction resumes and update the resume execution address with
110 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
111 flag in the SMRAM save state must always be cleared. This function returns
112 the value of the instruction pointer from the SMRAM save state that was
113 replaced. If this function returns 0, then the SMRAM save state was not
114 modified.
115
116 This function is called during the very first SMI on each CPU after
117 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
118 to signal that the SMBASE of each CPU has been updated before the default
119 SMBASE address is used for the first SMI to the next CPU.
120
121 @param[in] CpuIndex The index of the CPU to hook. The value
122 must be between 0 and the NumberOfCpus
123 field in the System Management System
124 Table (SMST).
125 @param[in] CpuState Pointer to SMRAM Save State Map for the
126 currently executing CPU.
127 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
128 32-bit execution mode from 64-bit SMM.
129 @param[in] NewInstructionPointer Instruction pointer to use if resuming to
130 same execution mode as SMM.
131
132 @retval 0 This function did modify the SMRAM save state.
133 @retval > 0 The original instruction pointer value from the SMRAM save state
134 before it was replaced.
135 **/
136 UINT64
137 EFIAPI
138 SmmCpuFeaturesHookReturnFromSmm (
139 IN UINTN CpuIndex,
140 IN SMRAM_SAVE_STATE_MAP *CpuState,
141 IN UINT64 NewInstructionPointer32,
142 IN UINT64 NewInstructionPointer
143 )
144 {
145 UINT64 OriginalInstructionPointer;
146 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
147
148 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;
149 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
150 OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;
151 CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;
152 //
153 // Clear the auto HALT restart flag so the RSM instruction returns
154 // program control to the instruction following the HLT instruction.
155 //
156 if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != 0) {
157 CpuSaveState->x86.AutoHALTRestart &= ~BIT0;
158 }
159 } else {
160 OriginalInstructionPointer = CpuSaveState->x64._RIP;
161 if ((CpuSaveState->x64.IA32_EFER & LMA) == 0) {
162 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer32;
163 } else {
164 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer;
165 }
166 //
167 // Clear the auto HALT restart flag so the RSM instruction returns
168 // program control to the instruction following the HLT instruction.
169 //
170 if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != 0) {
171 CpuSaveState->x64.AutoHALTRestart &= ~BIT0;
172 }
173 }
174 return OriginalInstructionPointer;
175 }
176
177 /**
178 Hook point in normal execution mode that allows the one CPU that was elected
179 as monarch during System Management Mode initialization to perform additional
180 initialization actions immediately after all of the CPUs have processed their
181 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
182 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
183 **/
184 VOID
185 EFIAPI
186 SmmCpuFeaturesSmmRelocationComplete (
187 VOID
188 )
189 {
190 }
191
192 /**
193 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
194 returned, then a custom SMI handler is not provided by this library,
195 and the default SMI handler must be used.
196
197 @retval 0 Use the default SMI handler.
198 @retval > 0 Use the SMI handler installed by
199 SmmCpuFeaturesInstallSmiHandler(). The caller is required to
200 allocate enough SMRAM for each CPU to support the size of the
201 custom SMI handler.
202 **/
203 UINTN
204 EFIAPI
205 SmmCpuFeaturesGetSmiHandlerSize (
206 VOID
207 )
208 {
209 return 0;
210 }
211
212 /**
213 Install a custom SMI handler for the CPU specified by CpuIndex. This
214 function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size
215 is greater than zero and is called by the CPU that was elected as monarch
216 during System Management Mode initialization.
217
218 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
219 The value must be between 0 and the NumberOfCpus field
220 in the System Management System Table (SMST).
221 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
222 @param[in] SmiStack The stack to use when an SMI is processed by the
223 the CPU specified by CpuIndex.
224 @param[in] StackSize The size, in bytes, if the stack used when an SMI is
225 processed by the CPU specified by CpuIndex.
226 @param[in] GdtBase The base address of the GDT to use when an SMI is
227 processed by the CPU specified by CpuIndex.
228 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
229 processed by the CPU specified by CpuIndex.
230 @param[in] IdtBase The base address of the IDT to use when an SMI is
231 processed by the CPU specified by CpuIndex.
232 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
233 processed by the CPU specified by CpuIndex.
234 @param[in] Cr3 The base address of the page tables to use when an SMI
235 is processed by the CPU specified by CpuIndex.
236 **/
237 VOID
238 EFIAPI
239 SmmCpuFeaturesInstallSmiHandler (
240 IN UINTN CpuIndex,
241 IN UINT32 SmBase,
242 IN VOID *SmiStack,
243 IN UINTN StackSize,
244 IN UINTN GdtBase,
245 IN UINTN GdtSize,
246 IN UINTN IdtBase,
247 IN UINTN IdtSize,
248 IN UINT32 Cr3
249 )
250 {
251 }
252
253 /**
254 Determines if MTRR registers must be configured to set SMRAM cache-ability
255 when executing in System Management Mode.
256
257 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
258 @retval FALSE MTRR registers do not need to be configured to set SMRAM
259 cache-ability.
260 **/
261 BOOLEAN
262 EFIAPI
263 SmmCpuFeaturesNeedConfigureMtrrs (
264 VOID
265 )
266 {
267 return FALSE;
268 }
269
270 /**
271 Disable SMRR register if SMRR is supported and
272 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
273 **/
274 VOID
275 EFIAPI
276 SmmCpuFeaturesDisableSmrr (
277 VOID
278 )
279 {
280 //
281 // No SMRR support, nothing to do
282 //
283 }
284
285 /**
286 Enable SMRR register if SMRR is supported and
287 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
288 **/
289 VOID
290 EFIAPI
291 SmmCpuFeaturesReenableSmrr (
292 VOID
293 )
294 {
295 //
296 // No SMRR support, nothing to do
297 //
298 }
299
300 /**
301 Processor specific hook point each time a CPU enters System Management Mode.
302
303 @param[in] CpuIndex The index of the CPU that has entered SMM. The value
304 must be between 0 and the NumberOfCpus field in the
305 System Management System Table (SMST).
306 **/
307 VOID
308 EFIAPI
309 SmmCpuFeaturesRendezvousEntry (
310 IN UINTN CpuIndex
311 )
312 {
313 //
314 // No SMRR support, nothing to do
315 //
316 }
317
318 /**
319 Processor specific hook point each time a CPU exits System Management Mode.
320
321 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value
322 must be between 0 and the NumberOfCpus field in the
323 System Management System Table (SMST).
324 **/
325 VOID
326 EFIAPI
327 SmmCpuFeaturesRendezvousExit (
328 IN UINTN CpuIndex
329 )
330 {
331 }
332
333 /**
334 Check to see if an SMM register is supported by a specified CPU.
335
336 @param[in] CpuIndex The index of the CPU to check for SMM register support.
337 The value must be between 0 and the NumberOfCpus field
338 in the System Management System Table (SMST).
339 @param[in] RegName Identifies the SMM register to check for support.
340
341 @retval TRUE The SMM register specified by RegName is supported by the CPU
342 specified by CpuIndex.
343 @retval FALSE The SMM register specified by RegName is not supported by the
344 CPU specified by CpuIndex.
345 **/
346 BOOLEAN
347 EFIAPI
348 SmmCpuFeaturesIsSmmRegisterSupported (
349 IN UINTN CpuIndex,
350 IN SMM_REG_NAME RegName
351 )
352 {
353 ASSERT (RegName == SmmRegFeatureControl);
354 return FALSE;
355 }
356
357 /**
358 Returns the current value of the SMM register for the specified CPU.
359 If the SMM register is not supported, then 0 is returned.
360
361 @param[in] CpuIndex The index of the CPU to read the SMM register. The
362 value must be between 0 and the NumberOfCpus field in
363 the System Management System Table (SMST).
364 @param[in] RegName Identifies the SMM register to read.
365
366 @return The value of the SMM register specified by RegName from the CPU
367 specified by CpuIndex.
368 **/
369 UINT64
370 EFIAPI
371 SmmCpuFeaturesGetSmmRegister (
372 IN UINTN CpuIndex,
373 IN SMM_REG_NAME RegName
374 )
375 {
376 //
377 // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.
378 // The last of these should actually be SmmRegSmmDisable, so we can just
379 // return FALSE.
380 //
381 return 0;
382 }
383
384 /**
385 Sets the value of an SMM register on a specified CPU.
386 If the SMM register is not supported, then no action is performed.
387
388 @param[in] CpuIndex The index of the CPU to write the SMM register. The
389 value must be between 0 and the NumberOfCpus field in
390 the System Management System Table (SMST).
391 @param[in] RegName Identifies the SMM register to write.
392 registers are read-only.
393 @param[in] Value The value to write to the SMM register.
394 **/
395 VOID
396 EFIAPI
397 SmmCpuFeaturesSetSmmRegister (
398 IN UINTN CpuIndex,
399 IN SMM_REG_NAME RegName,
400 IN UINT64 Value
401 )
402 {
403 ASSERT (FALSE);
404 }
405
406 ///
407 /// Macro used to simplify the lookup table entries of type
408 /// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
409 ///
410 #define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)
411
412 ///
413 /// Macro used to simplify the lookup table entries of type
414 /// CPU_SMM_SAVE_STATE_REGISTER_RANGE
415 ///
416 #define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
417
418 ///
419 /// Structure used to describe a range of registers
420 ///
421 typedef struct {
422 EFI_SMM_SAVE_STATE_REGISTER Start;
423 EFI_SMM_SAVE_STATE_REGISTER End;
424 UINTN Length;
425 } CPU_SMM_SAVE_STATE_REGISTER_RANGE;
426
427 ///
428 /// Structure used to build a lookup table to retrieve the widths and offsets
429 /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
430 ///
431
432 #define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1
433
434 typedef struct {
435 UINT8 Width32;
436 UINT8 Width64;
437 UINT16 Offset32;
438 UINT16 Offset64Lo;
439 UINT16 Offset64Hi;
440 BOOLEAN Writeable;
441 } CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
442
443 ///
444 /// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
445 /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
446 ///
447 STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
448 SMM_REGISTER_RANGE (
449 EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,
450 EFI_SMM_SAVE_STATE_REGISTER_LDTINFO
451 ),
452 SMM_REGISTER_RANGE (
453 EFI_SMM_SAVE_STATE_REGISTER_ES,
454 EFI_SMM_SAVE_STATE_REGISTER_RIP
455 ),
456 SMM_REGISTER_RANGE (
457 EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,
458 EFI_SMM_SAVE_STATE_REGISTER_CR4
459 ),
460 { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }
461 };
462
463 ///
464 /// Lookup table used to retrieve the widths and offsets associated with each
465 /// supported EFI_SMM_SAVE_STATE_REGISTER value
466 ///
467 STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
468 {
469 0, // Width32
470 0, // Width64
471 0, // Offset32
472 0, // Offset64Lo
473 0, // Offset64Hi
474 FALSE // Writeable
475 }, // Reserved
476
477 //
478 // CPU Save State registers defined in PI SMM CPU Protocol.
479 //
480 {
481 0, // Width32
482 8, // Width64
483 0, // Offset32
484 SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo
485 SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi
486 FALSE // Writeable
487 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
488
489 {
490 0, // Width32
491 8, // Width64
492 0, // Offset32
493 SMM_CPU_OFFSET (x64._IDTRBase), // Offset64Lo
494 SMM_CPU_OFFSET (x64._IDTRBase) + 4, // Offset64Hi
495 FALSE // Writeable
496 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
497
498 {
499 0, // Width32
500 8, // Width64
501 0, // Offset32
502 SMM_CPU_OFFSET (x64._LDTRBase), // Offset64Lo
503 SMM_CPU_OFFSET (x64._LDTRBase) + 4, // Offset64Hi
504 FALSE // Writeable
505 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
506
507 {
508 0, // Width32
509 0, // Width64
510 0, // Offset32
511 SMM_CPU_OFFSET (x64._GDTRLimit), // Offset64Lo
512 SMM_CPU_OFFSET (x64._GDTRLimit) + 4, // Offset64Hi
513 FALSE // Writeable
514 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
515
516 {
517 0, // Width32
518 0, // Width64
519 0, // Offset32
520 SMM_CPU_OFFSET (x64._IDTRLimit), // Offset64Lo
521 SMM_CPU_OFFSET (x64._IDTRLimit) + 4, // Offset64Hi
522 FALSE // Writeable
523 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
524
525 {
526 0, // Width32
527 0, // Width64
528 0, // Offset32
529 SMM_CPU_OFFSET (x64._LDTRLimit), // Offset64Lo
530 SMM_CPU_OFFSET (x64._LDTRLimit) + 4, // Offset64Hi
531 FALSE // Writeable
532 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
533
534 {
535 0, // Width32
536 0, // Width64
537 0, // Offset32
538 0, // Offset64Lo
539 0 + 4, // Offset64Hi
540 FALSE // Writeable
541 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
542
543 {
544 4, // Width32
545 4, // Width64
546 SMM_CPU_OFFSET (x86._ES), // Offset32
547 SMM_CPU_OFFSET (x64._ES), // Offset64Lo
548 0, // Offset64Hi
549 FALSE // Writeable
550 }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
551
552 {
553 4, // Width32
554 4, // Width64
555 SMM_CPU_OFFSET (x86._CS), // Offset32
556 SMM_CPU_OFFSET (x64._CS), // Offset64Lo
557 0, // Offset64Hi
558 FALSE // Writeable
559 }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
560
561 {
562 4, // Width32
563 4, // Width64
564 SMM_CPU_OFFSET (x86._SS), // Offset32
565 SMM_CPU_OFFSET (x64._SS), // Offset64Lo
566 0, // Offset64Hi
567 FALSE // Writeable
568 }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
569
570 {
571 4, // Width32
572 4, // Width64
573 SMM_CPU_OFFSET (x86._DS), // Offset32
574 SMM_CPU_OFFSET (x64._DS), // Offset64Lo
575 0, // Offset64Hi
576 FALSE // Writeable
577 }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
578
579 {
580 4, // Width32
581 4, // Width64
582 SMM_CPU_OFFSET (x86._FS), // Offset32
583 SMM_CPU_OFFSET (x64._FS), // Offset64Lo
584 0, // Offset64Hi
585 FALSE // Writeable
586 }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
587
588 {
589 4, // Width32
590 4, // Width64
591 SMM_CPU_OFFSET (x86._GS), // Offset32
592 SMM_CPU_OFFSET (x64._GS), // Offset64Lo
593 0, // Offset64Hi
594 FALSE // Writeable
595 }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
596
597 {
598 0, // Width32
599 4, // Width64
600 0, // Offset32
601 SMM_CPU_OFFSET (x64._LDTR), // Offset64Lo
602 0, // Offset64Hi
603 FALSE // Writeable
604 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
605
606 {
607 4, // Width32
608 4, // Width64
609 SMM_CPU_OFFSET (x86._TR), // Offset32
610 SMM_CPU_OFFSET (x64._TR), // Offset64Lo
611 0, // Offset64Hi
612 FALSE // Writeable
613 }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
614
615 {
616 4, // Width32
617 8, // Width64
618 SMM_CPU_OFFSET (x86._DR7), // Offset32
619 SMM_CPU_OFFSET (x64._DR7), // Offset64Lo
620 SMM_CPU_OFFSET (x64._DR7) + 4, // Offset64Hi
621 FALSE // Writeable
622 }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
623
624 {
625 4, // Width32
626 8, // Width64
627 SMM_CPU_OFFSET (x86._DR6), // Offset32
628 SMM_CPU_OFFSET (x64._DR6), // Offset64Lo
629 SMM_CPU_OFFSET (x64._DR6) + 4, // Offset64Hi
630 FALSE // Writeable
631 }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
632
633 {
634 0, // Width32
635 8, // Width64
636 0, // Offset32
637 SMM_CPU_OFFSET (x64._R8), // Offset64Lo
638 SMM_CPU_OFFSET (x64._R8) + 4, // Offset64Hi
639 TRUE // Writeable
640 }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
641
642 {
643 0, // Width32
644 8, // Width64
645 0, // Offset32
646 SMM_CPU_OFFSET (x64._R9), // Offset64Lo
647 SMM_CPU_OFFSET (x64._R9) + 4, // Offset64Hi
648 TRUE // Writeable
649 }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
650
651 {
652 0, // Width32
653 8, // Width64
654 0, // Offset32
655 SMM_CPU_OFFSET (x64._R10), // Offset64Lo
656 SMM_CPU_OFFSET (x64._R10) + 4, // Offset64Hi
657 TRUE // Writeable
658 }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
659
660 {
661 0, // Width32
662 8, // Width64
663 0, // Offset32
664 SMM_CPU_OFFSET (x64._R11), // Offset64Lo
665 SMM_CPU_OFFSET (x64._R11) + 4, // Offset64Hi
666 TRUE // Writeable
667 }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
668
669 {
670 0, // Width32
671 8, // Width64
672 0, // Offset32
673 SMM_CPU_OFFSET (x64._R12), // Offset64Lo
674 SMM_CPU_OFFSET (x64._R12) + 4, // Offset64Hi
675 TRUE // Writeable
676 }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
677
678 {
679 0, // Width32
680 8, // Width64
681 0, // Offset32
682 SMM_CPU_OFFSET (x64._R13), // Offset64Lo
683 SMM_CPU_OFFSET (x64._R13) + 4, // Offset64Hi
684 TRUE // Writeable
685 }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
686
687 {
688 0, // Width32
689 8, // Width64
690 0, // Offset32
691 SMM_CPU_OFFSET (x64._R14), // Offset64Lo
692 SMM_CPU_OFFSET (x64._R14) + 4, // Offset64Hi
693 TRUE // Writeable
694 }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
695
696 {
697 0, // Width32
698 8, // Width64
699 0, // Offset32
700 SMM_CPU_OFFSET (x64._R15), // Offset64Lo
701 SMM_CPU_OFFSET (x64._R15) + 4, // Offset64Hi
702 TRUE // Writeable
703 }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
704
705 {
706 4, // Width32
707 8, // Width64
708 SMM_CPU_OFFSET (x86._EAX), // Offset32
709 SMM_CPU_OFFSET (x64._RAX), // Offset64Lo
710 SMM_CPU_OFFSET (x64._RAX) + 4, // Offset64Hi
711 TRUE // Writeable
712 }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
713
714 {
715 4, // Width32
716 8, // Width64
717 SMM_CPU_OFFSET (x86._EBX), // Offset32
718 SMM_CPU_OFFSET (x64._RBX), // Offset64Lo
719 SMM_CPU_OFFSET (x64._RBX) + 4, // Offset64Hi
720 TRUE // Writeable
721 }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
722
723 {
724 4, // Width32
725 8, // Width64
726 SMM_CPU_OFFSET (x86._ECX), // Offset32
727 SMM_CPU_OFFSET (x64._RCX), // Offset64Lo
728 SMM_CPU_OFFSET (x64._RCX) + 4, // Offset64Hi
729 TRUE // Writeable
730 }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
731
732 {
733 4, // Width32
734 8, // Width64
735 SMM_CPU_OFFSET (x86._EDX), // Offset32
736 SMM_CPU_OFFSET (x64._RDX), // Offset64Lo
737 SMM_CPU_OFFSET (x64._RDX) + 4, // Offset64Hi
738 TRUE // Writeable
739 }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
740
741 {
742 4, // Width32
743 8, // Width64
744 SMM_CPU_OFFSET (x86._ESP), // Offset32
745 SMM_CPU_OFFSET (x64._RSP), // Offset64Lo
746 SMM_CPU_OFFSET (x64._RSP) + 4, // Offset64Hi
747 TRUE // Writeable
748 }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
749
750 {
751 4, // Width32
752 8, // Width64
753 SMM_CPU_OFFSET (x86._EBP), // Offset32
754 SMM_CPU_OFFSET (x64._RBP), // Offset64Lo
755 SMM_CPU_OFFSET (x64._RBP) + 4, // Offset64Hi
756 TRUE // Writeable
757 }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
758
759 {
760 4, // Width32
761 8, // Width64
762 SMM_CPU_OFFSET (x86._ESI), // Offset32
763 SMM_CPU_OFFSET (x64._RSI), // Offset64Lo
764 SMM_CPU_OFFSET (x64._RSI) + 4, // Offset64Hi
765 TRUE // Writeable
766 }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
767
768 {
769 4, // Width32
770 8, // Width64
771 SMM_CPU_OFFSET (x86._EDI), // Offset32
772 SMM_CPU_OFFSET (x64._RDI), // Offset64Lo
773 SMM_CPU_OFFSET (x64._RDI) + 4, // Offset64Hi
774 TRUE // Writeable
775 }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
776
777 {
778 4, // Width32
779 8, // Width64
780 SMM_CPU_OFFSET (x86._EIP), // Offset32
781 SMM_CPU_OFFSET (x64._RIP), // Offset64Lo
782 SMM_CPU_OFFSET (x64._RIP) + 4, // Offset64Hi
783 TRUE // Writeable
784 }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
785
786 {
787 4, // Width32
788 8, // Width64
789 SMM_CPU_OFFSET (x86._EFLAGS), // Offset32
790 SMM_CPU_OFFSET (x64._RFLAGS), // Offset64Lo
791 SMM_CPU_OFFSET (x64._RFLAGS) + 4, // Offset64Hi
792 TRUE // Writeable
793 }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
794
795 {
796 4, // Width32
797 8, // Width64
798 SMM_CPU_OFFSET (x86._CR0), // Offset32
799 SMM_CPU_OFFSET (x64._CR0), // Offset64Lo
800 SMM_CPU_OFFSET (x64._CR0) + 4, // Offset64Hi
801 FALSE // Writeable
802 }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
803
804 {
805 4, // Width32
806 8, // Width64
807 SMM_CPU_OFFSET (x86._CR3), // Offset32
808 SMM_CPU_OFFSET (x64._CR3), // Offset64Lo
809 SMM_CPU_OFFSET (x64._CR3) + 4, // Offset64Hi
810 FALSE // Writeable
811 }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
812
813 {
814 0, // Width32
815 4, // Width64
816 0, // Offset32
817 SMM_CPU_OFFSET (x64._CR4), // Offset64Lo
818 SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi
819 FALSE // Writeable
820 }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
821 };
822
823 //
824 // No support for I/O restart
825 //
826
827 /**
828 Read information from the CPU save state.
829
830 @param Register Specifies the CPU register to read form the save state.
831
832 @retval 0 Register is not valid
833 @retval >0 Index into mSmmCpuWidthOffset[] associated with Register
834
835 **/
836 STATIC
837 UINTN
838 GetRegisterIndex (
839 IN EFI_SMM_SAVE_STATE_REGISTER Register
840 )
841 {
842 UINTN Index;
843 UINTN Offset;
844
845 for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX;
846 mSmmCpuRegisterRanges[Index].Length != 0;
847 Index++) {
848 if (Register >= mSmmCpuRegisterRanges[Index].Start &&
849 Register <= mSmmCpuRegisterRanges[Index].End) {
850 return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
851 }
852 Offset += mSmmCpuRegisterRanges[Index].Length;
853 }
854 return 0;
855 }
856
857 /**
858 Read a CPU Save State register on the target processor.
859
860 This function abstracts the differences that whether the CPU Save State
861 register is in the IA32 CPU Save State Map or X64 CPU Save State Map.
862
863 This function supports reading a CPU Save State register in SMBase relocation
864 handler.
865
866 @param[in] CpuIndex Specifies the zero-based index of the CPU save
867 state.
868 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
869 @param[in] Width The number of bytes to read from the CPU save
870 state.
871 @param[out] Buffer Upon return, this holds the CPU register value
872 read from the save state.
873
874 @retval EFI_SUCCESS The register was read from Save State.
875 @retval EFI_NOT_FOUND The register is not defined for the Save State
876 of Processor.
877 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
878
879 **/
880 STATIC
881 EFI_STATUS
882 ReadSaveStateRegisterByIndex (
883 IN UINTN CpuIndex,
884 IN UINTN RegisterIndex,
885 IN UINTN Width,
886 OUT VOID *Buffer
887 )
888 {
889 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
890
891 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
892
893 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
894 //
895 // If 32-bit mode width is zero, then the specified register can not be
896 // accessed
897 //
898 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
899 return EFI_NOT_FOUND;
900 }
901
902 //
903 // If Width is bigger than the 32-bit mode width, then the specified
904 // register can not be accessed
905 //
906 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
907 return EFI_INVALID_PARAMETER;
908 }
909
910 //
911 // Write return buffer
912 //
913 ASSERT(CpuSaveState != NULL);
914 CopyMem (
915 Buffer,
916 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,
917 Width
918 );
919 } else {
920 //
921 // If 64-bit mode width is zero, then the specified register can not be
922 // accessed
923 //
924 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
925 return EFI_NOT_FOUND;
926 }
927
928 //
929 // If Width is bigger than the 64-bit mode width, then the specified
930 // register can not be accessed
931 //
932 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
933 return EFI_INVALID_PARAMETER;
934 }
935
936 //
937 // Write lower 32-bits of return buffer
938 //
939 CopyMem (
940 Buffer,
941 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,
942 MIN (4, Width)
943 );
944 if (Width >= 4) {
945 //
946 // Write upper 32-bits of return buffer
947 //
948 CopyMem (
949 (UINT8 *)Buffer + 4,
950 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,
951 Width - 4
952 );
953 }
954 }
955 return EFI_SUCCESS;
956 }
957
958 /**
959 Read an SMM Save State register on the target processor. If this function
960 returns EFI_UNSUPPORTED, then the caller is responsible for reading the
961 SMM Save Sate register.
962
963 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
964 value must be between 0 and the NumberOfCpus field in
965 the System Management System Table (SMST).
966 @param[in] Register The SMM Save State register to read.
967 @param[in] Width The number of bytes to read from the CPU save state.
968 @param[out] Buffer Upon return, this holds the CPU register value read
969 from the save state.
970
971 @retval EFI_SUCCESS The register was read from Save State.
972 @retval EFI_INVALID_PARAMTER Buffer is NULL.
973 @retval EFI_UNSUPPORTED This function does not support reading
974 Register.
975 **/
976 EFI_STATUS
977 EFIAPI
978 SmmCpuFeaturesReadSaveStateRegister (
979 IN UINTN CpuIndex,
980 IN EFI_SMM_SAVE_STATE_REGISTER Register,
981 IN UINTN Width,
982 OUT VOID *Buffer
983 )
984 {
985 UINTN RegisterIndex;
986 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
987
988 //
989 // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
990 //
991 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
992 //
993 // Only byte access is supported for this register
994 //
995 if (Width != 1) {
996 return EFI_INVALID_PARAMETER;
997 }
998
999 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
1000
1001 //
1002 // Check CPU mode
1003 //
1004 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
1005 *(UINT8 *)Buffer = 32;
1006 } else {
1007 *(UINT8 *)Buffer = 64;
1008 }
1009
1010 return EFI_SUCCESS;
1011 }
1012
1013 //
1014 // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
1015 //
1016 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
1017 return EFI_NOT_FOUND;
1018 }
1019
1020 //
1021 // Convert Register to a register lookup table index. Let
1022 // PiSmmCpuDxeSmm implement other special registers (currently
1023 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
1024 //
1025 RegisterIndex = GetRegisterIndex (Register);
1026 if (RegisterIndex == 0) {
1027 return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?
1028 EFI_NOT_FOUND :
1029 EFI_UNSUPPORTED);
1030 }
1031
1032 return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);
1033 }
1034
1035 /**
1036 Writes an SMM Save State register on the target processor. If this function
1037 returns EFI_UNSUPPORTED, then the caller is responsible for writing the
1038 SMM Save Sate register.
1039
1040 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
1041 value must be between 0 and the NumberOfCpus field in
1042 the System Management System Table (SMST).
1043 @param[in] Register The SMM Save State register to write.
1044 @param[in] Width The number of bytes to write to the CPU save state.
1045 @param[in] Buffer Upon entry, this holds the new CPU register value.
1046
1047 @retval EFI_SUCCESS The register was written to Save State.
1048 @retval EFI_INVALID_PARAMTER Buffer is NULL.
1049 @retval EFI_UNSUPPORTED This function does not support writing
1050 Register.
1051 **/
1052 EFI_STATUS
1053 EFIAPI
1054 SmmCpuFeaturesWriteSaveStateRegister (
1055 IN UINTN CpuIndex,
1056 IN EFI_SMM_SAVE_STATE_REGISTER Register,
1057 IN UINTN Width,
1058 IN CONST VOID *Buffer
1059 )
1060 {
1061 UINTN RegisterIndex;
1062 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
1063
1064 //
1065 // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
1066 //
1067 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
1068 return EFI_SUCCESS;
1069 }
1070
1071 //
1072 // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
1073 //
1074 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
1075 return EFI_NOT_FOUND;
1076 }
1077
1078 //
1079 // Convert Register to a register lookup table index. Let
1080 // PiSmmCpuDxeSmm implement other special registers (currently
1081 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
1082 //
1083 RegisterIndex = GetRegisterIndex (Register);
1084 if (RegisterIndex == 0) {
1085 return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?
1086 EFI_NOT_FOUND :
1087 EFI_UNSUPPORTED);
1088 }
1089
1090 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
1091
1092 //
1093 // Do not write non-writable SaveState, because it will cause exception.
1094 //
1095 if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
1096 return EFI_UNSUPPORTED;
1097 }
1098
1099 //
1100 // Check CPU mode
1101 //
1102 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
1103 //
1104 // If 32-bit mode width is zero, then the specified register can not be
1105 // accessed
1106 //
1107 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
1108 return EFI_NOT_FOUND;
1109 }
1110
1111 //
1112 // If Width is bigger than the 32-bit mode width, then the specified
1113 // register can not be accessed
1114 //
1115 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
1116 return EFI_INVALID_PARAMETER;
1117 }
1118 //
1119 // Write SMM State register
1120 //
1121 ASSERT (CpuSaveState != NULL);
1122 CopyMem (
1123 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,
1124 Buffer,
1125 Width
1126 );
1127 } else {
1128 //
1129 // If 64-bit mode width is zero, then the specified register can not be
1130 // accessed
1131 //
1132 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
1133 return EFI_NOT_FOUND;
1134 }
1135
1136 //
1137 // If Width is bigger than the 64-bit mode width, then the specified
1138 // register can not be accessed
1139 //
1140 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
1141 return EFI_INVALID_PARAMETER;
1142 }
1143
1144 //
1145 // Write lower 32-bits of SMM State register
1146 //
1147 CopyMem (
1148 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,
1149 Buffer,
1150 MIN (4, Width)
1151 );
1152 if (Width >= 4) {
1153 //
1154 // Write upper 32-bits of SMM State register
1155 //
1156 CopyMem (
1157 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,
1158 (UINT8 *)Buffer + 4,
1159 Width - 4
1160 );
1161 }
1162 }
1163 return EFI_SUCCESS;
1164 }
1165
1166 /**
1167 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
1168 notification is completely processed.
1169 **/
1170 VOID
1171 EFIAPI
1172 SmmCpuFeaturesCompleteSmmReadyToLock (
1173 VOID
1174 )
1175 {
1176 }
1177
1178 /**
1179 This API provides a method for a CPU to allocate a specific region for
1180 storing page tables.
1181
1182 This API can be called more once to allocate memory for page tables.
1183
1184 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns
1185 a pointer to the allocated buffer. The buffer returned is aligned on a 4KB
1186 boundary. If Pages is 0, then NULL is returned. If there is not enough
1187 memory remaining to satisfy the request, then NULL is returned.
1188
1189 This function can also return NULL if there is no preference on where the
1190 page tables are allocated in SMRAM.
1191
1192 @param Pages The number of 4 KB pages to allocate.
1193
1194 @return A pointer to the allocated buffer for page tables.
1195 @retval NULL Fail to allocate a specific region for storing page tables,
1196 Or there is no preference on where the page tables are
1197 allocated in SMRAM.
1198
1199 **/
1200 VOID *
1201 EFIAPI
1202 SmmCpuFeaturesAllocatePageTableMemory (
1203 IN UINTN Pages
1204 )
1205 {
1206 return NULL;
1207 }
1208
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