2 The CPU specific programming for PiSmmCpuDxeSmm module.
4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials are licensed and made available
7 under the terms and conditions of the BSD License which accompanies this
8 distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
12 WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Library/BaseLib.h>
16 #include <Library/BaseMemoryLib.h>
17 #include <Library/DebugLib.h>
18 #include <Library/MemoryAllocationLib.h>
19 #include <Library/PcdLib.h>
20 #include <Library/SmmCpuFeaturesLib.h>
21 #include <Library/SmmServicesTableLib.h>
23 #include <Register/QemuSmramSaveStateMap.h>
26 // EFER register LMA bit
31 The constructor function
33 @param[in] ImageHandle The firmware allocated handle for the EFI image.
34 @param[in] SystemTable A pointer to the EFI System Table.
36 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
41 SmmCpuFeaturesLibConstructor (
42 IN EFI_HANDLE ImageHandle
,
43 IN EFI_SYSTEM_TABLE
*SystemTable
47 // No need to program SMRRs on our virtual platform.
53 Called during the very first SMI into System Management Mode to initialize
54 CPU features, including SMBASE, for the currently executing CPU. Since this
55 is the first SMI, the SMRAM Save State Map is at the default address of
56 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
57 CPU is specified by CpuIndex and CpuIndex can be used to access information
58 about the currently executing CPU in the ProcessorInfo array and the
59 HotPlugCpuData data structure.
61 @param[in] CpuIndex The index of the CPU to initialize. The value
62 must be between 0 and the NumberOfCpus field in
63 the System Management System Table (SMST).
64 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
65 was elected as monarch during System Management
67 FALSE if the CpuIndex is not the index of the CPU
68 that was elected as monarch during System
69 Management Mode initialization.
70 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
71 structures. ProcessorInfo[CpuIndex] contains the
72 information for the currently executing CPU.
73 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
74 contains the ApidId and SmBase arrays.
78 SmmCpuFeaturesInitializeProcessor (
81 IN EFI_PROCESSOR_INFORMATION
*ProcessorInfo
,
82 IN CPU_HOT_PLUG_DATA
*CpuHotPlugData
85 QEMU_SMRAM_SAVE_STATE_MAP
*CpuState
;
90 CpuState
= (QEMU_SMRAM_SAVE_STATE_MAP
*)(UINTN
)(
92 SMRAM_SAVE_STATE_MAP_OFFSET
94 if ((CpuState
->x86
.SMMRevId
& 0xFFFF) == 0) {
95 CpuState
->x86
.SMBASE
= (UINT32
)CpuHotPlugData
->SmBase
[CpuIndex
];
97 CpuState
->x64
.SMBASE
= (UINT32
)CpuHotPlugData
->SmBase
[CpuIndex
];
101 // No need to program SMRRs on our virtual platform.
106 This function updates the SMRAM save state on the currently executing CPU
107 to resume execution at a specific address after an RSM instruction. This
108 function must evaluate the SMRAM save state to determine the execution mode
109 the RSM instruction resumes and update the resume execution address with
110 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
111 flag in the SMRAM save state must always be cleared. This function returns
112 the value of the instruction pointer from the SMRAM save state that was
113 replaced. If this function returns 0, then the SMRAM save state was not
116 This function is called during the very first SMI on each CPU after
117 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
118 to signal that the SMBASE of each CPU has been updated before the default
119 SMBASE address is used for the first SMI to the next CPU.
121 @param[in] CpuIndex The index of the CPU to hook. The value
122 must be between 0 and the NumberOfCpus
123 field in the System Management System
125 @param[in] CpuState Pointer to SMRAM Save State Map for the
126 currently executing CPU.
127 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
128 32-bit execution mode from 64-bit SMM.
129 @param[in] NewInstructionPointer Instruction pointer to use if resuming to
130 same execution mode as SMM.
132 @retval 0 This function did modify the SMRAM save state.
133 @retval > 0 The original instruction pointer value from the SMRAM save state
134 before it was replaced.
138 SmmCpuFeaturesHookReturnFromSmm (
140 IN SMRAM_SAVE_STATE_MAP
*CpuState
,
141 IN UINT64 NewInstructionPointer32
,
142 IN UINT64 NewInstructionPointer
145 UINT64 OriginalInstructionPointer
;
146 QEMU_SMRAM_SAVE_STATE_MAP
*CpuSaveState
;
148 CpuSaveState
= (QEMU_SMRAM_SAVE_STATE_MAP
*)CpuState
;
149 if ((CpuSaveState
->x86
.SMMRevId
& 0xFFFF) == 0) {
150 OriginalInstructionPointer
= (UINT64
)CpuSaveState
->x86
._EIP
;
151 CpuSaveState
->x86
._EIP
= (UINT32
)NewInstructionPointer
;
153 // Clear the auto HALT restart flag so the RSM instruction returns
154 // program control to the instruction following the HLT instruction.
156 if ((CpuSaveState
->x86
.AutoHALTRestart
& BIT0
) != 0) {
157 CpuSaveState
->x86
.AutoHALTRestart
&= ~BIT0
;
160 OriginalInstructionPointer
= CpuSaveState
->x64
._RIP
;
161 if ((CpuSaveState
->x64
.IA32_EFER
& LMA
) == 0) {
162 CpuSaveState
->x64
._RIP
= (UINT32
)NewInstructionPointer32
;
164 CpuSaveState
->x64
._RIP
= (UINT32
)NewInstructionPointer
;
167 // Clear the auto HALT restart flag so the RSM instruction returns
168 // program control to the instruction following the HLT instruction.
170 if ((CpuSaveState
->x64
.AutoHALTRestart
& BIT0
) != 0) {
171 CpuSaveState
->x64
.AutoHALTRestart
&= ~BIT0
;
174 return OriginalInstructionPointer
;
178 Hook point in normal execution mode that allows the one CPU that was elected
179 as monarch during System Management Mode initialization to perform additional
180 initialization actions immediately after all of the CPUs have processed their
181 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
182 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
186 SmmCpuFeaturesSmmRelocationComplete (
193 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
194 returned, then a custom SMI handler is not provided by this library,
195 and the default SMI handler must be used.
197 @retval 0 Use the default SMI handler.
198 @retval > 0 Use the SMI handler installed by
199 SmmCpuFeaturesInstallSmiHandler(). The caller is required to
200 allocate enough SMRAM for each CPU to support the size of the
205 SmmCpuFeaturesGetSmiHandlerSize (
213 Install a custom SMI handler for the CPU specified by CpuIndex. This
214 function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size
215 is greater than zero and is called by the CPU that was elected as monarch
216 during System Management Mode initialization.
218 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
219 The value must be between 0 and the NumberOfCpus field
220 in the System Management System Table (SMST).
221 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
222 @param[in] SmiStack The stack to use when an SMI is processed by the
223 the CPU specified by CpuIndex.
224 @param[in] StackSize The size, in bytes, if the stack used when an SMI is
225 processed by the CPU specified by CpuIndex.
226 @param[in] GdtBase The base address of the GDT to use when an SMI is
227 processed by the CPU specified by CpuIndex.
228 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
229 processed by the CPU specified by CpuIndex.
230 @param[in] IdtBase The base address of the IDT to use when an SMI is
231 processed by the CPU specified by CpuIndex.
232 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
233 processed by the CPU specified by CpuIndex.
234 @param[in] Cr3 The base address of the page tables to use when an SMI
235 is processed by the CPU specified by CpuIndex.
239 SmmCpuFeaturesInstallSmiHandler (
254 Determines if MTRR registers must be configured to set SMRAM cache-ability
255 when executing in System Management Mode.
257 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
258 @retval FALSE MTRR registers do not need to be configured to set SMRAM
263 SmmCpuFeaturesNeedConfigureMtrrs (
271 Disable SMRR register if SMRR is supported and
272 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
276 SmmCpuFeaturesDisableSmrr (
281 // No SMRR support, nothing to do
286 Enable SMRR register if SMRR is supported and
287 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
291 SmmCpuFeaturesReenableSmrr (
296 // No SMRR support, nothing to do
301 Processor specific hook point each time a CPU enters System Management Mode.
303 @param[in] CpuIndex The index of the CPU that has entered SMM. The value
304 must be between 0 and the NumberOfCpus field in the
305 System Management System Table (SMST).
309 SmmCpuFeaturesRendezvousEntry (
314 // No SMRR support, nothing to do
319 Processor specific hook point each time a CPU exits System Management Mode.
321 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value
322 must be between 0 and the NumberOfCpus field in the
323 System Management System Table (SMST).
327 SmmCpuFeaturesRendezvousExit (
334 Check to see if an SMM register is supported by a specified CPU.
336 @param[in] CpuIndex The index of the CPU to check for SMM register support.
337 The value must be between 0 and the NumberOfCpus field
338 in the System Management System Table (SMST).
339 @param[in] RegName Identifies the SMM register to check for support.
341 @retval TRUE The SMM register specified by RegName is supported by the CPU
342 specified by CpuIndex.
343 @retval FALSE The SMM register specified by RegName is not supported by the
344 CPU specified by CpuIndex.
348 SmmCpuFeaturesIsSmmRegisterSupported (
350 IN SMM_REG_NAME RegName
353 ASSERT (RegName
== SmmRegFeatureControl
);
358 Returns the current value of the SMM register for the specified CPU.
359 If the SMM register is not supported, then 0 is returned.
361 @param[in] CpuIndex The index of the CPU to read the SMM register. The
362 value must be between 0 and the NumberOfCpus field in
363 the System Management System Table (SMST).
364 @param[in] RegName Identifies the SMM register to read.
366 @return The value of the SMM register specified by RegName from the CPU
367 specified by CpuIndex.
371 SmmCpuFeaturesGetSmmRegister (
373 IN SMM_REG_NAME RegName
377 // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.
378 // The last of these should actually be SmmRegSmmDisable, so we can just
385 Sets the value of an SMM register on a specified CPU.
386 If the SMM register is not supported, then no action is performed.
388 @param[in] CpuIndex The index of the CPU to write the SMM register. The
389 value must be between 0 and the NumberOfCpus field in
390 the System Management System Table (SMST).
391 @param[in] RegName Identifies the SMM register to write.
392 registers are read-only.
393 @param[in] Value The value to write to the SMM register.
397 SmmCpuFeaturesSetSmmRegister (
399 IN SMM_REG_NAME RegName
,
407 /// Macro used to simplify the lookup table entries of type
408 /// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
410 #define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)
413 /// Macro used to simplify the lookup table entries of type
414 /// CPU_SMM_SAVE_STATE_REGISTER_RANGE
416 #define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
419 /// Structure used to describe a range of registers
422 EFI_SMM_SAVE_STATE_REGISTER Start
;
423 EFI_SMM_SAVE_STATE_REGISTER End
;
425 } CPU_SMM_SAVE_STATE_REGISTER_RANGE
;
428 /// Structure used to build a lookup table to retrieve the widths and offsets
429 /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
432 #define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1
441 } CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
;
444 /// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
445 /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
447 STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges
[] = {
449 EFI_SMM_SAVE_STATE_REGISTER_GDTBASE
,
450 EFI_SMM_SAVE_STATE_REGISTER_LDTINFO
453 EFI_SMM_SAVE_STATE_REGISTER_ES
,
454 EFI_SMM_SAVE_STATE_REGISTER_RIP
457 EFI_SMM_SAVE_STATE_REGISTER_RFLAGS
,
458 EFI_SMM_SAVE_STATE_REGISTER_CR4
460 { (EFI_SMM_SAVE_STATE_REGISTER
)0, (EFI_SMM_SAVE_STATE_REGISTER
)0, 0 }
464 /// Lookup table used to retrieve the widths and offsets associated with each
465 /// supported EFI_SMM_SAVE_STATE_REGISTER value
467 STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset
[] = {
478 // CPU Save State registers defined in PI SMM CPU Protocol.
484 SMM_CPU_OFFSET (x64
._GDTRBase
), // Offset64Lo
485 SMM_CPU_OFFSET (x64
._GDTRBase
) + 4, // Offset64Hi
487 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
493 SMM_CPU_OFFSET (x64
._IDTRBase
), // Offset64Lo
494 SMM_CPU_OFFSET (x64
._IDTRBase
) + 4, // Offset64Hi
496 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
502 SMM_CPU_OFFSET (x64
._LDTRBase
), // Offset64Lo
503 SMM_CPU_OFFSET (x64
._LDTRBase
) + 4, // Offset64Hi
505 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
511 SMM_CPU_OFFSET (x64
._GDTRLimit
), // Offset64Lo
512 SMM_CPU_OFFSET (x64
._GDTRLimit
) + 4, // Offset64Hi
514 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
520 SMM_CPU_OFFSET (x64
._IDTRLimit
), // Offset64Lo
521 SMM_CPU_OFFSET (x64
._IDTRLimit
) + 4, // Offset64Hi
523 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
529 SMM_CPU_OFFSET (x64
._LDTRLimit
), // Offset64Lo
530 SMM_CPU_OFFSET (x64
._LDTRLimit
) + 4, // Offset64Hi
532 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
541 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
546 SMM_CPU_OFFSET (x86
._ES
), // Offset32
547 SMM_CPU_OFFSET (x64
._ES
), // Offset64Lo
550 }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
555 SMM_CPU_OFFSET (x86
._CS
), // Offset32
556 SMM_CPU_OFFSET (x64
._CS
), // Offset64Lo
559 }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
564 SMM_CPU_OFFSET (x86
._SS
), // Offset32
565 SMM_CPU_OFFSET (x64
._SS
), // Offset64Lo
568 }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
573 SMM_CPU_OFFSET (x86
._DS
), // Offset32
574 SMM_CPU_OFFSET (x64
._DS
), // Offset64Lo
577 }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
582 SMM_CPU_OFFSET (x86
._FS
), // Offset32
583 SMM_CPU_OFFSET (x64
._FS
), // Offset64Lo
586 }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
591 SMM_CPU_OFFSET (x86
._GS
), // Offset32
592 SMM_CPU_OFFSET (x64
._GS
), // Offset64Lo
595 }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
601 SMM_CPU_OFFSET (x64
._LDTR
), // Offset64Lo
604 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
609 SMM_CPU_OFFSET (x86
._TR
), // Offset32
610 SMM_CPU_OFFSET (x64
._TR
), // Offset64Lo
613 }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
618 SMM_CPU_OFFSET (x86
._DR7
), // Offset32
619 SMM_CPU_OFFSET (x64
._DR7
), // Offset64Lo
620 SMM_CPU_OFFSET (x64
._DR7
) + 4, // Offset64Hi
622 }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
627 SMM_CPU_OFFSET (x86
._DR6
), // Offset32
628 SMM_CPU_OFFSET (x64
._DR6
), // Offset64Lo
629 SMM_CPU_OFFSET (x64
._DR6
) + 4, // Offset64Hi
631 }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
637 SMM_CPU_OFFSET (x64
._R8
), // Offset64Lo
638 SMM_CPU_OFFSET (x64
._R8
) + 4, // Offset64Hi
640 }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
646 SMM_CPU_OFFSET (x64
._R9
), // Offset64Lo
647 SMM_CPU_OFFSET (x64
._R9
) + 4, // Offset64Hi
649 }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
655 SMM_CPU_OFFSET (x64
._R10
), // Offset64Lo
656 SMM_CPU_OFFSET (x64
._R10
) + 4, // Offset64Hi
658 }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
664 SMM_CPU_OFFSET (x64
._R11
), // Offset64Lo
665 SMM_CPU_OFFSET (x64
._R11
) + 4, // Offset64Hi
667 }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
673 SMM_CPU_OFFSET (x64
._R12
), // Offset64Lo
674 SMM_CPU_OFFSET (x64
._R12
) + 4, // Offset64Hi
676 }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
682 SMM_CPU_OFFSET (x64
._R13
), // Offset64Lo
683 SMM_CPU_OFFSET (x64
._R13
) + 4, // Offset64Hi
685 }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
691 SMM_CPU_OFFSET (x64
._R14
), // Offset64Lo
692 SMM_CPU_OFFSET (x64
._R14
) + 4, // Offset64Hi
694 }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
700 SMM_CPU_OFFSET (x64
._R15
), // Offset64Lo
701 SMM_CPU_OFFSET (x64
._R15
) + 4, // Offset64Hi
703 }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
708 SMM_CPU_OFFSET (x86
._EAX
), // Offset32
709 SMM_CPU_OFFSET (x64
._RAX
), // Offset64Lo
710 SMM_CPU_OFFSET (x64
._RAX
) + 4, // Offset64Hi
712 }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
717 SMM_CPU_OFFSET (x86
._EBX
), // Offset32
718 SMM_CPU_OFFSET (x64
._RBX
), // Offset64Lo
719 SMM_CPU_OFFSET (x64
._RBX
) + 4, // Offset64Hi
721 }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
726 SMM_CPU_OFFSET (x86
._ECX
), // Offset32
727 SMM_CPU_OFFSET (x64
._RCX
), // Offset64Lo
728 SMM_CPU_OFFSET (x64
._RCX
) + 4, // Offset64Hi
730 }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
735 SMM_CPU_OFFSET (x86
._EDX
), // Offset32
736 SMM_CPU_OFFSET (x64
._RDX
), // Offset64Lo
737 SMM_CPU_OFFSET (x64
._RDX
) + 4, // Offset64Hi
739 }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
744 SMM_CPU_OFFSET (x86
._ESP
), // Offset32
745 SMM_CPU_OFFSET (x64
._RSP
), // Offset64Lo
746 SMM_CPU_OFFSET (x64
._RSP
) + 4, // Offset64Hi
748 }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
753 SMM_CPU_OFFSET (x86
._EBP
), // Offset32
754 SMM_CPU_OFFSET (x64
._RBP
), // Offset64Lo
755 SMM_CPU_OFFSET (x64
._RBP
) + 4, // Offset64Hi
757 }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
762 SMM_CPU_OFFSET (x86
._ESI
), // Offset32
763 SMM_CPU_OFFSET (x64
._RSI
), // Offset64Lo
764 SMM_CPU_OFFSET (x64
._RSI
) + 4, // Offset64Hi
766 }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
771 SMM_CPU_OFFSET (x86
._EDI
), // Offset32
772 SMM_CPU_OFFSET (x64
._RDI
), // Offset64Lo
773 SMM_CPU_OFFSET (x64
._RDI
) + 4, // Offset64Hi
775 }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
780 SMM_CPU_OFFSET (x86
._EIP
), // Offset32
781 SMM_CPU_OFFSET (x64
._RIP
), // Offset64Lo
782 SMM_CPU_OFFSET (x64
._RIP
) + 4, // Offset64Hi
784 }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
789 SMM_CPU_OFFSET (x86
._EFLAGS
), // Offset32
790 SMM_CPU_OFFSET (x64
._RFLAGS
), // Offset64Lo
791 SMM_CPU_OFFSET (x64
._RFLAGS
) + 4, // Offset64Hi
793 }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
798 SMM_CPU_OFFSET (x86
._CR0
), // Offset32
799 SMM_CPU_OFFSET (x64
._CR0
), // Offset64Lo
800 SMM_CPU_OFFSET (x64
._CR0
) + 4, // Offset64Hi
802 }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
807 SMM_CPU_OFFSET (x86
._CR3
), // Offset32
808 SMM_CPU_OFFSET (x64
._CR3
), // Offset64Lo
809 SMM_CPU_OFFSET (x64
._CR3
) + 4, // Offset64Hi
811 }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
817 SMM_CPU_OFFSET (x64
._CR4
), // Offset64Lo
818 SMM_CPU_OFFSET (x64
._CR4
) + 4, // Offset64Hi
820 }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
824 // No support for I/O restart
828 Read information from the CPU save state.
830 @param Register Specifies the CPU register to read form the save state.
832 @retval 0 Register is not valid
833 @retval >0 Index into mSmmCpuWidthOffset[] associated with Register
839 IN EFI_SMM_SAVE_STATE_REGISTER Register
845 for (Index
= 0, Offset
= SMM_SAVE_STATE_REGISTER_FIRST_INDEX
;
846 mSmmCpuRegisterRanges
[Index
].Length
!= 0;
848 if (Register
>= mSmmCpuRegisterRanges
[Index
].Start
&&
849 Register
<= mSmmCpuRegisterRanges
[Index
].End
) {
850 return Register
- mSmmCpuRegisterRanges
[Index
].Start
+ Offset
;
852 Offset
+= mSmmCpuRegisterRanges
[Index
].Length
;
858 Read a CPU Save State register on the target processor.
860 This function abstracts the differences that whether the CPU Save State
861 register is in the IA32 CPU Save State Map or X64 CPU Save State Map.
863 This function supports reading a CPU Save State register in SMBase relocation
866 @param[in] CpuIndex Specifies the zero-based index of the CPU save
868 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
869 @param[in] Width The number of bytes to read from the CPU save
871 @param[out] Buffer Upon return, this holds the CPU register value
872 read from the save state.
874 @retval EFI_SUCCESS The register was read from Save State.
875 @retval EFI_NOT_FOUND The register is not defined for the Save State
877 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
882 ReadSaveStateRegisterByIndex (
884 IN UINTN RegisterIndex
,
889 QEMU_SMRAM_SAVE_STATE_MAP
*CpuSaveState
;
891 CpuSaveState
= (QEMU_SMRAM_SAVE_STATE_MAP
*)gSmst
->CpuSaveState
[CpuIndex
];
893 if ((CpuSaveState
->x86
.SMMRevId
& 0xFFFF) == 0) {
895 // If 32-bit mode width is zero, then the specified register can not be
898 if (mSmmCpuWidthOffset
[RegisterIndex
].Width32
== 0) {
899 return EFI_NOT_FOUND
;
903 // If Width is bigger than the 32-bit mode width, then the specified
904 // register can not be accessed
906 if (Width
> mSmmCpuWidthOffset
[RegisterIndex
].Width32
) {
907 return EFI_INVALID_PARAMETER
;
911 // Write return buffer
913 ASSERT(CpuSaveState
!= NULL
);
916 (UINT8
*)CpuSaveState
+ mSmmCpuWidthOffset
[RegisterIndex
].Offset32
,
921 // If 64-bit mode width is zero, then the specified register can not be
924 if (mSmmCpuWidthOffset
[RegisterIndex
].Width64
== 0) {
925 return EFI_NOT_FOUND
;
929 // If Width is bigger than the 64-bit mode width, then the specified
930 // register can not be accessed
932 if (Width
> mSmmCpuWidthOffset
[RegisterIndex
].Width64
) {
933 return EFI_INVALID_PARAMETER
;
937 // Write lower 32-bits of return buffer
941 (UINT8
*)CpuSaveState
+ mSmmCpuWidthOffset
[RegisterIndex
].Offset64Lo
,
946 // Write upper 32-bits of return buffer
950 (UINT8
*)CpuSaveState
+ mSmmCpuWidthOffset
[RegisterIndex
].Offset64Hi
,
959 Read an SMM Save State register on the target processor. If this function
960 returns EFI_UNSUPPORTED, then the caller is responsible for reading the
961 SMM Save Sate register.
963 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
964 value must be between 0 and the NumberOfCpus field in
965 the System Management System Table (SMST).
966 @param[in] Register The SMM Save State register to read.
967 @param[in] Width The number of bytes to read from the CPU save state.
968 @param[out] Buffer Upon return, this holds the CPU register value read
971 @retval EFI_SUCCESS The register was read from Save State.
972 @retval EFI_INVALID_PARAMTER Buffer is NULL.
973 @retval EFI_UNSUPPORTED This function does not support reading
978 SmmCpuFeaturesReadSaveStateRegister (
980 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
986 QEMU_SMRAM_SAVE_STATE_MAP
*CpuSaveState
;
989 // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
991 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_LMA
) {
993 // Only byte access is supported for this register
996 return EFI_INVALID_PARAMETER
;
999 CpuSaveState
= (QEMU_SMRAM_SAVE_STATE_MAP
*)gSmst
->CpuSaveState
[CpuIndex
];
1004 if ((CpuSaveState
->x86
.SMMRevId
& 0xFFFF) == 0) {
1005 *(UINT8
*)Buffer
= 32;
1007 *(UINT8
*)Buffer
= 64;
1014 // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
1016 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_IO
) {
1017 return EFI_NOT_FOUND
;
1021 // Convert Register to a register lookup table index. Let
1022 // PiSmmCpuDxeSmm implement other special registers (currently
1023 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
1025 RegisterIndex
= GetRegisterIndex (Register
);
1026 if (RegisterIndex
== 0) {
1027 return (Register
< EFI_SMM_SAVE_STATE_REGISTER_IO
?
1032 return ReadSaveStateRegisterByIndex (CpuIndex
, RegisterIndex
, Width
, Buffer
);
1036 Writes an SMM Save State register on the target processor. If this function
1037 returns EFI_UNSUPPORTED, then the caller is responsible for writing the
1038 SMM Save Sate register.
1040 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
1041 value must be between 0 and the NumberOfCpus field in
1042 the System Management System Table (SMST).
1043 @param[in] Register The SMM Save State register to write.
1044 @param[in] Width The number of bytes to write to the CPU save state.
1045 @param[in] Buffer Upon entry, this holds the new CPU register value.
1047 @retval EFI_SUCCESS The register was written to Save State.
1048 @retval EFI_INVALID_PARAMTER Buffer is NULL.
1049 @retval EFI_UNSUPPORTED This function does not support writing
1054 SmmCpuFeaturesWriteSaveStateRegister (
1056 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
1058 IN CONST VOID
*Buffer
1061 UINTN RegisterIndex
;
1062 QEMU_SMRAM_SAVE_STATE_MAP
*CpuSaveState
;
1065 // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
1067 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_LMA
) {
1072 // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
1074 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_IO
) {
1075 return EFI_NOT_FOUND
;
1079 // Convert Register to a register lookup table index. Let
1080 // PiSmmCpuDxeSmm implement other special registers (currently
1081 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
1083 RegisterIndex
= GetRegisterIndex (Register
);
1084 if (RegisterIndex
== 0) {
1085 return (Register
< EFI_SMM_SAVE_STATE_REGISTER_IO
?
1090 CpuSaveState
= (QEMU_SMRAM_SAVE_STATE_MAP
*)gSmst
->CpuSaveState
[CpuIndex
];
1093 // Do not write non-writable SaveState, because it will cause exception.
1095 if (!mSmmCpuWidthOffset
[RegisterIndex
].Writeable
) {
1096 return EFI_UNSUPPORTED
;
1102 if ((CpuSaveState
->x86
.SMMRevId
& 0xFFFF) == 0) {
1104 // If 32-bit mode width is zero, then the specified register can not be
1107 if (mSmmCpuWidthOffset
[RegisterIndex
].Width32
== 0) {
1108 return EFI_NOT_FOUND
;
1112 // If Width is bigger than the 32-bit mode width, then the specified
1113 // register can not be accessed
1115 if (Width
> mSmmCpuWidthOffset
[RegisterIndex
].Width32
) {
1116 return EFI_INVALID_PARAMETER
;
1119 // Write SMM State register
1121 ASSERT (CpuSaveState
!= NULL
);
1123 (UINT8
*)CpuSaveState
+ mSmmCpuWidthOffset
[RegisterIndex
].Offset32
,
1129 // If 64-bit mode width is zero, then the specified register can not be
1132 if (mSmmCpuWidthOffset
[RegisterIndex
].Width64
== 0) {
1133 return EFI_NOT_FOUND
;
1137 // If Width is bigger than the 64-bit mode width, then the specified
1138 // register can not be accessed
1140 if (Width
> mSmmCpuWidthOffset
[RegisterIndex
].Width64
) {
1141 return EFI_INVALID_PARAMETER
;
1145 // Write lower 32-bits of SMM State register
1148 (UINT8
*)CpuSaveState
+ mSmmCpuWidthOffset
[RegisterIndex
].Offset64Lo
,
1154 // Write upper 32-bits of SMM State register
1157 (UINT8
*)CpuSaveState
+ mSmmCpuWidthOffset
[RegisterIndex
].Offset64Hi
,
1158 (UINT8
*)Buffer
+ 4,
1167 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
1168 notification is completely processed.
1172 SmmCpuFeaturesCompleteSmmReadyToLock (
1179 This API provides a method for a CPU to allocate a specific region for
1180 storing page tables.
1182 This API can be called more once to allocate memory for page tables.
1184 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns
1185 a pointer to the allocated buffer. The buffer returned is aligned on a 4KB
1186 boundary. If Pages is 0, then NULL is returned. If there is not enough
1187 memory remaining to satisfy the request, then NULL is returned.
1189 This function can also return NULL if there is no preference on where the
1190 page tables are allocated in SMRAM.
1192 @param Pages The number of 4 KB pages to allocate.
1194 @return A pointer to the allocated buffer for page tables.
1195 @retval NULL Fail to allocate a specific region for storing page tables,
1196 Or there is no preference on where the page tables are
1202 SmmCpuFeaturesAllocatePageTableMemory (