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1 /** @file
2 The CPU specific programming for PiSmmCpuDxeSmm module.
3
4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include <PiSmm.h>
16 #include <Library/SmmCpuFeaturesLib.h>
17 #include <Library/BaseLib.h>
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/PcdLib.h>
20 #include <Library/MemoryAllocationLib.h>
21 #include <Library/SmmServicesTableLib.h>
22 #include <Library/DebugLib.h>
23 #include <Register/SmramSaveStateMap.h>
24
25 //
26 // EFER register LMA bit
27 //
28 #define LMA BIT10
29
30 /**
31 The constructor function
32
33 @param[in] ImageHandle The firmware allocated handle for the EFI image.
34 @param[in] SystemTable A pointer to the EFI System Table.
35
36 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
37
38 **/
39 EFI_STATUS
40 EFIAPI
41 SmmCpuFeaturesLibConstructor (
42 IN EFI_HANDLE ImageHandle,
43 IN EFI_SYSTEM_TABLE *SystemTable
44 )
45 {
46 //
47 // No need to program SMRRs on our virtual platform.
48 //
49 return EFI_SUCCESS;
50 }
51
52 /**
53 Called during the very first SMI into System Management Mode to initialize
54 CPU features, including SMBASE, for the currently executing CPU. Since this
55 is the first SMI, the SMRAM Save State Map is at the default address of
56 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
57 CPU is specified by CpuIndex and CpuIndex can be used to access information
58 about the currently executing CPU in the ProcessorInfo array and the
59 HotPlugCpuData data structure.
60
61 @param[in] CpuIndex The index of the CPU to initialize. The value
62 must be between 0 and the NumberOfCpus field in
63 the System Management System Table (SMST).
64 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
65 was elected as monarch during System Management
66 Mode initialization.
67 FALSE if the CpuIndex is not the index of the CPU
68 that was elected as monarch during System
69 Management Mode initialization.
70 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
71 structures. ProcessorInfo[CpuIndex] contains the
72 information for the currently executing CPU.
73 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
74 contains the ApidId and SmBase arrays.
75 **/
76 VOID
77 EFIAPI
78 SmmCpuFeaturesInitializeProcessor (
79 IN UINTN CpuIndex,
80 IN BOOLEAN IsMonarch,
81 IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,
82 IN CPU_HOT_PLUG_DATA *CpuHotPlugData
83 )
84 {
85 SMRAM_SAVE_STATE_MAP *CpuState;
86
87 //
88 // Configure SMBASE.
89 //
90 CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
91 CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
92
93 //
94 // No need to program SMRRs on our virtual platform.
95 //
96 }
97
98 /**
99 This function updates the SMRAM save state on the currently executing CPU
100 to resume execution at a specific address after an RSM instruction. This
101 function must evaluate the SMRAM save state to determine the execution mode
102 the RSM instruction resumes and update the resume execution address with
103 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
104 flag in the SMRAM save state must always be cleared. This function returns
105 the value of the instruction pointer from the SMRAM save state that was
106 replaced. If this function returns 0, then the SMRAM save state was not
107 modified.
108
109 This function is called during the very first SMI on each CPU after
110 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
111 to signal that the SMBASE of each CPU has been updated before the default
112 SMBASE address is used for the first SMI to the next CPU.
113
114 @param[in] CpuIndex The index of the CPU to hook. The value
115 must be between 0 and the NumberOfCpus
116 field in the System Management System Table
117 (SMST).
118 @param[in] CpuState Pointer to SMRAM Save State Map for the
119 currently executing CPU.
120 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
121 32-bit execution mode from 64-bit SMM.
122 @param[in] NewInstructionPointer Instruction pointer to use if resuming to
123 same execution mode as SMM.
124
125 @retval 0 This function did modify the SMRAM save state.
126 @retval > 0 The original instruction pointer value from the SMRAM save state
127 before it was replaced.
128 **/
129 UINT64
130 EFIAPI
131 SmmCpuFeaturesHookReturnFromSmm (
132 IN UINTN CpuIndex,
133 IN SMRAM_SAVE_STATE_MAP *CpuState,
134 IN UINT64 NewInstructionPointer32,
135 IN UINT64 NewInstructionPointer
136 )
137 {
138 UINT64 OriginalInstructionPointer;
139 SMRAM_SAVE_STATE_MAP *CpuSaveState = (SMRAM_SAVE_STATE_MAP *)CpuState;
140
141 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
142 OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;
143 CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;
144 //
145 // Clear the auto HALT restart flag so the RSM instruction returns
146 // program control to the instruction following the HLT instruction.
147 //
148 if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != 0) {
149 CpuSaveState->x86.AutoHALTRestart &= ~BIT0;
150 }
151 } else {
152 OriginalInstructionPointer = CpuSaveState->x64._RIP;
153 if ((CpuSaveState->x64.IA32_EFER & LMA) == 0) {
154 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer32;
155 } else {
156 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer;
157 }
158 //
159 // Clear the auto HALT restart flag so the RSM instruction returns
160 // program control to the instruction following the HLT instruction.
161 //
162 if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != 0) {
163 CpuSaveState->x64.AutoHALTRestart &= ~BIT0;
164 }
165 }
166 return OriginalInstructionPointer;
167 }
168
169 /**
170 Hook point in normal execution mode that allows the one CPU that was elected
171 as monarch during System Management Mode initialization to perform additional
172 initialization actions immediately after all of the CPUs have processed their
173 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
174 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
175 **/
176 VOID
177 EFIAPI
178 SmmCpuFeaturesSmmRelocationComplete (
179 VOID
180 )
181 {
182 }
183
184 /**
185 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
186 returned, then a custom SMI handler is not provided by this library,
187 and the default SMI handler must be used.
188
189 @retval 0 Use the default SMI handler.
190 @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
191 The caller is required to allocate enough SMRAM for each CPU to
192 support the size of the custom SMI handler.
193 **/
194 UINTN
195 EFIAPI
196 SmmCpuFeaturesGetSmiHandlerSize (
197 VOID
198 )
199 {
200 return 0;
201 }
202
203 /**
204 Install a custom SMI handler for the CPU specified by CpuIndex. This function
205 is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
206 than zero and is called by the CPU that was elected as monarch during System
207 Management Mode initialization.
208
209 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
210 The value must be between 0 and the NumberOfCpus field
211 in the System Management System Table (SMST).
212 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
213 @param[in] SmiStack The stack to use when an SMI is processed by the
214 the CPU specified by CpuIndex.
215 @param[in] StackSize The size, in bytes, if the stack used when an SMI is
216 processed by the CPU specified by CpuIndex.
217 @param[in] GdtBase The base address of the GDT to use when an SMI is
218 processed by the CPU specified by CpuIndex.
219 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
220 processed by the CPU specified by CpuIndex.
221 @param[in] IdtBase The base address of the IDT to use when an SMI is
222 processed by the CPU specified by CpuIndex.
223 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
224 processed by the CPU specified by CpuIndex.
225 @param[in] Cr3 The base address of the page tables to use when an SMI
226 is processed by the CPU specified by CpuIndex.
227 **/
228 VOID
229 EFIAPI
230 SmmCpuFeaturesInstallSmiHandler (
231 IN UINTN CpuIndex,
232 IN UINT32 SmBase,
233 IN VOID *SmiStack,
234 IN UINTN StackSize,
235 IN UINTN GdtBase,
236 IN UINTN GdtSize,
237 IN UINTN IdtBase,
238 IN UINTN IdtSize,
239 IN UINT32 Cr3
240 )
241 {
242 }
243
244 /**
245 Determines if MTRR registers must be configured to set SMRAM cache-ability
246 when executing in System Management Mode.
247
248 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
249 @retval FALSE MTRR registers do not need to be configured to set SMRAM
250 cache-ability.
251 **/
252 BOOLEAN
253 EFIAPI
254 SmmCpuFeaturesNeedConfigureMtrrs (
255 VOID
256 )
257 {
258 return FALSE;
259 }
260
261 /**
262 Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
263 returns TRUE.
264 **/
265 VOID
266 EFIAPI
267 SmmCpuFeaturesDisableSmrr (
268 VOID
269 )
270 {
271 //
272 // No SMRR support, nothing to do
273 //
274 }
275
276 /**
277 Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
278 returns TRUE.
279 **/
280 VOID
281 EFIAPI
282 SmmCpuFeaturesReenableSmrr (
283 VOID
284 )
285 {
286 //
287 // No SMRR support, nothing to do
288 //
289 }
290
291 /**
292 Processor specific hook point each time a CPU enters System Management Mode.
293
294 @param[in] CpuIndex The index of the CPU that has entered SMM. The value
295 must be between 0 and the NumberOfCpus field in the
296 System Management System Table (SMST).
297 **/
298 VOID
299 EFIAPI
300 SmmCpuFeaturesRendezvousEntry (
301 IN UINTN CpuIndex
302 )
303 {
304 //
305 // No SMRR support, nothing to do
306 //
307 }
308
309 /**
310 Processor specific hook point each time a CPU exits System Management Mode.
311
312 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must
313 be between 0 and the NumberOfCpus field in the System
314 Management System Table (SMST).
315 **/
316 VOID
317 EFIAPI
318 SmmCpuFeaturesRendezvousExit (
319 IN UINTN CpuIndex
320 )
321 {
322 }
323
324 /**
325 Check to see if an SMM register is supported by a specified CPU.
326
327 @param[in] CpuIndex The index of the CPU to check for SMM register support.
328 The value must be between 0 and the NumberOfCpus field
329 in the System Management System Table (SMST).
330 @param[in] RegName Identifies the SMM register to check for support.
331
332 @retval TRUE The SMM register specified by RegName is supported by the CPU
333 specified by CpuIndex.
334 @retval FALSE The SMM register specified by RegName is not supported by the
335 CPU specified by CpuIndex.
336 **/
337 BOOLEAN
338 EFIAPI
339 SmmCpuFeaturesIsSmmRegisterSupported (
340 IN UINTN CpuIndex,
341 IN SMM_REG_NAME RegName
342 )
343 {
344 ASSERT (RegName == SmmRegFeatureControl);
345 return FALSE;
346 }
347
348 /**
349 Returns the current value of the SMM register for the specified CPU.
350 If the SMM register is not supported, then 0 is returned.
351
352 @param[in] CpuIndex The index of the CPU to read the SMM register. The
353 value must be between 0 and the NumberOfCpus field in
354 the System Management System Table (SMST).
355 @param[in] RegName Identifies the SMM register to read.
356
357 @return The value of the SMM register specified by RegName from the CPU
358 specified by CpuIndex.
359 **/
360 UINT64
361 EFIAPI
362 SmmCpuFeaturesGetSmmRegister (
363 IN UINTN CpuIndex,
364 IN SMM_REG_NAME RegName
365 )
366 {
367 //
368 // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.
369 // The last of these should actually be SmmRegSmmDisable, so we can just
370 // return FALSE.
371 //
372 return 0;
373 }
374
375 /**
376 Sets the value of an SMM register on a specified CPU.
377 If the SMM register is not supported, then no action is performed.
378
379 @param[in] CpuIndex The index of the CPU to write the SMM register. The
380 value must be between 0 and the NumberOfCpus field in
381 the System Management System Table (SMST).
382 @param[in] RegName Identifies the SMM register to write.
383 registers are read-only.
384 @param[in] Value The value to write to the SMM register.
385 **/
386 VOID
387 EFIAPI
388 SmmCpuFeaturesSetSmmRegister (
389 IN UINTN CpuIndex,
390 IN SMM_REG_NAME RegName,
391 IN UINT64 Value
392 )
393 {
394 ASSERT (FALSE);
395 }
396
397 ///
398 /// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
399 ///
400 #define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)
401
402 ///
403 /// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE
404 ///
405 #define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
406
407 ///
408 /// Structure used to describe a range of registers
409 ///
410 typedef struct {
411 EFI_SMM_SAVE_STATE_REGISTER Start;
412 EFI_SMM_SAVE_STATE_REGISTER End;
413 UINTN Length;
414 } CPU_SMM_SAVE_STATE_REGISTER_RANGE;
415
416 ///
417 /// Structure used to build a lookup table to retrieve the widths and offsets
418 /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
419 ///
420
421 #define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1
422
423 typedef struct {
424 UINT8 Width32;
425 UINT8 Width64;
426 UINT16 Offset32;
427 UINT16 Offset64Lo;
428 UINT16 Offset64Hi;
429 BOOLEAN Writeable;
430 } CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
431
432 ///
433 /// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
434 /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
435 ///
436 static CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
437 SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),
438 SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP),
439 SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4),
440 { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }
441 };
442
443 ///
444 /// Lookup table used to retrieve the widths and offsets associated with each
445 /// supported EFI_SMM_SAVE_STATE_REGISTER value
446 ///
447 static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
448 {0, 0, 0, 0, 0, FALSE}, // Reserved
449
450 //
451 // CPU Save State registers defined in PI SMM CPU Protocol.
452 //
453 {0, 8, 0 , SMM_CPU_OFFSET (x64.GdtBaseLoDword) , SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
454 {0, 8, 0 , SMM_CPU_OFFSET (x64.IdtBaseLoDword) , SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
455 {0, 8, 0 , SMM_CPU_OFFSET (x64.LdtBaseLoDword) , SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
456 {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
457 {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
458 {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
459 {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
460
461 {4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
462 {4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
463 {4, 4, SMM_CPU_OFFSET (x86._SS) , SMM_CPU_OFFSET (x64._SS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
464 {4, 4, SMM_CPU_OFFSET (x86._DS) , SMM_CPU_OFFSET (x64._DS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
465 {4, 4, SMM_CPU_OFFSET (x86._FS) , SMM_CPU_OFFSET (x64._FS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
466 {4, 4, SMM_CPU_OFFSET (x86._GS) , SMM_CPU_OFFSET (x64._GS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
467 {0, 4, 0 , SMM_CPU_OFFSET (x64._LDTR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
468 {4, 4, SMM_CPU_OFFSET (x86._TR) , SMM_CPU_OFFSET (x64._TR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
469 {4, 8, SMM_CPU_OFFSET (x86._DR7) , SMM_CPU_OFFSET (x64._DR7) , SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
470 {4, 8, SMM_CPU_OFFSET (x86._DR6) , SMM_CPU_OFFSET (x64._DR6) , SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
471 {0, 8, 0 , SMM_CPU_OFFSET (x64._R8) , SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
472 {0, 8, 0 , SMM_CPU_OFFSET (x64._R9) , SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
473 {0, 8, 0 , SMM_CPU_OFFSET (x64._R10) , SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
474 {0, 8, 0 , SMM_CPU_OFFSET (x64._R11) , SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
475 {0, 8, 0 , SMM_CPU_OFFSET (x64._R12) , SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
476 {0, 8, 0 , SMM_CPU_OFFSET (x64._R13) , SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
477 {0, 8, 0 , SMM_CPU_OFFSET (x64._R14) , SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
478 {0, 8, 0 , SMM_CPU_OFFSET (x64._R15) , SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
479 {4, 8, SMM_CPU_OFFSET (x86._EAX) , SMM_CPU_OFFSET (x64._RAX) , SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
480 {4, 8, SMM_CPU_OFFSET (x86._EBX) , SMM_CPU_OFFSET (x64._RBX) , SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
481 {4, 8, SMM_CPU_OFFSET (x86._ECX) , SMM_CPU_OFFSET (x64._RCX) , SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
482 {4, 8, SMM_CPU_OFFSET (x86._EDX) , SMM_CPU_OFFSET (x64._RDX) , SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
483 {4, 8, SMM_CPU_OFFSET (x86._ESP) , SMM_CPU_OFFSET (x64._RSP) , SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
484 {4, 8, SMM_CPU_OFFSET (x86._EBP) , SMM_CPU_OFFSET (x64._RBP) , SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
485 {4, 8, SMM_CPU_OFFSET (x86._ESI) , SMM_CPU_OFFSET (x64._RSI) , SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
486 {4, 8, SMM_CPU_OFFSET (x86._EDI) , SMM_CPU_OFFSET (x64._RDI) , SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
487 {4, 8, SMM_CPU_OFFSET (x86._EIP) , SMM_CPU_OFFSET (x64._RIP) , SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
488
489 {4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
490 {4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
491 {4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
492 {0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
493 };
494
495 //
496 // No support for I/O restart
497 //
498
499 /**
500 Read information from the CPU save state.
501
502 @param Register Specifies the CPU register to read form the save state.
503
504 @retval 0 Register is not valid
505 @retval >0 Index into mSmmCpuWidthOffset[] associated with Register
506
507 **/
508 static UINTN
509 GetRegisterIndex (
510 IN EFI_SMM_SAVE_STATE_REGISTER Register
511 )
512 {
513 UINTN Index;
514 UINTN Offset;
515
516 for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {
517 if (Register >= mSmmCpuRegisterRanges[Index].Start && Register <= mSmmCpuRegisterRanges[Index].End) {
518 return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
519 }
520 Offset += mSmmCpuRegisterRanges[Index].Length;
521 }
522 return 0;
523 }
524
525 /**
526 Read a CPU Save State register on the target processor.
527
528 This function abstracts the differences that whether the CPU Save State register is in the
529 IA32 CPU Save State Map or X64 CPU Save State Map.
530
531 This function supports reading a CPU Save State register in SMBase relocation handler.
532
533 @param[in] CpuIndex Specifies the zero-based index of the CPU save state.
534 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
535 @param[in] Width The number of bytes to read from the CPU save state.
536 @param[out] Buffer Upon return, this holds the CPU register value read from the save state.
537
538 @retval EFI_SUCCESS The register was read from Save State.
539 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
540 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
541
542 **/
543 static EFI_STATUS
544 ReadSaveStateRegisterByIndex (
545 IN UINTN CpuIndex,
546 IN UINTN RegisterIndex,
547 IN UINTN Width,
548 OUT VOID *Buffer
549 )
550 {
551 SMRAM_SAVE_STATE_MAP *CpuSaveState;
552
553 CpuSaveState = gSmst->CpuSaveState[CpuIndex];
554
555 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
556 //
557 // If 32-bit mode width is zero, then the specified register can not be accessed
558 //
559 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
560 return EFI_NOT_FOUND;
561 }
562
563 //
564 // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
565 //
566 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
567 return EFI_INVALID_PARAMETER;
568 }
569
570 //
571 // Write return buffer
572 //
573 ASSERT(CpuSaveState != NULL);
574 CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);
575 } else {
576 //
577 // If 64-bit mode width is zero, then the specified register can not be accessed
578 //
579 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
580 return EFI_NOT_FOUND;
581 }
582
583 //
584 // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
585 //
586 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
587 return EFI_INVALID_PARAMETER;
588 }
589
590 //
591 // Write lower 32-bits of return buffer
592 //
593 CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width));
594 if (Width >= 4) {
595 //
596 // Write upper 32-bits of return buffer
597 //
598 CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
599 }
600 }
601 return EFI_SUCCESS;
602 }
603
604 /**
605 Read an SMM Save State register on the target processor. If this function
606 returns EFI_UNSUPPORTED, then the caller is responsible for reading the
607 SMM Save Sate register.
608
609 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
610 value must be between 0 and the NumberOfCpus field in
611 the System Management System Table (SMST).
612 @param[in] Register The SMM Save State register to read.
613 @param[in] Width The number of bytes to read from the CPU save state.
614 @param[out] Buffer Upon return, this holds the CPU register value read
615 from the save state.
616
617 @retval EFI_SUCCESS The register was read from Save State.
618 @retval EFI_INVALID_PARAMTER Buffer is NULL.
619 @retval EFI_UNSUPPORTED This function does not support reading Register.
620
621 **/
622 EFI_STATUS
623 EFIAPI
624 SmmCpuFeaturesReadSaveStateRegister (
625 IN UINTN CpuIndex,
626 IN EFI_SMM_SAVE_STATE_REGISTER Register,
627 IN UINTN Width,
628 OUT VOID *Buffer
629 )
630 {
631 UINTN RegisterIndex;
632 SMRAM_SAVE_STATE_MAP *CpuSaveState;
633
634 //
635 // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
636 //
637 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
638 //
639 // Only byte access is supported for this register
640 //
641 if (Width != 1) {
642 return EFI_INVALID_PARAMETER;
643 }
644
645 CpuSaveState = gSmst->CpuSaveState[CpuIndex];
646
647 //
648 // Check CPU mode
649 //
650 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
651 *(UINT8 *)Buffer = 32;
652 } else {
653 *(UINT8 *)Buffer = 64;
654 }
655
656 return EFI_SUCCESS;
657 }
658
659 //
660 // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
661 //
662 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
663 return EFI_NOT_FOUND;
664 }
665
666 //
667 // Convert Register to a register lookup table index. Let
668 // PiSmmCpuDxeSmm implement other special registers (currently
669 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
670 //
671 RegisterIndex = GetRegisterIndex (Register);
672 if (RegisterIndex == 0) {
673 return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED;
674 }
675
676 return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);
677 }
678
679 /**
680 Writes an SMM Save State register on the target processor. If this function
681 returns EFI_UNSUPPORTED, then the caller is responsible for writing the
682 SMM Save Sate register.
683
684 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
685 value must be between 0 and the NumberOfCpus field in
686 the System Management System Table (SMST).
687 @param[in] Register The SMM Save State register to write.
688 @param[in] Width The number of bytes to write to the CPU save state.
689 @param[in] Buffer Upon entry, this holds the new CPU register value.
690
691 @retval EFI_SUCCESS The register was written to Save State.
692 @retval EFI_INVALID_PARAMTER Buffer is NULL.
693 @retval EFI_UNSUPPORTED This function does not support writing Register.
694 **/
695 EFI_STATUS
696 EFIAPI
697 SmmCpuFeaturesWriteSaveStateRegister (
698 IN UINTN CpuIndex,
699 IN EFI_SMM_SAVE_STATE_REGISTER Register,
700 IN UINTN Width,
701 IN CONST VOID *Buffer
702 )
703 {
704 UINTN RegisterIndex;
705 SMRAM_SAVE_STATE_MAP *CpuSaveState;
706
707 //
708 // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
709 //
710 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
711 return EFI_SUCCESS;
712 }
713
714 //
715 // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
716 //
717 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
718 return EFI_NOT_FOUND;
719 }
720
721 //
722 // Convert Register to a register lookup table index. Let
723 // PiSmmCpuDxeSmm implement other special registers (currently
724 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
725 //
726 RegisterIndex = GetRegisterIndex (Register);
727 if (RegisterIndex == 0) {
728 return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED;
729 }
730
731 CpuSaveState = gSmst->CpuSaveState[CpuIndex];
732
733 //
734 // Do not write non-writable SaveState, because it will cause exception.
735 //
736 if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
737 return EFI_UNSUPPORTED;
738 }
739
740 //
741 // Check CPU mode
742 //
743 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
744 //
745 // If 32-bit mode width is zero, then the specified register can not be accessed
746 //
747 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
748 return EFI_NOT_FOUND;
749 }
750
751 //
752 // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
753 //
754 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
755 return EFI_INVALID_PARAMETER;
756 }
757 //
758 // Write SMM State register
759 //
760 ASSERT (CpuSaveState != NULL);
761 CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
762 } else {
763 //
764 // If 64-bit mode width is zero, then the specified register can not be accessed
765 //
766 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
767 return EFI_NOT_FOUND;
768 }
769
770 //
771 // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
772 //
773 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
774 return EFI_INVALID_PARAMETER;
775 }
776
777 //
778 // Write lower 32-bits of SMM State register
779 //
780 CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
781 if (Width >= 4) {
782 //
783 // Write upper 32-bits of SMM State register
784 //
785 CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
786 }
787 }
788 return EFI_SUCCESS;
789 }
790
791 /**
792 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
793 notification is completely processed.
794 **/
795 VOID
796 EFIAPI
797 SmmCpuFeaturesCompleteSmmReadyToLock (
798 VOID
799 )
800 {
801 }
802
803 /**
804 This API provides a method for a CPU to allocate a specific region for storing page tables.
805
806 This API can be called more once to allocate memory for page tables.
807
808 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
809 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
810 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
811 returned.
812
813 This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.
814
815 @param Pages The number of 4 KB pages to allocate.
816
817 @return A pointer to the allocated buffer for page tables.
818 @retval NULL Fail to allocate a specific region for storing page tables,
819 Or there is no preference on where the page tables are allocated in SMRAM.
820
821 **/
822 VOID *
823 EFIAPI
824 SmmCpuFeaturesAllocatePageTableMemory (
825 IN UINTN Pages
826 )
827 {
828 return NULL;
829 }
830
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