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OvmfPkg: introduce PciCapPciSegmentLib
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1 ## @file
2 # EFI/Framework Open Virtual Machine Firmware (OVMF) platform
3 #
4 # Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
5 #
6 # This program and the accompanying materials
7 # are licensed and made available under the terms and conditions of the BSD License
8 # which accompanies this distribution. The full text of the license may be found at
9 # http://opensource.org/licenses/bsd-license.php
10 #
11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 #
14 ##
15
16 [Defines]
17 DEC_SPECIFICATION = 0x00010005
18 PACKAGE_NAME = OvmfPkg
19 PACKAGE_GUID = 2daf5f34-50e5-4b9d-b8e3-5562334d87e5
20 PACKAGE_VERSION = 0.1
21
22 [Includes]
23 Include
24
25 [LibraryClasses]
26 ## @libraryclass Loads and boots a Linux kernel image
27 #
28 LoadLinuxLib|Include/Library/LoadLinuxLib.h
29
30 ## @libraryclass Save and restore variables using a file
31 #
32 NvVarsFileLib|Include/Library/NvVarsFileLib.h
33
34 ## @libraryclass Provides services to work with PCI capabilities in PCI
35 # config space.
36 PciCapLib|Include/Library/PciCapLib.h
37
38 ## @libraryclass Layered on top of PciCapLib, allows clients to plug a
39 # PciSegmentLib backend into PciCapLib, for config space
40 # access.
41 PciCapPciSegmentLib|Include/Library/PciCapPciSegmentLib.h
42
43 ## @libraryclass Access QEMU's firmware configuration interface
44 #
45 QemuFwCfgLib|Include/Library/QemuFwCfgLib.h
46
47 ## @libraryclass S3 support for QEMU fw_cfg
48 #
49 QemuFwCfgS3Lib|Include/Library/QemuFwCfgS3Lib.h
50
51 ## @libraryclass Rewrite the BootOrder NvVar based on QEMU's "bootorder"
52 # fw_cfg file.
53 #
54 QemuBootOrderLib|Include/Library/QemuBootOrderLib.h
55
56 ## @libraryclass Serialize (and deserialize) variables
57 #
58 SerializeVariablesLib|Include/Library/SerializeVariablesLib.h
59
60 ## @libraryclass Invoke Xen hypercalls
61 #
62 XenHypercallLib|Include/Library/XenHypercallLib.h
63
64 ## @libraryclass Manage XenBus device path and I/O handles
65 #
66 XenIoMmioLib|Include/Library/XenIoMmioLib.h
67
68 [Guids]
69 gUefiOvmfPkgTokenSpaceGuid = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}
70 gEfiXenInfoGuid = {0xd3b46f3b, 0xd441, 0x1244, {0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}}
71 gOvmfPlatformConfigGuid = {0x7235c51c, 0x0c80, 0x4cab, {0x87, 0xac, 0x3b, 0x08, 0x4a, 0x63, 0x04, 0xb1}}
72 gVirtioMmioTransportGuid = {0x837dca9e, 0xe874, 0x4d82, {0xb2, 0x9a, 0x23, 0xfe, 0x0e, 0x23, 0xd1, 0xe2}}
73 gXenBusRootDeviceGuid = {0xa732241f, 0x383d, 0x4d9c, {0x8a, 0xe1, 0x8e, 0x09, 0x83, 0x75, 0x89, 0xd7}}
74 gRootBridgesConnectedEventGroupGuid = {0x24a2d66f, 0xeedd, 0x4086, {0x90, 0x42, 0xf2, 0x6e, 0x47, 0x97, 0xee, 0x69}}
75
76 [Protocols]
77 gVirtioDeviceProtocolGuid = {0xfa920010, 0x6785, 0x4941, {0xb6, 0xec, 0x49, 0x8c, 0x57, 0x9f, 0x16, 0x0a}}
78 gXenBusProtocolGuid = {0x3d3ca290, 0xb9a5, 0x11e3, {0xb7, 0x5d, 0xb8, 0xac, 0x6f, 0x7d, 0x65, 0xe6}}
79 gXenIoProtocolGuid = {0x6efac84f, 0x0ab0, 0x4747, {0x81, 0xbe, 0x85, 0x55, 0x62, 0x59, 0x04, 0x49}}
80 gIoMmuAbsentProtocolGuid = {0xf8775d50, 0x8abd, 0x4adf, {0x92, 0xac, 0x85, 0x3e, 0x51, 0xf6, 0xc8, 0xdc}}
81
82 [PcdsFixedAtBuild]
83 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|0x0|UINT32|0
84 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize|0x0|UINT32|1
85 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|0x0|UINT32|0x15
86 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize|0x0|UINT32|0x16
87
88 ## This flag is used to control the destination port for PlatformDebugLibIoPort
89 gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort|0x402|UINT16|4
90
91 ## When VirtioScsiDxe is instantiated for a HBA, the numbers of targets and
92 # LUNs are retrieved from the host during virtio-scsi setup.
93 # MdeModulePkg/Bus/Scsi/ScsiBusDxe then scans all MaxTarget * MaxLun
94 # possible devices. This can take extremely long, for example with
95 # MaxTarget=255 and MaxLun=16383. The *inclusive* constants below limit
96 # MaxTarget and MaxLun, independently, should the host report higher values,
97 # so that scanning the number of devices given by their product is still
98 # acceptably fast.
99 gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit|31|UINT16|6
100 gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7
101
102 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|0x8
103 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|0x9
104 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa
105 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0xb
106 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|0xc
107 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|0xd
108 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|0x0|UINT32|0xe
109 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress|0x0|UINT32|0xf
110 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase|0x0|UINT32|0x11
111 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize|0x0|UINT32|0x12
112 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|0x0|UINT32|0x13
113 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize|0x0|UINT32|0x14
114 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase|0x0|UINT32|0x18
115 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize|0x0|UINT32|0x19
116 gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0x1a
117 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd|0x0|UINT32|0x1f
118
119 [PcdsDynamic, PcdsDynamicEx]
120 gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2
121 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10
122 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0|UINT16|0x1b
123 gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE|BOOLEAN|0x21
124
125 ## The IO port aperture shared by all PCI root bridges.
126 #
127 gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22
128 gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23
129
130 ## The 32-bit MMIO aperture shared by all PCI root bridges.
131 #
132 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24
133 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25
134
135 ## The 64-bit MMIO aperture shared by all PCI root bridges.
136 #
137 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26
138 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27
139
140 ## The following setting controls how many megabytes we configure as TSEG on
141 # Q35, for SMRAM purposes. Permitted defaults are: 1, 2, 8. Other defaults
142 # cause undefined behavior. During boot, the PCD is updated by PlatformPei
143 # to reflect the extended TSEG size, if one is advertized by QEMU.
144 #
145 # This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).
146 gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20
147
148 [PcdsFeatureFlag]
149 gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c
150 gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d
151
152 ## This feature flag enables SMM/SMRAM support. Note that it also requires
153 # such support from the underlying QEMU instance; if that support is not
154 # present, the firmware will reject continuing after a certain point.
155 #
156 # The flag also acts as a general "security switch"; when TRUE, many
157 # components will change behavior, with the goal of preventing a malicious
158 # runtime OS from tampering with firmware structures (special memory ranges
159 # used by OVMF, the varstore pflash chip, LockBox etc).
160 gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire|FALSE|BOOLEAN|0x1e