OvmfPkg/PlatformPei/MemDetect.c

   1 /**@file
   2   Memory Detection for Virtual Machines.
   3
   4   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 Module Name:
   8
   9   MemDetect.c
  10
  11 **/
  12
  13 //
  14 // The package level header files this module uses
  15 //
  16 #include <IndustryStandard/E820.h>
  17 #include <IndustryStandard/I440FxPiix4.h>
  18 #include <IndustryStandard/Q35MchIch9.h>
  19 #include <PiPei.h>
  20
  21 //
  22 // The Library classes this module consumes
  23 //
  24 #include <Library/BaseLib.h>
  25 #include <Library/BaseMemoryLib.h>
  26 #include <Library/DebugLib.h>
  27 #include <Library/HobLib.h>
  28 #include <Library/IoLib.h>
  29 #include <Library/PcdLib.h>
  30 #include <Library/PciLib.h>
  31 #include <Library/PeimEntryPoint.h>
  32 #include <Library/ResourcePublicationLib.h>
  33 #include <Library/MtrrLib.h>
  34 #include <Library/QemuFwCfgLib.h>
  35
  36 #include "Platform.h"
  37 #include "Cmos.h"
  38
  39 UINT8 mPhysMemAddressWidth;
  40
  41 STATIC UINT32 mS3AcpiReservedMemoryBase;
  42 STATIC UINT32 mS3AcpiReservedMemorySize;
  43
  44 STATIC UINT16 mQ35TsegMbytes;
  45
  46 UINT32 mQemuUc32Base;
  47
  48 VOID
  49 Q35TsegMbytesInitialization (
  50   VOID
  51   )
  52 {
  53   UINT16        ExtendedTsegMbytes;
  54   RETURN_STATUS PcdStatus;
  55
  56   if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {
  57     DEBUG ((
  58       DEBUG_ERROR,
  59       "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
  60       "only DID=0x%04x (Q35) is supported\n",
  61       __FUNCTION__,
  62       mHostBridgeDevId,
  63       INTEL_Q35_MCH_DEVICE_ID
  64       ));
  65     ASSERT (FALSE);
  66     CpuDeadLoop ();
  67   }
  68
  69   //
  70   // Check if QEMU offers an extended TSEG.
  71   //
  72   // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB
  73   // register, and reading back the register.
  74   //
  75   // On a QEMU machine type that does not offer an extended TSEG, the initial
  76   // write overwrites whatever value a malicious guest OS may have placed in
  77   // the (unimplemented) register, before entering S3 or rebooting.
  78   // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.
  79   //
  80   // On a QEMU machine type that offers an extended TSEG, the initial write
  81   // triggers an update to the register. Subsequently, the value read back
  82   // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the
  83   // number of megabytes.
  84   //
  85   PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);
  86   ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));
  87   if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {
  88     mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);
  89     return;
  90   }
  91
  92   DEBUG ((
  93     DEBUG_INFO,
  94     "%a: QEMU offers an extended TSEG (%d MB)\n",
  95     __FUNCTION__,
  96     ExtendedTsegMbytes
  97     ));
  98   PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);
  99   ASSERT_RETURN_ERROR (PcdStatus);
 100   mQ35TsegMbytes = ExtendedTsegMbytes;
 101 }
 102
 103
 104 VOID
 105 QemuUc32BaseInitialization (
 106   VOID
 107   )
 108 {
 109   UINT32 LowerMemorySize;
 110   UINT32 Uc32Size;
 111
 112   if (mXen) {
 113     return;
 114   }
 115
 116   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 117     //
 118     // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
 119     // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
 120     // setting PcdPciExpressBaseAddress such that describing the
 121     // [PcdPciExpressBaseAddress, 4GB) range require a very small number of
 122     // variable MTRRs (preferably 1 or 2).
 123     //
 124     ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);
 125     mQemuUc32Base = (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress);
 126     return;
 127   }
 128
 129   ASSERT (mHostBridgeDevId == INTEL_82441_DEVICE_ID);
 130   //
 131   // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one
 132   // variable MTRR suffices by truncating the size to a whole power of two,
 133   // while keeping the end affixed to 4GB. This will round the base up.
 134   //
 135   LowerMemorySize = GetSystemMemorySizeBelow4gb ();
 136   Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));
 137   mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);
 138   //
 139   // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.
 140   // Therefore mQemuUc32Base is at least 2GB.
 141   //
 142   ASSERT (mQemuUc32Base >= BASE_2GB);
 143
 144   if (mQemuUc32Base != LowerMemorySize) {
 145     DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, for "
 146       "an UC32 size of 0x%x\n", __FUNCTION__, LowerMemorySize, mQemuUc32Base,
 147       Uc32Size));
 148   }
 149 }
 150
 151
 152 /**
 153   Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside
 154   of the 32-bit address range.
 155
 156   Find the highest exclusive >=4GB RAM address, or produce memory resource
 157   descriptor HOBs for RAM entries that start at or above 4GB.
 158
 159   @param[out] MaxAddress  If MaxAddress is NULL, then ScanOrAdd64BitE820Ram()
 160                           produces memory resource descriptor HOBs for RAM
 161                           entries that start at or above 4GB.
 162
 163                           Otherwise, MaxAddress holds the highest exclusive
 164                           >=4GB RAM address on output. If QEMU's fw_cfg E820
 165                           RAM map contains no RAM entry that starts outside of
 166                           the 32-bit address range, then MaxAddress is exactly
 167                           4GB on output.
 168
 169   @retval EFI_SUCCESS         The fw_cfg E820 RAM map was found and processed.
 170
 171   @retval EFI_PROTOCOL_ERROR  The RAM map was found, but its size wasn't a
 172                               whole multiple of sizeof(EFI_E820_ENTRY64). No
 173                               RAM entry was processed.
 174
 175   @return                     Error codes from QemuFwCfgFindFile(). No RAM
 176                               entry was processed.
 177 **/
 178 STATIC
 179 EFI_STATUS
 180 ScanOrAdd64BitE820Ram (
 181   OUT UINT64 *MaxAddress OPTIONAL
 182   )
 183 {
 184   EFI_STATUS           Status;
 185   FIRMWARE_CONFIG_ITEM FwCfgItem;
 186   UINTN                FwCfgSize;
 187   EFI_E820_ENTRY64     E820Entry;
 188   UINTN                Processed;
 189
 190   Status = QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize);
 191   if (EFI_ERROR (Status)) {
 192     return Status;
 193   }
 194   if (FwCfgSize % sizeof E820Entry != 0) {
 195     return EFI_PROTOCOL_ERROR;
 196   }
 197
 198   if (MaxAddress != NULL) {
 199     *MaxAddress = BASE_4GB;
 200   }
 201
 202   QemuFwCfgSelectItem (FwCfgItem);
 203   for (Processed = 0; Processed < FwCfgSize; Processed += sizeof E820Entry) {
 204     QemuFwCfgReadBytes (sizeof E820Entry, &E820Entry);
 205     DEBUG ((
 206       DEBUG_VERBOSE,
 207       "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",
 208       __FUNCTION__,
 209       E820Entry.BaseAddr,
 210       E820Entry.Length,
 211       E820Entry.Type
 212       ));
 213     if (E820Entry.Type == EfiAcpiAddressRangeMemory &&
 214         E820Entry.BaseAddr >= BASE_4GB) {
 215       if (MaxAddress == NULL) {
 216         UINT64 Base;
 217         UINT64 End;
 218
 219         //
 220         // Round up the start address, and round down the end address.
 221         //
 222         Base = ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE);
 223         End = (E820Entry.BaseAddr + E820Entry.Length) &
 224               ~(UINT64)EFI_PAGE_MASK;
 225         if (Base < End) {
 226           AddMemoryRangeHob (Base, End);
 227           DEBUG ((
 228             DEBUG_VERBOSE,
 229             "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n",
 230             __FUNCTION__,
 231             Base,
 232             End
 233             ));
 234         }
 235       } else {
 236         UINT64 Candidate;
 237
 238         Candidate = E820Entry.BaseAddr + E820Entry.Length;
 239         if (Candidate > *MaxAddress) {
 240           *MaxAddress = Candidate;
 241           DEBUG ((
 242             DEBUG_VERBOSE,
 243             "%a: MaxAddress=0x%Lx\n",
 244             __FUNCTION__,
 245             *MaxAddress
 246             ));
 247         }
 248       }
 249     }
 250   }
 251   return EFI_SUCCESS;
 252 }
 253
 254
 255 UINT32
 256 GetSystemMemorySizeBelow4gb (
 257   VOID
 258   )
 259 {
 260   UINT8 Cmos0x34;
 261   UINT8 Cmos0x35;
 262
 263   //
 264   // CMOS 0x34/0x35 specifies the system memory above 16 MB.
 265   // * CMOS(0x35) is the high byte
 266   // * CMOS(0x34) is the low byte
 267   // * The size is specified in 64kb chunks
 268   // * Since this is memory above 16MB, the 16MB must be added
 269   //   into the calculation to get the total memory size.
 270   //
 271
 272   Cmos0x34 = (UINT8) CmosRead8 (0x34);
 273   Cmos0x35 = (UINT8) CmosRead8 (0x35);
 274
 275   return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);
 276 }
 277
 278
 279 STATIC
 280 UINT64
 281 GetSystemMemorySizeAbove4gb (
 282   )
 283 {
 284   UINT32 Size;
 285   UINTN  CmosIndex;
 286
 287   //
 288   // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
 289   // * CMOS(0x5d) is the most significant size byte
 290   // * CMOS(0x5c) is the middle size byte
 291   // * CMOS(0x5b) is the least significant size byte
 292   // * The size is specified in 64kb chunks
 293   //
 294
 295   Size = 0;
 296   for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {
 297     Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);
 298   }
 299
 300   return LShiftU64 (Size, 16);
 301 }
 302
 303
 304 /**
 305   Return the highest address that DXE could possibly use, plus one.
 306 **/
 307 STATIC
 308 UINT64
 309 GetFirstNonAddress (
 310   VOID
 311   )
 312 {
 313   UINT64               FirstNonAddress;
 314   UINT64               Pci64Base, Pci64Size;
 315   CHAR8                MbString[7 + 1];
 316   EFI_STATUS           Status;
 317   FIRMWARE_CONFIG_ITEM FwCfgItem;
 318   UINTN                FwCfgSize;
 319   UINT64               HotPlugMemoryEnd;
 320   RETURN_STATUS        PcdStatus;
 321
 322   //
 323   // set FirstNonAddress to suppress incorrect compiler/analyzer warnings
 324   //
 325   FirstNonAddress = 0;
 326
 327   //
 328   // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM
 329   // address from it. This can express an address >= 4GB+1TB.
 330   //
 331   // Otherwise, get the flat size of the memory above 4GB from the CMOS (which
 332   // can only express a size smaller than 1TB), and add it to 4GB.
 333   //
 334   Status = ScanOrAdd64BitE820Ram (&FirstNonAddress);
 335   if (EFI_ERROR (Status)) {
 336     FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();
 337   }
 338
 339   //
 340   // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO
 341   // resources to 32-bit anyway. See DegradeResource() in
 342   // "PciResourceSupport.c".
 343   //
 344 #ifdef MDE_CPU_IA32
 345   if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
 346     return FirstNonAddress;
 347   }
 348 #endif
 349
 350   //
 351   // Otherwise, in order to calculate the highest address plus one, we must
 352   // consider the 64-bit PCI host aperture too. Fetch the default size.
 353   //
 354   Pci64Size = PcdGet64 (PcdPciMmio64Size);
 355
 356   //
 357   // See if the user specified the number of megabytes for the 64-bit PCI host
 358   // aperture. The number of non-NUL characters in MbString allows for
 359   // 9,999,999 MB, which is approximately 10 TB.
 360   //
 361   // As signaled by the "X-" prefix, this knob is experimental, and might go
 362   // away at any time.
 363   //
 364   Status = QemuFwCfgFindFile ("opt/ovmf/X-PciMmio64Mb", &FwCfgItem,
 365              &FwCfgSize);
 366   if (!EFI_ERROR (Status)) {
 367     if (FwCfgSize >= sizeof MbString) {
 368       DEBUG ((EFI_D_WARN,
 369         "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",
 370         __FUNCTION__));
 371     } else {
 372       QemuFwCfgSelectItem (FwCfgItem);
 373       QemuFwCfgReadBytes (FwCfgSize, MbString);
 374       MbString[FwCfgSize] = '\0';
 375       Pci64Size = LShiftU64 (AsciiStrDecimalToUint64 (MbString), 20);
 376     }
 377   }
 378
 379   if (Pci64Size == 0) {
 380     if (mBootMode != BOOT_ON_S3_RESUME) {
 381       DEBUG ((EFI_D_INFO, "%a: disabling 64-bit PCI host aperture\n",
 382         __FUNCTION__));
 383       PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);
 384       ASSERT_RETURN_ERROR (PcdStatus);
 385     }
 386
 387     //
 388     // There's nothing more to do; the amount of memory above 4GB fully
 389     // determines the highest address plus one. The memory hotplug area (see
 390     // below) plays no role for the firmware in this case.
 391     //
 392     return FirstNonAddress;
 393   }
 394
 395   //
 396   // The "etc/reserved-memory-end" fw_cfg file, when present, contains an
 397   // absolute, exclusive end address for the memory hotplug area. This area
 398   // starts right at the end of the memory above 4GB. The 64-bit PCI host
 399   // aperture must be placed above it.
 400   //
 401   Status = QemuFwCfgFindFile ("etc/reserved-memory-end", &FwCfgItem,
 402              &FwCfgSize);
 403   if (!EFI_ERROR (Status) && FwCfgSize == sizeof HotPlugMemoryEnd) {
 404     QemuFwCfgSelectItem (FwCfgItem);
 405     QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd);
 406     DEBUG ((DEBUG_VERBOSE, "%a: HotPlugMemoryEnd=0x%Lx\n", __FUNCTION__,
 407       HotPlugMemoryEnd));
 408
 409     ASSERT (HotPlugMemoryEnd >= FirstNonAddress);
 410     FirstNonAddress = HotPlugMemoryEnd;
 411   }
 412
 413   //
 414   // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
 415   // that the host can map it with 1GB hugepages. Follow suit.
 416   //
 417   Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);
 418   Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);
 419
 420   //
 421   // The 64-bit PCI host aperture should also be "naturally" aligned. The
 422   // alignment is determined by rounding the size of the aperture down to the
 423   // next smaller or equal power of two. That is, align the aperture by the
 424   // largest BAR size that can fit into it.
 425   //
 426   Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));
 427
 428   if (mBootMode != BOOT_ON_S3_RESUME) {
 429     //
 430     // The core PciHostBridgeDxe driver will automatically add this range to
 431     // the GCD memory space map through our PciHostBridgeLib instance; here we
 432     // only need to set the PCDs.
 433     //
 434     PcdStatus = PcdSet64S (PcdPciMmio64Base, Pci64Base);
 435     ASSERT_RETURN_ERROR (PcdStatus);
 436     PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);
 437     ASSERT_RETURN_ERROR (PcdStatus);
 438
 439     DEBUG ((EFI_D_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
 440       __FUNCTION__, Pci64Base, Pci64Size));
 441   }
 442
 443   //
 444   // The useful address space ends with the 64-bit PCI host aperture.
 445   //
 446   FirstNonAddress = Pci64Base + Pci64Size;
 447   return FirstNonAddress;
 448 }
 449
 450
 451 /**
 452   Initialize the mPhysMemAddressWidth variable, based on guest RAM size.
 453 **/
 454 VOID
 455 AddressWidthInitialization (
 456   VOID
 457   )
 458 {
 459   UINT64 FirstNonAddress;
 460
 461   //
 462   // As guest-physical memory size grows, the permanent PEI RAM requirements
 463   // are dominated by the identity-mapping page tables built by the DXE IPL.
 464   // The DXL IPL keys off of the physical address bits advertized in the CPU
 465   // HOB. To conserve memory, we calculate the minimum address width here.
 466   //
 467   FirstNonAddress      = GetFirstNonAddress ();
 468   mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);
 469
 470   //
 471   // If FirstNonAddress is not an integral power of two, then we need an
 472   // additional bit.
 473   //
 474   if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {
 475     ++mPhysMemAddressWidth;
 476   }
 477
 478   //
 479   // The minimum address width is 36 (covers up to and excluding 64 GB, which
 480   // is the maximum for Ia32 + PAE). The theoretical architecture maximum for
 481   // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
 482   // can simply assert that here, since 48 bits are good enough for 256 TB.
 483   //
 484   if (mPhysMemAddressWidth <= 36) {
 485     mPhysMemAddressWidth = 36;
 486   }
 487   ASSERT (mPhysMemAddressWidth <= 48);
 488 }
 489
 490
 491 /**
 492   Calculate the cap for the permanent PEI memory.
 493 **/
 494 STATIC
 495 UINT32
 496 GetPeiMemoryCap (
 497   VOID
 498   )
 499 {
 500   BOOLEAN Page1GSupport;
 501   UINT32  RegEax;
 502   UINT32  RegEdx;
 503   UINT32  Pml4Entries;
 504   UINT32  PdpEntries;
 505   UINTN   TotalPages;
 506
 507   //
 508   // If DXE is 32-bit, then just return the traditional 64 MB cap.
 509   //
 510 #ifdef MDE_CPU_IA32
 511   if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
 512     return SIZE_64MB;
 513   }
 514 #endif
 515
 516   //
 517   // Dependent on physical address width, PEI memory allocations can be
 518   // dominated by the page tables built for 64-bit DXE. So we key the cap off
 519   // of those. The code below is based on CreateIdentityMappingPageTables() in
 520   // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
 521   //
 522   Page1GSupport = FALSE;
 523   if (PcdGetBool (PcdUse1GPageTable)) {
 524     AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
 525     if (RegEax >= 0x80000001) {
 526       AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
 527       if ((RegEdx & BIT26) != 0) {
 528         Page1GSupport = TRUE;
 529       }
 530     }
 531   }
 532
 533   if (mPhysMemAddressWidth <= 39) {
 534     Pml4Entries = 1;
 535     PdpEntries = 1 << (mPhysMemAddressWidth - 30);
 536     ASSERT (PdpEntries <= 0x200);
 537   } else {
 538     Pml4Entries = 1 << (mPhysMemAddressWidth - 39);
 539     ASSERT (Pml4Entries <= 0x200);
 540     PdpEntries = 512;
 541   }
 542
 543   TotalPages = Page1GSupport ? Pml4Entries + 1 :
 544                                (PdpEntries + 1) * Pml4Entries + 1;
 545   ASSERT (TotalPages <= 0x40201);
 546
 547   //
 548   // Add 64 MB for miscellaneous allocations. Note that for
 549   // mPhysMemAddressWidth values close to 36, the cap will actually be
 550   // dominated by this increment.
 551   //
 552   return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);
 553 }
 554
 555
 556 /**
 557   Publish PEI core memory
 558
 559   @return EFI_SUCCESS     The PEIM initialized successfully.
 560
 561 **/
 562 EFI_STATUS
 563 PublishPeiMemory (
 564   VOID
 565   )
 566 {
 567   EFI_STATUS                  Status;
 568   EFI_PHYSICAL_ADDRESS        MemoryBase;
 569   UINT64                      MemorySize;
 570   UINT32                      LowerMemorySize;
 571   UINT32                      PeiMemoryCap;
 572
 573   LowerMemorySize = GetSystemMemorySizeBelow4gb ();
 574   if (FeaturePcdGet (PcdSmmSmramRequire)) {
 575     //
 576     // TSEG is chipped from the end of low RAM
 577     //
 578     LowerMemorySize -= mQ35TsegMbytes * SIZE_1MB;
 579   }
 580
 581   //
 582   // If S3 is supported, then the S3 permanent PEI memory is placed next,
 583   // downwards. Its size is primarily dictated by CpuMpPei. The formula below
 584   // is an approximation.
 585   //
 586   if (mS3Supported) {
 587     mS3AcpiReservedMemorySize = SIZE_512KB +
 588       mMaxCpuCount *
 589       PcdGet32 (PcdCpuApStackSize);
 590     mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;
 591     LowerMemorySize = mS3AcpiReservedMemoryBase;
 592   }
 593
 594   if (mBootMode == BOOT_ON_S3_RESUME) {
 595     MemoryBase = mS3AcpiReservedMemoryBase;
 596     MemorySize = mS3AcpiReservedMemorySize;
 597   } else {
 598     PeiMemoryCap = GetPeiMemoryCap ();
 599     DEBUG ((EFI_D_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
 600       __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));
 601
 602     //
 603     // Determine the range of memory to use during PEI
 604     //
 605     // Technically we could lay the permanent PEI RAM over SEC's temporary
 606     // decompression and scratch buffer even if "secure S3" is needed, since
 607     // their lifetimes don't overlap. However, PeiFvInitialization() will cover
 608     // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory
 609     // allocation HOB, and other allocations served from the permanent PEI RAM
 610     // shouldn't overlap with that HOB.
 611     //
 612     MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?
 613       PcdGet32 (PcdOvmfDecompressionScratchEnd) :
 614       PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);
 615     MemorySize = LowerMemorySize - MemoryBase;
 616     if (MemorySize > PeiMemoryCap) {
 617       MemoryBase = LowerMemorySize - PeiMemoryCap;
 618       MemorySize = PeiMemoryCap;
 619     }
 620   }
 621
 622   //
 623   // Publish this memory to the PEI Core
 624   //
 625   Status = PublishSystemMemory(MemoryBase, MemorySize);
 626   ASSERT_EFI_ERROR (Status);
 627
 628   return Status;
 629 }
 630
 631
 632 /**
 633   Peform Memory Detection for QEMU / KVM
 634
 635 **/
 636 STATIC
 637 VOID
 638 QemuInitializeRam (
 639   VOID
 640   )
 641 {
 642   UINT64                      LowerMemorySize;
 643   UINT64                      UpperMemorySize;
 644   MTRR_SETTINGS               MtrrSettings;
 645   EFI_STATUS                  Status;
 646
 647   DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__));
 648
 649   //
 650   // Determine total memory size available
 651   //
 652   LowerMemorySize = GetSystemMemorySizeBelow4gb ();
 653   UpperMemorySize = GetSystemMemorySizeAbove4gb ();
 654
 655   if (mBootMode == BOOT_ON_S3_RESUME) {
 656     //
 657     // Create the following memory HOB as an exception on the S3 boot path.
 658     //
 659     // Normally we'd create memory HOBs only on the normal boot path. However,
 660     // CpuMpPei specifically needs such a low-memory HOB on the S3 path as
 661     // well, for "borrowing" a subset of it temporarily, for the AP startup
 662     // vector.
 663     //
 664     // CpuMpPei saves the original contents of the borrowed area in permanent
 665     // PEI RAM, in a backup buffer allocated with the normal PEI services.
 666     // CpuMpPei restores the original contents ("returns" the borrowed area) at
 667     // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before
 668     // transferring control to the OS's wakeup vector in the FACS.
 669     //
 670     // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to
 671     // restore the original contents. Furthermore, we expect all such PEIMs
 672     // (CpuMpPei included) to claim the borrowed areas by producing memory
 673     // allocation HOBs, and to honor preexistent memory allocation HOBs when
 674     // looking for an area to borrow.
 675     //
 676     AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);
 677   } else {
 678     //
 679     // Create memory HOBs
 680     //
 681     AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);
 682
 683     if (FeaturePcdGet (PcdSmmSmramRequire)) {
 684       UINT32 TsegSize;
 685
 686       TsegSize = mQ35TsegMbytes * SIZE_1MB;
 687       AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);
 688       AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize,
 689         TRUE);
 690     } else {
 691       AddMemoryRangeHob (BASE_1MB, LowerMemorySize);
 692     }
 693
 694     //
 695     // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM
 696     // entries. Otherwise, create a single memory HOB with the flat >=4GB
 697     // memory size read from the CMOS.
 698     //
 699     Status = ScanOrAdd64BitE820Ram (NULL);
 700     if (EFI_ERROR (Status) && UpperMemorySize != 0) {
 701       AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);
 702     }
 703   }
 704
 705   //
 706   // We'd like to keep the following ranges uncached:
 707   // - [640 KB, 1 MB)
 708   // - [LowerMemorySize, 4 GB)
 709   //
 710   // Everything else should be WB. Unfortunately, programming the inverse (ie.
 711   // keeping the default UC, and configuring the complement set of the above as
 712   // WB) is not reliable in general, because the end of the upper RAM can have
 713   // practically any alignment, and we may not have enough variable MTRRs to
 714   // cover it exactly.
 715   //
 716   if (IsMtrrSupported ()) {
 717     MtrrGetAllMtrrs (&MtrrSettings);
 718
 719     //
 720     // MTRRs disabled, fixed MTRRs disabled, default type is uncached
 721     //
 722     ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);
 723     ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);
 724     ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);
 725
 726     //
 727     // flip default type to writeback
 728     //
 729     SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);
 730     ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);
 731     MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;
 732     MtrrSetAllMtrrs (&MtrrSettings);
 733
 734     //
 735     // Set memory range from 640KB to 1MB to uncacheable
 736     //
 737     Status = MtrrSetMemoryAttribute (BASE_512KB + BASE_128KB,
 738                BASE_1MB - (BASE_512KB + BASE_128KB), CacheUncacheable);
 739     ASSERT_EFI_ERROR (Status);
 740
 741     //
 742     // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI
 743     // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.
 744     //
 745     Status = MtrrSetMemoryAttribute (mQemuUc32Base, SIZE_4GB - mQemuUc32Base,
 746                CacheUncacheable);
 747     ASSERT_EFI_ERROR (Status);
 748   }
 749 }
 750
 751 /**
 752   Publish system RAM and reserve memory regions
 753
 754 **/
 755 VOID
 756 InitializeRamRegions (
 757   VOID
 758   )
 759 {
 760   if (!mXen) {
 761     QemuInitializeRam ();
 762   } else {
 763     XenPublishRamRegions ();
 764   }
 765
 766   if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {
 767     //
 768     // This is the memory range that will be used for PEI on S3 resume
 769     //
 770     BuildMemoryAllocationHob (
 771       mS3AcpiReservedMemoryBase,
 772       mS3AcpiReservedMemorySize,
 773       EfiACPIMemoryNVS
 774       );
 775
 776     //
 777     // Cover the initial RAM area used as stack and temporary PEI heap.
 778     //
 779     // This is reserved as ACPI NVS so it can be used on S3 resume.
 780     //
 781     BuildMemoryAllocationHob (
 782       PcdGet32 (PcdOvmfSecPeiTempRamBase),
 783       PcdGet32 (PcdOvmfSecPeiTempRamSize),
 784       EfiACPIMemoryNVS
 785       );
 786
 787     //
 788     // SEC stores its table of GUIDed section handlers here.
 789     //
 790     BuildMemoryAllocationHob (
 791       PcdGet64 (PcdGuidedExtractHandlerTableAddress),
 792       PcdGet32 (PcdGuidedExtractHandlerTableSize),
 793       EfiACPIMemoryNVS
 794       );
 795
 796 #ifdef MDE_CPU_X64
 797     //
 798     // Reserve the initial page tables built by the reset vector code.
 799     //
 800     // Since this memory range will be used by the Reset Vector on S3
 801     // resume, it must be reserved as ACPI NVS.
 802     //
 803     BuildMemoryAllocationHob (
 804       (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecPageTablesBase),
 805       (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize),
 806       EfiACPIMemoryNVS
 807       );
 808 #endif
 809   }
 810
 811   if (mBootMode != BOOT_ON_S3_RESUME) {
 812     if (!FeaturePcdGet (PcdSmmSmramRequire)) {
 813       //
 814       // Reserve the lock box storage area
 815       //
 816       // Since this memory range will be used on S3 resume, it must be
 817       // reserved as ACPI NVS.
 818       //
 819       // If S3 is unsupported, then various drivers might still write to the
 820       // LockBox area. We ought to prevent DXE from serving allocation requests
 821       // such that they would overlap the LockBox storage.
 822       //
 823       ZeroMem (
 824         (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),
 825         (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)
 826         );
 827       BuildMemoryAllocationHob (
 828         (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),
 829         (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),
 830         mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
 831         );
 832     }
 833
 834     if (FeaturePcdGet (PcdSmmSmramRequire)) {
 835       UINT32 TsegSize;
 836
 837       //
 838       // Make sure the TSEG area that we reported as a reserved memory resource
 839       // cannot be used for reserved memory allocations.
 840       //
 841       TsegSize = mQ35TsegMbytes * SIZE_1MB;
 842       BuildMemoryAllocationHob (
 843         GetSystemMemorySizeBelow4gb() - TsegSize,
 844         TsegSize,
 845         EfiReservedMemoryType
 846         );
 847     }
 848   }
 849 }