OvmfPkg/PlatformPei/MemDetect.c

   1 /**@file
   2   Memory Detection for Virtual Machines.
   3
   4   Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 Module Name:
  14
  15   MemDetect.c
  16
  17 **/
  18
  19 //
  20 // The package level header files this module uses
  21 //
  22 #include <PiPei.h>
  23
  24 //
  25 // The Library classes this module consumes
  26 //
  27 #include <Library/BaseMemoryLib.h>
  28 #include <Library/DebugLib.h>
  29 #include <Library/HobLib.h>
  30 #include <Library/IoLib.h>
  31 #include <Library/PcdLib.h>
  32 #include <Library/PeimEntryPoint.h>
  33 #include <Library/ResourcePublicationLib.h>
  34 #include <Library/MtrrLib.h>
  35
  36 #include "Platform.h"
  37 #include "Cmos.h"
  38
  39 UINT8 mPhysMemAddressWidth;
  40
  41 UINT32
  42 GetSystemMemorySizeBelow4gb (
  43   VOID
  44   )
  45 {
  46   UINT8 Cmos0x34;
  47   UINT8 Cmos0x35;
  48
  49   //
  50   // CMOS 0x34/0x35 specifies the system memory above 16 MB.
  51   // * CMOS(0x35) is the high byte
  52   // * CMOS(0x34) is the low byte
  53   // * The size is specified in 64kb chunks
  54   // * Since this is memory above 16MB, the 16MB must be added
  55   //   into the calculation to get the total memory size.
  56   //
  57
  58   Cmos0x34 = (UINT8) CmosRead8 (0x34);
  59   Cmos0x35 = (UINT8) CmosRead8 (0x35);
  60
  61   return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);
  62 }
  63
  64
  65 STATIC
  66 UINT64
  67 GetSystemMemorySizeAbove4gb (
  68   )
  69 {
  70   UINT32 Size;
  71   UINTN  CmosIndex;
  72
  73   //
  74   // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
  75   // * CMOS(0x5d) is the most significant size byte
  76   // * CMOS(0x5c) is the middle size byte
  77   // * CMOS(0x5b) is the least significant size byte
  78   // * The size is specified in 64kb chunks
  79   //
  80
  81   Size = 0;
  82   for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {
  83     Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);
  84   }
  85
  86   return LShiftU64 (Size, 16);
  87 }
  88
  89
  90 /**
  91   Initialize the mPhysMemAddressWidth variable, based on guest RAM size.
  92 **/
  93 VOID
  94 AddressWidthInitialization (
  95   VOID
  96   )
  97 {
  98   UINT64 FirstNonAddress;
  99
 100   //
 101   // As guest-physical memory size grows, the permanent PEI RAM requirements
 102   // are dominated by the identity-mapping page tables built by the DXE IPL.
 103   // The DXL IPL keys off of the physical address bits advertized in the CPU
 104   // HOB. To conserve memory, we calculate the minimum address width here.
 105   //
 106   FirstNonAddress      = BASE_4GB + GetSystemMemorySizeAbove4gb ();
 107   mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);
 108
 109   //
 110   // If FirstNonAddress is not an integral power of two, then we need an
 111   // additional bit.
 112   //
 113   if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {
 114     ++mPhysMemAddressWidth;
 115   }
 116
 117   //
 118   // The minimum address width is 36 (covers up to and excluding 64 GB, which
 119   // is the maximum for Ia32 + PAE). The theoretical architecture maximum for
 120   // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
 121   // can simply assert that here, since 48 bits are good enough for 256 TB.
 122   //
 123   if (mPhysMemAddressWidth <= 36) {
 124     mPhysMemAddressWidth = 36;
 125   }
 126   ASSERT (mPhysMemAddressWidth <= 48);
 127 }
 128
 129
 130 /**
 131   Calculate the cap for the permanent PEI memory.
 132 **/
 133 STATIC
 134 UINT32
 135 GetPeiMemoryCap (
 136   VOID
 137   )
 138 {
 139   BOOLEAN Page1GSupport;
 140   UINT32  RegEax;
 141   UINT32  RegEdx;
 142   UINT32  Pml4Entries;
 143   UINT32  PdpEntries;
 144   UINTN   TotalPages;
 145
 146   //
 147   // If DXE is 32-bit, then just return the traditional 64 MB cap.
 148   //
 149 #ifdef MDE_CPU_IA32
 150   if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
 151     return SIZE_64MB;
 152   }
 153 #endif
 154
 155   //
 156   // Dependent on physical address width, PEI memory allocations can be
 157   // dominated by the page tables built for 64-bit DXE. So we key the cap off
 158   // of those. The code below is based on CreateIdentityMappingPageTables() in
 159   // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
 160   //
 161   Page1GSupport = FALSE;
 162   if (PcdGetBool (PcdUse1GPageTable)) {
 163     AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
 164     if (RegEax >= 0x80000001) {
 165       AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
 166       if ((RegEdx & BIT26) != 0) {
 167         Page1GSupport = TRUE;
 168       }
 169     }
 170   }
 171
 172   if (mPhysMemAddressWidth <= 39) {
 173     Pml4Entries = 1;
 174     PdpEntries = 1 << (mPhysMemAddressWidth - 30);
 175     ASSERT (PdpEntries <= 0x200);
 176   } else {
 177     Pml4Entries = 1 << (mPhysMemAddressWidth - 39);
 178     ASSERT (Pml4Entries <= 0x200);
 179     PdpEntries = 512;
 180   }
 181
 182   TotalPages = Page1GSupport ? Pml4Entries + 1 :
 183                                (PdpEntries + 1) * Pml4Entries + 1;
 184   ASSERT (TotalPages <= 0x40201);
 185
 186   //
 187   // Add 64 MB for miscellaneous allocations. Note that for
 188   // mPhysMemAddressWidth values close to 36, the cap will actually be
 189   // dominated by this increment.
 190   //
 191   return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);
 192 }
 193
 194
 195 /**
 196   Publish PEI core memory
 197
 198   @return EFI_SUCCESS     The PEIM initialized successfully.
 199
 200 **/
 201 EFI_STATUS
 202 PublishPeiMemory (
 203   VOID
 204   )
 205 {
 206   EFI_STATUS                  Status;
 207   EFI_PHYSICAL_ADDRESS        MemoryBase;
 208   UINT64                      MemorySize;
 209   UINT64                      LowerMemorySize;
 210   UINT32                      PeiMemoryCap;
 211
 212   if (mBootMode == BOOT_ON_S3_RESUME) {
 213     MemoryBase = PcdGet32 (PcdS3AcpiReservedMemoryBase);
 214     MemorySize = PcdGet32 (PcdS3AcpiReservedMemorySize);
 215   } else {
 216     LowerMemorySize = GetSystemMemorySizeBelow4gb ();
 217
 218     PeiMemoryCap = GetPeiMemoryCap ();
 219     DEBUG ((EFI_D_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
 220       __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));
 221
 222     //
 223     // Determine the range of memory to use during PEI
 224     //
 225     MemoryBase = PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);
 226     MemorySize = LowerMemorySize - MemoryBase;
 227     if (MemorySize > PeiMemoryCap) {
 228       MemoryBase = LowerMemorySize - PeiMemoryCap;
 229       MemorySize = PeiMemoryCap;
 230     }
 231   }
 232
 233   //
 234   // Publish this memory to the PEI Core
 235   //
 236   Status = PublishSystemMemory(MemoryBase, MemorySize);
 237   ASSERT_EFI_ERROR (Status);
 238
 239   return Status;
 240 }
 241
 242
 243 /**
 244   Peform Memory Detection for QEMU / KVM
 245
 246 **/
 247 STATIC
 248 VOID
 249 QemuInitializeRam (
 250   VOID
 251   )
 252 {
 253   UINT64                      LowerMemorySize;
 254   UINT64                      UpperMemorySize;
 255
 256   DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__));
 257
 258   //
 259   // Determine total memory size available
 260   //
 261   LowerMemorySize = GetSystemMemorySizeBelow4gb ();
 262   UpperMemorySize = GetSystemMemorySizeAbove4gb ();
 263
 264   if (mBootMode != BOOT_ON_S3_RESUME) {
 265     //
 266     // Create memory HOBs
 267     //
 268     AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);
 269     AddMemoryRangeHob (BASE_1MB, LowerMemorySize);
 270     if (UpperMemorySize != 0) {
 271       AddUntestedMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);
 272     }
 273   }
 274
 275   MtrrSetMemoryAttribute (BASE_1MB, LowerMemorySize - BASE_1MB, CacheWriteBack);
 276
 277   MtrrSetMemoryAttribute (0, BASE_512KB + BASE_128KB, CacheWriteBack);
 278
 279   if (UpperMemorySize != 0) {
 280     MtrrSetMemoryAttribute (BASE_4GB, UpperMemorySize, CacheWriteBack);
 281   }
 282 }
 283
 284 /**
 285   Publish system RAM and reserve memory regions
 286
 287 **/
 288 VOID
 289 InitializeRamRegions (
 290   VOID
 291   )
 292 {
 293   if (!mXen) {
 294     QemuInitializeRam ();
 295   } else {
 296     XenPublishRamRegions ();
 297   }
 298
 299   if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {
 300     //
 301     // This is the memory range that will be used for PEI on S3 resume
 302     //
 303     BuildMemoryAllocationHob (
 304       (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdS3AcpiReservedMemoryBase),
 305       (UINT64)(UINTN) PcdGet32 (PcdS3AcpiReservedMemorySize),
 306       EfiACPIMemoryNVS
 307       );
 308
 309     //
 310     // Cover the initial RAM area used as stack and temporary PEI heap.
 311     //
 312     // This is reserved as ACPI NVS so it can be used on S3 resume.
 313     //
 314     BuildMemoryAllocationHob (
 315       PcdGet32 (PcdOvmfSecPeiTempRamBase),
 316       PcdGet32 (PcdOvmfSecPeiTempRamSize),
 317       EfiACPIMemoryNVS
 318       );
 319
 320     //
 321     // SEC stores its table of GUIDed section handlers here.
 322     //
 323     BuildMemoryAllocationHob (
 324       PcdGet64 (PcdGuidedExtractHandlerTableAddress),
 325       PcdGet32 (PcdGuidedExtractHandlerTableSize),
 326       EfiACPIMemoryNVS
 327       );
 328
 329 #ifdef MDE_CPU_X64
 330     //
 331     // Reserve the initial page tables built by the reset vector code.
 332     //
 333     // Since this memory range will be used by the Reset Vector on S3
 334     // resume, it must be reserved as ACPI NVS.
 335     //
 336     BuildMemoryAllocationHob (
 337       (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecPageTablesBase),
 338       (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize),
 339       EfiACPIMemoryNVS
 340       );
 341 #endif
 342   }
 343
 344   if (mBootMode != BOOT_ON_S3_RESUME) {
 345     //
 346     // Reserve the lock box storage area
 347     //
 348     // Since this memory range will be used on S3 resume, it must be
 349     // reserved as ACPI NVS.
 350     //
 351     // If S3 is unsupported, then various drivers might still write to the
 352     // LockBox area. We ought to prevent DXE from serving allocation requests
 353     // such that they would overlap the LockBox storage.
 354     //
 355     ZeroMem (
 356       (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),
 357       (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)
 358       );
 359     BuildMemoryAllocationHob (
 360       (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),
 361       (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),
 362       mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
 363       );
 364   }
 365 }