OvmfPkg/PlatformPei/MemDetect.c

   1 /**@file
   2   Memory Detection for Virtual Machines.
   3
   4   Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 Module Name:
  14
  15   MemDetect.c
  16
  17 **/
  18
  19 //
  20 // The package level header files this module uses
  21 //
  22 #include <PiPei.h>
  23
  24 //
  25 // The Library classes this module consumes
  26 //
  27 #include <Library/BaseMemoryLib.h>
  28 #include <Library/DebugLib.h>
  29 #include <Library/HobLib.h>
  30 #include <Library/IoLib.h>
  31 #include <Library/PcdLib.h>
  32 #include <Library/PeimEntryPoint.h>
  33 #include <Library/ResourcePublicationLib.h>
  34 #include <Library/MtrrLib.h>
  35
  36 #include "Platform.h"
  37 #include "Cmos.h"
  38
  39 UINT8 mPhysMemAddressWidth;
  40
  41 UINT32
  42 GetSystemMemorySizeBelow4gb (
  43   VOID
  44   )
  45 {
  46   UINT8 Cmos0x34;
  47   UINT8 Cmos0x35;
  48
  49   //
  50   // CMOS 0x34/0x35 specifies the system memory above 16 MB.
  51   // * CMOS(0x35) is the high byte
  52   // * CMOS(0x34) is the low byte
  53   // * The size is specified in 64kb chunks
  54   // * Since this is memory above 16MB, the 16MB must be added
  55   //   into the calculation to get the total memory size.
  56   //
  57
  58   Cmos0x34 = (UINT8) CmosRead8 (0x34);
  59   Cmos0x35 = (UINT8) CmosRead8 (0x35);
  60
  61   return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);
  62 }
  63
  64
  65 STATIC
  66 UINT64
  67 GetSystemMemorySizeAbove4gb (
  68   )
  69 {
  70   UINT32 Size;
  71   UINTN  CmosIndex;
  72
  73   //
  74   // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
  75   // * CMOS(0x5d) is the most significant size byte
  76   // * CMOS(0x5c) is the middle size byte
  77   // * CMOS(0x5b) is the least significant size byte
  78   // * The size is specified in 64kb chunks
  79   //
  80
  81   Size = 0;
  82   for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {
  83     Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);
  84   }
  85
  86   return LShiftU64 (Size, 16);
  87 }
  88
  89
  90 /**
  91   Initialize the mPhysMemAddressWidth variable, based on guest RAM size.
  92 **/
  93 VOID
  94 AddressWidthInitialization (
  95   VOID
  96   )
  97 {
  98   UINT64 FirstNonAddress;
  99
 100   //
 101   // As guest-physical memory size grows, the permanent PEI RAM requirements
 102   // are dominated by the identity-mapping page tables built by the DXE IPL.
 103   // The DXL IPL keys off of the physical address bits advertized in the CPU
 104   // HOB. To conserve memory, we calculate the minimum address width here.
 105   //
 106   FirstNonAddress      = BASE_4GB + GetSystemMemorySizeAbove4gb ();
 107   mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);
 108
 109   //
 110   // If FirstNonAddress is not an integral power of two, then we need an
 111   // additional bit.
 112   //
 113   if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {
 114     ++mPhysMemAddressWidth;
 115   }
 116
 117   //
 118   // The minimum address width is 36 (covers up to and excluding 64 GB, which
 119   // is the maximum for Ia32 + PAE). The theoretical architecture maximum for
 120   // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
 121   // can simply assert that here, since 48 bits are good enough for 256 TB.
 122   //
 123   if (mPhysMemAddressWidth <= 36) {
 124     mPhysMemAddressWidth = 36;
 125   }
 126   ASSERT (mPhysMemAddressWidth <= 48);
 127 }
 128
 129
 130 /**
 131   Calculate the cap for the permanent PEI memory.
 132 **/
 133 STATIC
 134 UINT32
 135 GetPeiMemoryCap (
 136   VOID
 137   )
 138 {
 139   BOOLEAN Page1GSupport;
 140   UINT32  RegEax;
 141   UINT32  RegEdx;
 142   UINT32  Pml4Entries;
 143   UINT32  PdpEntries;
 144   UINTN   TotalPages;
 145
 146   //
 147   // If DXE is 32-bit, then just return the traditional 64 MB cap.
 148   //
 149 #ifdef MDE_CPU_IA32
 150   if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
 151     return SIZE_64MB;
 152   }
 153 #endif
 154
 155   //
 156   // Dependent on physical address width, PEI memory allocations can be
 157   // dominated by the page tables built for 64-bit DXE. So we key the cap off
 158   // of those. The code below is based on CreateIdentityMappingPageTables() in
 159   // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
 160   //
 161   Page1GSupport = FALSE;
 162   if (PcdGetBool (PcdUse1GPageTable)) {
 163     AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
 164     if (RegEax >= 0x80000001) {
 165       AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
 166       if ((RegEdx & BIT26) != 0) {
 167         Page1GSupport = TRUE;
 168       }
 169     }
 170   }
 171
 172   if (mPhysMemAddressWidth <= 39) {
 173     Pml4Entries = 1;
 174     PdpEntries = 1 << (mPhysMemAddressWidth - 30);
 175     ASSERT (PdpEntries <= 0x200);
 176   } else {
 177     Pml4Entries = 1 << (mPhysMemAddressWidth - 39);
 178     ASSERT (Pml4Entries <= 0x200);
 179     PdpEntries = 512;
 180   }
 181
 182   TotalPages = Page1GSupport ? Pml4Entries + 1 :
 183                                (PdpEntries + 1) * Pml4Entries + 1;
 184   ASSERT (TotalPages <= 0x40201);
 185
 186   //
 187   // Add 64 MB for miscellaneous allocations. Note that for
 188   // mPhysMemAddressWidth values close to 36, the cap will actually be
 189   // dominated by this increment.
 190   //
 191   return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);
 192 }
 193
 194
 195 /**
 196   Publish PEI core memory
 197
 198   @return EFI_SUCCESS     The PEIM initialized successfully.
 199
 200 **/
 201 EFI_STATUS
 202 PublishPeiMemory (
 203   VOID
 204   )
 205 {
 206   EFI_STATUS                  Status;
 207   EFI_PHYSICAL_ADDRESS        MemoryBase;
 208   UINT64                      MemorySize;
 209   UINT64                      LowerMemorySize;
 210   UINT32                      PeiMemoryCap;
 211
 212   if (mBootMode == BOOT_ON_S3_RESUME) {
 213     MemoryBase = PcdGet32 (PcdS3AcpiReservedMemoryBase);
 214     MemorySize = PcdGet32 (PcdS3AcpiReservedMemorySize);
 215   } else {
 216     LowerMemorySize = GetSystemMemorySizeBelow4gb ();
 217
 218     PeiMemoryCap = GetPeiMemoryCap ();
 219     DEBUG ((EFI_D_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
 220       __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));
 221
 222     //
 223     // Determine the range of memory to use during PEI
 224     //
 225     // Technically we could lay the permanent PEI RAM over SEC's temporary
 226     // decompression and scratch buffer even if "secure S3" is needed, since
 227     // their lifetimes don't overlap. However, PeiFvInitialization() will cover
 228     // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory
 229     // allocation HOB, and other allocations served from the permanent PEI RAM
 230     // shouldn't overlap with that HOB.
 231     //
 232     MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?
 233       PcdGet32 (PcdOvmfDecompressionScratchEnd) :
 234       PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);
 235     MemorySize = LowerMemorySize - MemoryBase;
 236     if (MemorySize > PeiMemoryCap) {
 237       MemoryBase = LowerMemorySize - PeiMemoryCap;
 238       MemorySize = PeiMemoryCap;
 239     }
 240   }
 241
 242   //
 243   // Publish this memory to the PEI Core
 244   //
 245   Status = PublishSystemMemory(MemoryBase, MemorySize);
 246   ASSERT_EFI_ERROR (Status);
 247
 248   return Status;
 249 }
 250
 251
 252 /**
 253   Peform Memory Detection for QEMU / KVM
 254
 255 **/
 256 STATIC
 257 VOID
 258 QemuInitializeRam (
 259   VOID
 260   )
 261 {
 262   UINT64                      LowerMemorySize;
 263   UINT64                      UpperMemorySize;
 264   MTRR_SETTINGS               MtrrSettings;
 265   EFI_STATUS                  Status;
 266
 267   DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__));
 268
 269   //
 270   // Determine total memory size available
 271   //
 272   LowerMemorySize = GetSystemMemorySizeBelow4gb ();
 273   UpperMemorySize = GetSystemMemorySizeAbove4gb ();
 274
 275   if (mBootMode != BOOT_ON_S3_RESUME) {
 276     //
 277     // Create memory HOBs
 278     //
 279     AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);
 280     AddMemoryRangeHob (BASE_1MB, LowerMemorySize);
 281     if (UpperMemorySize != 0) {
 282       AddUntestedMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);
 283     }
 284   }
 285
 286   //
 287   // We'd like to keep the following ranges uncached:
 288   // - [640 KB, 1 MB)
 289   // - [LowerMemorySize, 4 GB)
 290   //
 291   // Everything else should be WB. Unfortunately, programming the inverse (ie.
 292   // keeping the default UC, and configuring the complement set of the above as
 293   // WB) is not reliable in general, because the end of the upper RAM can have
 294   // practically any alignment, and we may not have enough variable MTRRs to
 295   // cover it exactly.
 296   //
 297   if (IsMtrrSupported ()) {
 298     MtrrGetAllMtrrs (&MtrrSettings);
 299
 300     //
 301     // MTRRs disabled, fixed MTRRs disabled, default type is uncached
 302     //
 303     ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);
 304     ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);
 305     ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);
 306
 307     //
 308     // flip default type to writeback
 309     //
 310     SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);
 311     ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);
 312     MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;
 313     MtrrSetAllMtrrs (&MtrrSettings);
 314
 315     //
 316     // Set memory range from 640KB to 1MB to uncacheable
 317     //
 318     Status = MtrrSetMemoryAttribute (BASE_512KB + BASE_128KB,
 319                BASE_1MB - (BASE_512KB + BASE_128KB), CacheUncacheable);
 320     ASSERT_EFI_ERROR (Status);
 321
 322     //
 323     // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB as
 324     // uncacheable
 325     //
 326     Status = MtrrSetMemoryAttribute (LowerMemorySize,
 327                SIZE_4GB - LowerMemorySize, CacheUncacheable);
 328     ASSERT_EFI_ERROR (Status);
 329   }
 330 }
 331
 332 /**
 333   Publish system RAM and reserve memory regions
 334
 335 **/
 336 VOID
 337 InitializeRamRegions (
 338   VOID
 339   )
 340 {
 341   if (!mXen) {
 342     QemuInitializeRam ();
 343   } else {
 344     XenPublishRamRegions ();
 345   }
 346
 347   if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {
 348     //
 349     // This is the memory range that will be used for PEI on S3 resume
 350     //
 351     BuildMemoryAllocationHob (
 352       (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdS3AcpiReservedMemoryBase),
 353       (UINT64)(UINTN) PcdGet32 (PcdS3AcpiReservedMemorySize),
 354       EfiACPIMemoryNVS
 355       );
 356
 357     //
 358     // Cover the initial RAM area used as stack and temporary PEI heap.
 359     //
 360     // This is reserved as ACPI NVS so it can be used on S3 resume.
 361     //
 362     BuildMemoryAllocationHob (
 363       PcdGet32 (PcdOvmfSecPeiTempRamBase),
 364       PcdGet32 (PcdOvmfSecPeiTempRamSize),
 365       EfiACPIMemoryNVS
 366       );
 367
 368     //
 369     // SEC stores its table of GUIDed section handlers here.
 370     //
 371     BuildMemoryAllocationHob (
 372       PcdGet64 (PcdGuidedExtractHandlerTableAddress),
 373       PcdGet32 (PcdGuidedExtractHandlerTableSize),
 374       EfiACPIMemoryNVS
 375       );
 376
 377 #ifdef MDE_CPU_X64
 378     //
 379     // Reserve the initial page tables built by the reset vector code.
 380     //
 381     // Since this memory range will be used by the Reset Vector on S3
 382     // resume, it must be reserved as ACPI NVS.
 383     //
 384     BuildMemoryAllocationHob (
 385       (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecPageTablesBase),
 386       (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize),
 387       EfiACPIMemoryNVS
 388       );
 389 #endif
 390   }
 391
 392   if (mBootMode != BOOT_ON_S3_RESUME) {
 393     //
 394     // Reserve the lock box storage area
 395     //
 396     // Since this memory range will be used on S3 resume, it must be
 397     // reserved as ACPI NVS.
 398     //
 399     // If S3 is unsupported, then various drivers might still write to the
 400     // LockBox area. We ought to prevent DXE from serving allocation requests
 401     // such that they would overlap the LockBox storage.
 402     //
 403     ZeroMem (
 404       (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),
 405       (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)
 406       );
 407     BuildMemoryAllocationHob (
 408       (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),
 409       (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),
 410       mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
 411       );
 412   }
 413 }