OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 //
  18 // The package level header files this module uses
  19 //
  20 #include <PiPei.h>
  21
  22 //
  23 // The Library classes this module consumes
  24 //
  25 #include <Library/BaseLib.h>
  26 #include <Library/DebugLib.h>
  27 #include <Library/HobLib.h>
  28 #include <Library/IoLib.h>
  29 #include <Library/MemoryAllocationLib.h>
  30 #include <Library/PcdLib.h>
  31 #include <Library/PciLib.h>
  32 #include <Library/PeimEntryPoint.h>
  33 #include <Library/PeiServicesLib.h>
  34 #include <Library/QemuFwCfgLib.h>
  35 #include <Library/QemuFwCfgS3Lib.h>
  36 #include <Library/ResourcePublicationLib.h>
  37 #include <Guid/MemoryTypeInformation.h>
  38 #include <Ppi/MasterBootMode.h>
  39 #include <IndustryStandard/Pci22.h>
  40 #include <OvmfPlatforms.h>
  41
  42 #include "Platform.h"
  43 #include "Cmos.h"
  44
  45 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  46   { EfiACPIMemoryNVS,       0x004 },
  47   { EfiACPIReclaimMemory,   0x008 },
  48   { EfiReservedMemoryType,  0x004 },
  49   { EfiRuntimeServicesData, 0x024 },
  50   { EfiRuntimeServicesCode, 0x030 },
  51   { EfiBootServicesCode,    0x180 },
  52   { EfiBootServicesData,    0xF00 },
  53   { EfiMaxMemoryType,       0x000 }
  54 };
  55
  56
  57 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  58   {
  59     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  60     &gEfiPeiMasterBootModePpiGuid,
  61     NULL
  62   }
  63 };
  64
  65
  66 UINT16 mHostBridgeDevId;
  67
  68 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  69
  70 BOOLEAN mS3Supported = FALSE;
  71
  72 UINT32 mMaxCpuCount;
  73
  74 VOID
  75 AddIoMemoryBaseSizeHob (
  76   EFI_PHYSICAL_ADDRESS        MemoryBase,
  77   UINT64                      MemorySize
  78   )
  79 {
  80   BuildResourceDescriptorHob (
  81     EFI_RESOURCE_MEMORY_MAPPED_IO,
  82       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  83       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  84       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  85       EFI_RESOURCE_ATTRIBUTE_TESTED,
  86     MemoryBase,
  87     MemorySize
  88     );
  89 }
  90
  91 VOID
  92 AddReservedMemoryBaseSizeHob (
  93   EFI_PHYSICAL_ADDRESS        MemoryBase,
  94   UINT64                      MemorySize,
  95   BOOLEAN                     Cacheable
  96   )
  97 {
  98   BuildResourceDescriptorHob (
  99     EFI_RESOURCE_MEMORY_RESERVED,
 100       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 101       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 102       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 103       (Cacheable ?
 104        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 105        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 106        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
 107        0
 108        ) |
 109       EFI_RESOURCE_ATTRIBUTE_TESTED,
 110     MemoryBase,
 111     MemorySize
 112     );
 113 }
 114
 115 VOID
 116 AddIoMemoryRangeHob (
 117   EFI_PHYSICAL_ADDRESS        MemoryBase,
 118   EFI_PHYSICAL_ADDRESS        MemoryLimit
 119   )
 120 {
 121   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 122 }
 123
 124
 125 VOID
 126 AddMemoryBaseSizeHob (
 127   EFI_PHYSICAL_ADDRESS        MemoryBase,
 128   UINT64                      MemorySize
 129   )
 130 {
 131   BuildResourceDescriptorHob (
 132     EFI_RESOURCE_SYSTEM_MEMORY,
 133       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 134       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 135       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 136       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 137       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 138       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 139       EFI_RESOURCE_ATTRIBUTE_TESTED,
 140     MemoryBase,
 141     MemorySize
 142     );
 143 }
 144
 145
 146 VOID
 147 AddMemoryRangeHob (
 148   EFI_PHYSICAL_ADDRESS        MemoryBase,
 149   EFI_PHYSICAL_ADDRESS        MemoryLimit
 150   )
 151 {
 152   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 153 }
 154
 155
 156 VOID
 157 MemMapInitialization (
 158   VOID
 159   )
 160 {
 161   UINT64        PciIoBase;
 162   UINT64        PciIoSize;
 163   RETURN_STATUS PcdStatus;
 164
 165   PciIoBase = 0xC000;
 166   PciIoSize = 0x4000;
 167
 168   //
 169   // Create Memory Type Information HOB
 170   //
 171   BuildGuidDataHob (
 172     &gEfiMemoryTypeInformationGuid,
 173     mDefaultMemoryTypeInformation,
 174     sizeof(mDefaultMemoryTypeInformation)
 175     );
 176
 177   //
 178   // Video memory + Legacy BIOS region
 179   //
 180   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 181
 182   if (!mXen) {
 183     UINT32  TopOfLowRam;
 184     UINT64  PciExBarBase;
 185     UINT32  PciBase;
 186     UINT32  PciSize;
 187
 188     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 189     PciExBarBase = 0;
 190     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 191       //
 192       // The MMCONFIG area is expected to fall between the top of low RAM and
 193       // the base of the 32-bit PCI host aperture.
 194       //
 195       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
 196       ASSERT (TopOfLowRam <= PciExBarBase);
 197       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
 198       PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
 199     } else {
 200       PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
 201     }
 202
 203     //
 204     // address       purpose   size
 205     // ------------  --------  -------------------------
 206     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 207     // 0xFC000000    gap                           44 MB
 208     // 0xFEC00000    IO-APIC                        4 KB
 209     // 0xFEC01000    gap                         1020 KB
 210     // 0xFED00000    HPET                           1 KB
 211     // 0xFED00400    gap                          111 KB
 212     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 213     // 0xFED20000    gap                          896 KB
 214     // 0xFEE00000    LAPIC                          1 MB
 215     //
 216     PciSize = 0xFC000000 - PciBase;
 217     AddIoMemoryBaseSizeHob (PciBase, PciSize);
 218     PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);
 219     ASSERT_RETURN_ERROR (PcdStatus);
 220     PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);
 221     ASSERT_RETURN_ERROR (PcdStatus);
 222
 223     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 224     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 225     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 226       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 227       //
 228       // Note: there should be an
 229       //
 230       //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
 231       //
 232       // call below, just like the one above for RCBA. However, Linux insists
 233       // that the MMCONFIG area be marked in the E820 or UEFI memory map as
 234       // "reserved memory" -- Linux does not content itself with a simple gap
 235       // in the memory map wherever the MCFG ACPI table points to.
 236       //
 237       // This appears to be a safety measure. The PCI Firmware Specification
 238       // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
 239       // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
 240       // [...]". (Emphasis added here.)
 241       //
 242       // Normally we add memory resource descriptor HOBs in
 243       // QemuInitializeRam(), and pre-allocate from those with memory
 244       // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
 245       // is most definitely not RAM; so, as an exception, cover it with
 246       // uncacheable reserved memory right here.
 247       //
 248       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
 249       BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
 250         EfiReservedMemoryType);
 251     }
 252     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 253
 254     //
 255     // On Q35, the IO Port space is available for PCI resource allocations from
 256     // 0x6000 up.
 257     //
 258     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 259       PciIoBase = 0x6000;
 260       PciIoSize = 0xA000;
 261       ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
 262     }
 263   }
 264
 265   //
 266   // Add PCI IO Port space available for PCI resource allocations.
 267   //
 268   BuildResourceDescriptorHob (
 269     EFI_RESOURCE_IO,
 270     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 271     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 272     PciIoBase,
 273     PciIoSize
 274     );
 275   PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);
 276   ASSERT_RETURN_ERROR (PcdStatus);
 277   PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);
 278   ASSERT_RETURN_ERROR (PcdStatus);
 279 }
 280
 281 EFI_STATUS
 282 GetNamedFwCfgBoolean (
 283   IN  CHAR8   *FwCfgFileName,
 284   OUT BOOLEAN *Setting
 285   )
 286 {
 287   EFI_STATUS           Status;
 288   FIRMWARE_CONFIG_ITEM FwCfgItem;
 289   UINTN                FwCfgSize;
 290   UINT8                Value[3];
 291
 292   Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);
 293   if (EFI_ERROR (Status)) {
 294     return Status;
 295   }
 296   if (FwCfgSize > sizeof Value) {
 297     return EFI_BAD_BUFFER_SIZE;
 298   }
 299   QemuFwCfgSelectItem (FwCfgItem);
 300   QemuFwCfgReadBytes (FwCfgSize, Value);
 301
 302   if ((FwCfgSize == 1) ||
 303       (FwCfgSize == 2 && Value[1] == '\n') ||
 304       (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {
 305     switch (Value[0]) {
 306       case '0':
 307       case 'n':
 308       case 'N':
 309         *Setting = FALSE;
 310         return EFI_SUCCESS;
 311
 312       case '1':
 313       case 'y':
 314       case 'Y':
 315         *Setting = TRUE;
 316         return EFI_SUCCESS;
 317
 318       default:
 319         break;
 320     }
 321   }
 322   return EFI_PROTOCOL_ERROR;
 323 }
 324
 325 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \
 326           do {                                                      \
 327             BOOLEAN       Setting;                                  \
 328             RETURN_STATUS PcdStatus;                                \
 329                                                                     \
 330             if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \
 331                               "opt/ovmf/" #TokenName, &Setting))) { \
 332               PcdStatus = PcdSetBoolS (TokenName, Setting);         \
 333               ASSERT_RETURN_ERROR (PcdStatus);                      \
 334             }                                                       \
 335           } while (0)
 336
 337 VOID
 338 NoexecDxeInitialization (
 339   VOID
 340   )
 341 {
 342   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);
 343   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
 344 }
 345
 346 VOID
 347 PciExBarInitialization (
 348   VOID
 349   )
 350 {
 351   union {
 352     UINT64 Uint64;
 353     UINT32 Uint32[2];
 354   } PciExBarBase;
 355
 356   //
 357   // We only support the 256MB size for the MMCONFIG area:
 358   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 359   //
 360   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 361   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 362   //
 363   // Note that (b) also ensures that the minimum address width we have
 364   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 365   // for DXE's page tables to cover the MMCONFIG area.
 366   //
 367   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 368   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 369   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 370
 371   //
 372   // Clear the PCIEXBAREN bit first, before programming the high register.
 373   //
 374   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 375
 376   //
 377   // Program the high register. Then program the low register, setting the
 378   // MMCONFIG area size and enabling decoding at once.
 379   //
 380   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 381   PciWrite32 (
 382     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 383     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 384     );
 385 }
 386
 387 VOID
 388 MiscInitialization (
 389   VOID
 390   )
 391 {
 392   UINTN         PmCmd;
 393   UINTN         Pmba;
 394   UINT32        PmbaAndVal;
 395   UINT32        PmbaOrVal;
 396   UINTN         AcpiCtlReg;
 397   UINT8         AcpiEnBit;
 398   RETURN_STATUS PcdStatus;
 399
 400   //
 401   // Disable A20 Mask
 402   //
 403   IoOr8 (0x92, BIT1);
 404
 405   //
 406   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 407   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 408   // S3 resume as well, so we build it unconditionally.)
 409   //
 410   BuildCpuHob (mPhysMemAddressWidth, 16);
 411
 412   //
 413   // Determine platform type and save Host Bridge DID to PCD
 414   //
 415   switch (mHostBridgeDevId) {
 416     case INTEL_82441_DEVICE_ID:
 417       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 418       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 419       PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
 420       PmbaOrVal  = PIIX4_PMBA_VALUE;
 421       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 422       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 423       break;
 424     case INTEL_Q35_MCH_DEVICE_ID:
 425       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 426       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 427       PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
 428       PmbaOrVal  = ICH9_PMBASE_VALUE;
 429       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 430       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 431       break;
 432     default:
 433       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 434         __FUNCTION__, mHostBridgeDevId));
 435       ASSERT (FALSE);
 436       return;
 437   }
 438   PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 439   ASSERT_RETURN_ERROR (PcdStatus);
 440
 441   //
 442   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 443   // has been configured (e.g., by Xen) and skip the setup here.
 444   // This matches the logic in AcpiTimerLibConstructor ().
 445   //
 446   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 447     //
 448     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 449     // 1. set PMBA
 450     //
 451     PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 452
 453     //
 454     // 2. set PCICMD/IOSE
 455     //
 456     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 457
 458     //
 459     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 460     //
 461     PciOr8 (AcpiCtlReg, AcpiEnBit);
 462   }
 463
 464   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 465     //
 466     // Set Root Complex Register Block BAR
 467     //
 468     PciWrite32 (
 469       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 470       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 471       );
 472
 473     //
 474     // Set PCI Express Register Range Base Address
 475     //
 476     PciExBarInitialization ();
 477   }
 478 }
 479
 480
 481 VOID
 482 BootModeInitialization (
 483   VOID
 484   )
 485 {
 486   EFI_STATUS    Status;
 487
 488   if (CmosRead8 (0xF) == 0xFE) {
 489     mBootMode = BOOT_ON_S3_RESUME;
 490   }
 491   CmosWrite8 (0xF, 0x00);
 492
 493   Status = PeiServicesSetBootMode (mBootMode);
 494   ASSERT_EFI_ERROR (Status);
 495
 496   Status = PeiServicesInstallPpi (mPpiBootMode);
 497   ASSERT_EFI_ERROR (Status);
 498 }
 499
 500
 501 VOID
 502 ReserveEmuVariableNvStore (
 503   )
 504 {
 505   EFI_PHYSICAL_ADDRESS VariableStore;
 506   RETURN_STATUS        PcdStatus;
 507   UINT32               Alignment;
 508
 509   //
 510   // Allocate storage for NV variables early on so it will be
 511   // at a consistent address.  Since VM memory is preserved
 512   // across reboots, this allows the NV variable storage to survive
 513   // a VM reboot.
 514   //
 515   Alignment = PcdGet32 (PcdFlashNvStorageFtwSpareSize);
 516   if ((Alignment & (Alignment - 1)) != 0) {
 517     //
 518     // Round up Alignment to the next power of two.
 519     //
 520     Alignment = GetPowerOfTwo32 (Alignment) << 1;
 521   }
 522
 523   VariableStore =
 524     (EFI_PHYSICAL_ADDRESS)(UINTN)
 525       AllocateAlignedRuntimePages (
 526         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
 527         Alignment
 528         );
 529   DEBUG ((EFI_D_INFO,
 530           "Reserved variable store memory: 0x%lX; size: %dkb, "
 531           "alignment: 0x%x\n",
 532           VariableStore,
 533           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024,
 534           Alignment
 535         ));
 536   PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
 537   ASSERT_RETURN_ERROR (PcdStatus);
 538 }
 539
 540
 541 VOID
 542 DebugDumpCmos (
 543   VOID
 544   )
 545 {
 546   UINT32 Loop;
 547
 548   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 549
 550   for (Loop = 0; Loop < 0x80; Loop++) {
 551     if ((Loop % 0x10) == 0) {
 552       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 553     }
 554     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 555     if ((Loop % 0x10) == 0xf) {
 556       DEBUG ((EFI_D_INFO, "\n"));
 557     }
 558   }
 559 }
 560
 561
 562 VOID
 563 S3Verification (
 564   VOID
 565   )
 566 {
 567 #if defined (MDE_CPU_X64)
 568   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
 569     DEBUG ((EFI_D_ERROR,
 570       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
 571     DEBUG ((EFI_D_ERROR,
 572       "%a: Please disable S3 on the QEMU command line (see the README),\n",
 573       __FUNCTION__));
 574     DEBUG ((EFI_D_ERROR,
 575       "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
 576     ASSERT (FALSE);
 577     CpuDeadLoop ();
 578   }
 579 #endif
 580 }
 581
 582
 583 /**
 584   Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.
 585   Set the mMaxCpuCount variable.
 586 **/
 587 VOID
 588 MaxCpuCountInitialization (
 589   VOID
 590   )
 591 {
 592   UINT16        ProcessorCount;
 593   RETURN_STATUS PcdStatus;
 594
 595   QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);
 596   ProcessorCount = QemuFwCfgRead16 ();
 597   //
 598   // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount
 599   // from the PCD default. No change to PCDs.
 600   //
 601   if (ProcessorCount == 0) {
 602     mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
 603     return;
 604   }
 605   //
 606   // Otherwise, set mMaxCpuCount to the value reported by QEMU.
 607   //
 608   mMaxCpuCount = ProcessorCount;
 609   //
 610   // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)
 611   // to wait, in the initial AP bringup, exactly as long as it takes for all of
 612   // the APs to report in. For this, we set the longest representable timeout
 613   // (approx. 71 minutes).
 614   //
 615   PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);
 616   ASSERT_RETURN_ERROR (PcdStatus);
 617   PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);
 618   ASSERT_RETURN_ERROR (PcdStatus);
 619   DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,
 620     ProcessorCount));
 621 }
 622
 623
 624 /**
 625   Perform Platform PEI initialization.
 626
 627   @param  FileHandle      Handle of the file being invoked.
 628   @param  PeiServices     Describes the list of possible PEI Services.
 629
 630   @return EFI_SUCCESS     The PEIM initialized successfully.
 631
 632 **/
 633 EFI_STATUS
 634 EFIAPI
 635 InitializePlatform (
 636   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 637   IN CONST EFI_PEI_SERVICES     **PeiServices
 638   )
 639 {
 640   EFI_STATUS    Status;
 641
 642   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
 643
 644   DebugDumpCmos ();
 645
 646   XenDetect ();
 647
 648   if (QemuFwCfgS3Enabled ()) {
 649     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
 650     mS3Supported = TRUE;
 651     Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
 652     ASSERT_EFI_ERROR (Status);
 653   }
 654
 655   S3Verification ();
 656   BootModeInitialization ();
 657   AddressWidthInitialization ();
 658   MaxCpuCountInitialization ();
 659
 660   PublishPeiMemory ();
 661
 662   InitializeRamRegions ();
 663
 664   if (mXen) {
 665     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 666     InitializeXen ();
 667   }
 668
 669   //
 670   // Query Host Bridge DID
 671   //
 672   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 673
 674   if (mBootMode != BOOT_ON_S3_RESUME) {
 675     ReserveEmuVariableNvStore ();
 676     PeiFvInitialization ();
 677     MemMapInitialization ();
 678     NoexecDxeInitialization ();
 679   }
 680
 681   MiscInitialization ();
 682   InstallFeatureControlCallback ();
 683
 684   return EFI_SUCCESS;
 685 }