4 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 // The package level header files this module uses
23 // The Library classes this module consumes
25 #include <Library/DebugLib.h>
26 #include <Library/HobLib.h>
27 #include <Library/IoLib.h>
28 #include <Library/MemoryAllocationLib.h>
29 #include <Library/PcdLib.h>
30 #include <Library/PciLib.h>
31 #include <Library/PeimEntryPoint.h>
32 #include <Library/PeiServicesLib.h>
33 #include <Library/ResourcePublicationLib.h>
34 #include <Guid/MemoryTypeInformation.h>
35 #include <Ppi/MasterBootMode.h>
36 #include <IndustryStandard/Pci22.h>
41 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation
[] = {
42 { EfiACPIMemoryNVS
, 0x004 },
43 { EfiACPIReclaimMemory
, 0x008 },
44 { EfiReservedMemoryType
, 0x004 },
45 { EfiRuntimeServicesData
, 0x024 },
46 { EfiRuntimeServicesCode
, 0x030 },
47 { EfiBootServicesCode
, 0x180 },
48 { EfiBootServicesData
, 0xF00 },
49 { EfiMaxMemoryType
, 0x000 }
53 EFI_PEI_PPI_DESCRIPTOR mPpiBootMode
[] = {
55 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
56 &gEfiPeiMasterBootModePpiGuid
,
63 AddIoMemoryBaseSizeHob (
64 EFI_PHYSICAL_ADDRESS MemoryBase
,
68 BuildResourceDescriptorHob (
69 EFI_RESOURCE_MEMORY_MAPPED_IO
,
70 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
71 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
72 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
73 EFI_RESOURCE_ATTRIBUTE_TESTED
,
80 AddReservedMemoryBaseSizeHob (
81 EFI_PHYSICAL_ADDRESS MemoryBase
,
85 BuildResourceDescriptorHob (
86 EFI_RESOURCE_MEMORY_RESERVED
,
87 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
88 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
89 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
90 EFI_RESOURCE_ATTRIBUTE_TESTED
,
98 EFI_PHYSICAL_ADDRESS MemoryBase
,
99 EFI_PHYSICAL_ADDRESS MemoryLimit
102 AddIoMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
107 AddMemoryBaseSizeHob (
108 EFI_PHYSICAL_ADDRESS MemoryBase
,
112 BuildResourceDescriptorHob (
113 EFI_RESOURCE_SYSTEM_MEMORY
,
114 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
115 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
116 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
117 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
118 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
119 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
|
120 EFI_RESOURCE_ATTRIBUTE_TESTED
,
129 EFI_PHYSICAL_ADDRESS MemoryBase
,
130 EFI_PHYSICAL_ADDRESS MemoryLimit
133 AddMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
138 AddUntestedMemoryBaseSizeHob (
139 EFI_PHYSICAL_ADDRESS MemoryBase
,
143 BuildResourceDescriptorHob (
144 EFI_RESOURCE_SYSTEM_MEMORY
,
145 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
146 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
147 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
148 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
149 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
150 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
,
158 AddUntestedMemoryRangeHob (
159 EFI_PHYSICAL_ADDRESS MemoryBase
,
160 EFI_PHYSICAL_ADDRESS MemoryLimit
163 AddUntestedMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
167 XenMemMapInitialization (
172 // Create Memory Type Information HOB
175 &gEfiMemoryTypeInformationGuid
,
176 mDefaultMemoryTypeInformation
,
177 sizeof(mDefaultMemoryTypeInformation
)
181 // Add PCI IO Port space available for PCI resource allocations.
183 BuildResourceDescriptorHob (
185 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
186 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
,
192 // Video memory + Legacy BIOS region
194 AddIoMemoryRangeHob (0x0A0000, BASE_1MB
);
196 XenPublishRamRegions ();
201 MemMapInitialization (
202 EFI_PHYSICAL_ADDRESS TopOfMemory
206 // Create Memory Type Information HOB
209 &gEfiMemoryTypeInformationGuid
,
210 mDefaultMemoryTypeInformation
,
211 sizeof(mDefaultMemoryTypeInformation
)
215 // Add PCI IO Port space available for PCI resource allocations.
217 BuildResourceDescriptorHob (
219 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
220 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
,
226 // Video memory + Legacy BIOS region
228 AddIoMemoryRangeHob (0x0A0000, BASE_1MB
);
231 // address purpose size
232 // ------------ -------- -------------------------
233 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
234 // 0xFC000000 gap 44 MB
235 // 0xFEC00000 IO-APIC 4 KB
236 // 0xFEC01000 gap 1020 KB
237 // 0xFED00000 HPET 1 KB
238 // 0xFED00400 gap 1023 KB
239 // 0xFEE00000 LAPIC 1 MB
241 AddIoMemoryRangeHob (TopOfMemory
< BASE_2GB
? BASE_2GB
: TopOfMemory
, 0xFC000000);
242 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB
);
243 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB
);
244 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress
), SIZE_1MB
);
259 // Build the CPU hob with 36-bit addressing and 16-bits of IO space.
261 BuildCpuHob (36, 16);
264 // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for
265 // example by Xen) and skip the setup here. This matches the logic in
266 // AcpiTimerLibConstructor ().
268 if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {
270 // The PEI phase should be exited with fully accessibe PIIX4 IO space:
274 PCI_LIB_ADDRESS (0, 1, 3, 0x40),
276 PcdGet16 (PcdAcpiPmBaseAddress
)
280 // 2. set PCICMD/IOSE
283 PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET
),
284 EFI_PCI_COMMAND_IO_SPACE
288 // 3. set PMREGMISC/PMIOSE
290 PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);
296 BootModeInitialization (
301 Status
= PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION
);
302 ASSERT_EFI_ERROR (Status
);
304 Status
= PeiServicesInstallPpi (mPpiBootMode
);
305 ASSERT_EFI_ERROR (Status
);
310 ReserveEmuVariableNvStore (
313 EFI_PHYSICAL_ADDRESS VariableStore
;
316 // Allocate storage for NV variables early on so it will be
317 // at a consistent address. Since VM memory is preserved
318 // across reboots, this allows the NV variable storage to survive
322 (EFI_PHYSICAL_ADDRESS
)(UINTN
)
323 AllocateAlignedRuntimePages (
324 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
)),
325 PcdGet32 (PcdFlashNvStorageFtwSpareSize
)
328 "Reserved variable store memory: 0x%lX; size: %dkb\n",
330 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
)) / 1024
332 PcdSet64 (PcdEmuVariableNvStoreReserved
, VariableStore
);
343 DEBUG ((EFI_D_INFO
, "CMOS:\n"));
345 for (Loop
= 0; Loop
< 0x80; Loop
++) {
346 if ((Loop
% 0x10) == 0) {
347 DEBUG ((EFI_D_INFO
, "%02x:", Loop
));
349 DEBUG ((EFI_D_INFO
, " %02x", CmosRead8 (Loop
)));
350 if ((Loop
% 0x10) == 0xf) {
351 DEBUG ((EFI_D_INFO
, "\n"));
358 Perform Platform PEI initialization.
360 @param FileHandle Handle of the file being invoked.
361 @param PeiServices Describes the list of possible PEI Services.
363 @return EFI_SUCCESS The PEIM initialized successfully.
369 IN EFI_PEI_FILE_HANDLE FileHandle
,
370 IN CONST EFI_PEI_SERVICES
**PeiServices
373 EFI_PHYSICAL_ADDRESS TopOfMemory
;
377 DEBUG ((EFI_D_ERROR
, "Platform PEIM Loaded\n"));
383 BootModeInitialization ();
388 PcdSetBool (PcdPciDisableBusEnumeration
, TRUE
);
390 TopOfMemory
= MemDetect ();
394 DEBUG ((EFI_D_INFO
, "Xen was detected\n"));
398 ReserveEmuVariableNvStore ();
400 PeiFvInitialization ();
403 XenMemMapInitialization ();
405 MemMapInitialization (TopOfMemory
);
408 MiscInitialization ();