]> git.proxmox.com Git - mirror_edk2.git/blob - OvmfPkg/PlatformPei/Platform.c
OvmfPkg: PlatformPei: detect S3 Resume in CMOS and set boot mode accordingly
[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c
1 /**@file
2 Platform PEI driver
3
4 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
6
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 //
18 // The package level header files this module uses
19 //
20 #include <PiPei.h>
21
22 //
23 // The Library classes this module consumes
24 //
25 #include <Library/DebugLib.h>
26 #include <Library/HobLib.h>
27 #include <Library/IoLib.h>
28 #include <Library/MemoryAllocationLib.h>
29 #include <Library/PcdLib.h>
30 #include <Library/PciLib.h>
31 #include <Library/PeimEntryPoint.h>
32 #include <Library/PeiServicesLib.h>
33 #include <Library/ResourcePublicationLib.h>
34 #include <Guid/MemoryTypeInformation.h>
35 #include <Ppi/MasterBootMode.h>
36 #include <IndustryStandard/Pci22.h>
37
38 #include "Platform.h"
39 #include "Cmos.h"
40
41 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
42 { EfiACPIMemoryNVS, 0x004 },
43 { EfiACPIReclaimMemory, 0x008 },
44 { EfiReservedMemoryType, 0x004 },
45 { EfiRuntimeServicesData, 0x024 },
46 { EfiRuntimeServicesCode, 0x030 },
47 { EfiBootServicesCode, 0x180 },
48 { EfiBootServicesData, 0xF00 },
49 { EfiMaxMemoryType, 0x000 }
50 };
51
52
53 EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
54 {
55 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
56 &gEfiPeiMasterBootModePpiGuid,
57 NULL
58 }
59 };
60
61
62 VOID
63 AddIoMemoryBaseSizeHob (
64 EFI_PHYSICAL_ADDRESS MemoryBase,
65 UINT64 MemorySize
66 )
67 {
68 BuildResourceDescriptorHob (
69 EFI_RESOURCE_MEMORY_MAPPED_IO,
70 EFI_RESOURCE_ATTRIBUTE_PRESENT |
71 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
72 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
73 EFI_RESOURCE_ATTRIBUTE_TESTED,
74 MemoryBase,
75 MemorySize
76 );
77 }
78
79 VOID
80 AddReservedMemoryBaseSizeHob (
81 EFI_PHYSICAL_ADDRESS MemoryBase,
82 UINT64 MemorySize
83 )
84 {
85 BuildResourceDescriptorHob (
86 EFI_RESOURCE_MEMORY_RESERVED,
87 EFI_RESOURCE_ATTRIBUTE_PRESENT |
88 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
89 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
90 EFI_RESOURCE_ATTRIBUTE_TESTED,
91 MemoryBase,
92 MemorySize
93 );
94 }
95
96 VOID
97 AddIoMemoryRangeHob (
98 EFI_PHYSICAL_ADDRESS MemoryBase,
99 EFI_PHYSICAL_ADDRESS MemoryLimit
100 )
101 {
102 AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
103 }
104
105
106 VOID
107 AddMemoryBaseSizeHob (
108 EFI_PHYSICAL_ADDRESS MemoryBase,
109 UINT64 MemorySize
110 )
111 {
112 BuildResourceDescriptorHob (
113 EFI_RESOURCE_SYSTEM_MEMORY,
114 EFI_RESOURCE_ATTRIBUTE_PRESENT |
115 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
116 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
117 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
118 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
119 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
120 EFI_RESOURCE_ATTRIBUTE_TESTED,
121 MemoryBase,
122 MemorySize
123 );
124 }
125
126
127 VOID
128 AddMemoryRangeHob (
129 EFI_PHYSICAL_ADDRESS MemoryBase,
130 EFI_PHYSICAL_ADDRESS MemoryLimit
131 )
132 {
133 AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
134 }
135
136
137 VOID
138 AddUntestedMemoryBaseSizeHob (
139 EFI_PHYSICAL_ADDRESS MemoryBase,
140 UINT64 MemorySize
141 )
142 {
143 BuildResourceDescriptorHob (
144 EFI_RESOURCE_SYSTEM_MEMORY,
145 EFI_RESOURCE_ATTRIBUTE_PRESENT |
146 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
147 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
148 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
149 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
150 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
151 MemoryBase,
152 MemorySize
153 );
154 }
155
156
157 VOID
158 AddUntestedMemoryRangeHob (
159 EFI_PHYSICAL_ADDRESS MemoryBase,
160 EFI_PHYSICAL_ADDRESS MemoryLimit
161 )
162 {
163 AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
164 }
165
166 VOID
167 MemMapInitialization (
168 VOID
169 )
170 {
171 //
172 // Create Memory Type Information HOB
173 //
174 BuildGuidDataHob (
175 &gEfiMemoryTypeInformationGuid,
176 mDefaultMemoryTypeInformation,
177 sizeof(mDefaultMemoryTypeInformation)
178 );
179
180 //
181 // Add PCI IO Port space available for PCI resource allocations.
182 //
183 BuildResourceDescriptorHob (
184 EFI_RESOURCE_IO,
185 EFI_RESOURCE_ATTRIBUTE_PRESENT |
186 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
187 0xC000,
188 0x4000
189 );
190
191 //
192 // Video memory + Legacy BIOS region
193 //
194 AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
195
196 if (!mXen) {
197 UINT32 TopOfLowRam;
198 TopOfLowRam = GetSystemMemorySizeBelow4gb ();
199
200 //
201 // address purpose size
202 // ------------ -------- -------------------------
203 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
204 // 0xFC000000 gap 44 MB
205 // 0xFEC00000 IO-APIC 4 KB
206 // 0xFEC01000 gap 1020 KB
207 // 0xFED00000 HPET 1 KB
208 // 0xFED00400 gap 1023 KB
209 // 0xFEE00000 LAPIC 1 MB
210 //
211 AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?
212 BASE_2GB : TopOfLowRam, 0xFC000000);
213 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
214 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
215 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
216 }
217 }
218
219
220 VOID
221 MiscInitialization (
222 VOID
223 )
224 {
225 //
226 // Disable A20 Mask
227 //
228 IoOr8 (0x92, BIT1);
229
230 //
231 // Build the CPU hob with 36-bit addressing and 16-bits of IO space.
232 //
233 BuildCpuHob (36, 16);
234
235 //
236 // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for
237 // example by Xen) and skip the setup here. This matches the logic in
238 // AcpiTimerLibConstructor ().
239 //
240 if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {
241 //
242 // The PEI phase should be exited with fully accessibe PIIX4 IO space:
243 // 1. set PMBA
244 //
245 PciAndThenOr32 (
246 PCI_LIB_ADDRESS (0, 1, 3, 0x40),
247 (UINT32) ~0xFFC0,
248 PcdGet16 (PcdAcpiPmBaseAddress)
249 );
250
251 //
252 // 2. set PCICMD/IOSE
253 //
254 PciOr8 (
255 PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),
256 EFI_PCI_COMMAND_IO_SPACE
257 );
258
259 //
260 // 3. set PMREGMISC/PMIOSE
261 //
262 PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);
263 }
264 }
265
266
267 VOID
268 BootModeInitialization (
269 VOID
270 )
271 {
272 EFI_BOOT_MODE BootMode;
273 EFI_STATUS Status;
274
275 if (CmosRead8 (0xF) == 0xFE) {
276 BootMode = BOOT_ON_S3_RESUME;
277 } else {
278 BootMode = BOOT_WITH_FULL_CONFIGURATION;
279 }
280
281 Status = PeiServicesSetBootMode (BootMode);
282 ASSERT_EFI_ERROR (Status);
283
284 Status = PeiServicesInstallPpi (mPpiBootMode);
285 ASSERT_EFI_ERROR (Status);
286 }
287
288
289 VOID
290 ReserveEmuVariableNvStore (
291 )
292 {
293 EFI_PHYSICAL_ADDRESS VariableStore;
294
295 //
296 // Allocate storage for NV variables early on so it will be
297 // at a consistent address. Since VM memory is preserved
298 // across reboots, this allows the NV variable storage to survive
299 // a VM reboot.
300 //
301 VariableStore =
302 (EFI_PHYSICAL_ADDRESS)(UINTN)
303 AllocateAlignedRuntimePages (
304 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
305 PcdGet32 (PcdFlashNvStorageFtwSpareSize)
306 );
307 DEBUG ((EFI_D_INFO,
308 "Reserved variable store memory: 0x%lX; size: %dkb\n",
309 VariableStore,
310 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
311 ));
312 PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
313 }
314
315
316 VOID
317 DebugDumpCmos (
318 VOID
319 )
320 {
321 UINTN Loop;
322
323 DEBUG ((EFI_D_INFO, "CMOS:\n"));
324
325 for (Loop = 0; Loop < 0x80; Loop++) {
326 if ((Loop % 0x10) == 0) {
327 DEBUG ((EFI_D_INFO, "%02x:", Loop));
328 }
329 DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
330 if ((Loop % 0x10) == 0xf) {
331 DEBUG ((EFI_D_INFO, "\n"));
332 }
333 }
334 }
335
336
337 /**
338 Perform Platform PEI initialization.
339
340 @param FileHandle Handle of the file being invoked.
341 @param PeiServices Describes the list of possible PEI Services.
342
343 @return EFI_SUCCESS The PEIM initialized successfully.
344
345 **/
346 EFI_STATUS
347 EFIAPI
348 InitializePlatform (
349 IN EFI_PEI_FILE_HANDLE FileHandle,
350 IN CONST EFI_PEI_SERVICES **PeiServices
351 )
352 {
353 DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
354
355 DebugDumpCmos ();
356
357 XenDetect ();
358
359 BootModeInitialization ();
360
361 PublishPeiMemory ();
362
363 InitializeRamRegions ();
364
365 if (mXen) {
366 DEBUG ((EFI_D_INFO, "Xen was detected\n"));
367 InitializeXen ();
368 }
369
370 ReserveEmuVariableNvStore ();
371
372 PeiFvInitialization ();
373
374 MemMapInitialization ();
375
376 MiscInitialization ();
377
378 return EFI_SUCCESS;
379 }