OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 //
  12 // The package level header files this module uses
  13 //
  14 #include <PiPei.h>
  15
  16 //
  17 // The Library classes this module consumes
  18 //
  19 #include <Library/BaseLib.h>
  20 #include <Library/DebugLib.h>
  21 #include <Library/HobLib.h>
  22 #include <Library/IoLib.h>
  23 #include <Library/MemoryAllocationLib.h>
  24 #include <Library/PcdLib.h>
  25 #include <Library/PciLib.h>
  26 #include <Library/PeimEntryPoint.h>
  27 #include <Library/PeiServicesLib.h>
  28 #include <Library/QemuFwCfgLib.h>
  29 #include <Library/QemuFwCfgS3Lib.h>
  30 #include <Library/ResourcePublicationLib.h>
  31 #include <Guid/MemoryTypeInformation.h>
  32 #include <Ppi/MasterBootMode.h>
  33 #include <IndustryStandard/Pci22.h>
  34 #include <OvmfPlatforms.h>
  35
  36 #include "Platform.h"
  37 #include "Cmos.h"
  38
  39 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  40   { EfiACPIMemoryNVS,       0x004 },
  41   { EfiACPIReclaimMemory,   0x008 },
  42   { EfiReservedMemoryType,  0x004 },
  43   { EfiRuntimeServicesData, 0x024 },
  44   { EfiRuntimeServicesCode, 0x030 },
  45   { EfiBootServicesCode,    0x180 },
  46   { EfiBootServicesData,    0xF00 },
  47   { EfiMaxMemoryType,       0x000 }
  48 };
  49
  50
  51 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  52   {
  53     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  54     &gEfiPeiMasterBootModePpiGuid,
  55     NULL
  56   }
  57 };
  58
  59
  60 UINT16 mHostBridgeDevId;
  61
  62 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  63
  64 BOOLEAN mS3Supported = FALSE;
  65
  66 UINT32 mMaxCpuCount;
  67
  68 VOID
  69 AddIoMemoryBaseSizeHob (
  70   EFI_PHYSICAL_ADDRESS        MemoryBase,
  71   UINT64                      MemorySize
  72   )
  73 {
  74   BuildResourceDescriptorHob (
  75     EFI_RESOURCE_MEMORY_MAPPED_IO,
  76       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  77       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  78       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  79       EFI_RESOURCE_ATTRIBUTE_TESTED,
  80     MemoryBase,
  81     MemorySize
  82     );
  83 }
  84
  85 VOID
  86 AddReservedMemoryBaseSizeHob (
  87   EFI_PHYSICAL_ADDRESS        MemoryBase,
  88   UINT64                      MemorySize,
  89   BOOLEAN                     Cacheable
  90   )
  91 {
  92   BuildResourceDescriptorHob (
  93     EFI_RESOURCE_MEMORY_RESERVED,
  94       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  95       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  96       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  97       (Cacheable ?
  98        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
  99        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 100        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
 101        0
 102        ) |
 103       EFI_RESOURCE_ATTRIBUTE_TESTED,
 104     MemoryBase,
 105     MemorySize
 106     );
 107 }
 108
 109 VOID
 110 AddIoMemoryRangeHob (
 111   EFI_PHYSICAL_ADDRESS        MemoryBase,
 112   EFI_PHYSICAL_ADDRESS        MemoryLimit
 113   )
 114 {
 115   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 116 }
 117
 118
 119 VOID
 120 AddMemoryBaseSizeHob (
 121   EFI_PHYSICAL_ADDRESS        MemoryBase,
 122   UINT64                      MemorySize
 123   )
 124 {
 125   BuildResourceDescriptorHob (
 126     EFI_RESOURCE_SYSTEM_MEMORY,
 127       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 128       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 129       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 130       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 131       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 132       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 133       EFI_RESOURCE_ATTRIBUTE_TESTED,
 134     MemoryBase,
 135     MemorySize
 136     );
 137 }
 138
 139
 140 VOID
 141 AddMemoryRangeHob (
 142   EFI_PHYSICAL_ADDRESS        MemoryBase,
 143   EFI_PHYSICAL_ADDRESS        MemoryLimit
 144   )
 145 {
 146   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 147 }
 148
 149
 150 VOID
 151 MemMapInitialization (
 152   VOID
 153   )
 154 {
 155   UINT64        PciIoBase;
 156   UINT64        PciIoSize;
 157   RETURN_STATUS PcdStatus;
 158
 159   PciIoBase = 0xC000;
 160   PciIoSize = 0x4000;
 161
 162   //
 163   // Create Memory Type Information HOB
 164   //
 165   BuildGuidDataHob (
 166     &gEfiMemoryTypeInformationGuid,
 167     mDefaultMemoryTypeInformation,
 168     sizeof(mDefaultMemoryTypeInformation)
 169     );
 170
 171   //
 172   // Video memory + Legacy BIOS region
 173   //
 174   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 175
 176   if (!mXen) {
 177     UINT32  TopOfLowRam;
 178     UINT64  PciExBarBase;
 179     UINT32  PciBase;
 180     UINT32  PciSize;
 181
 182     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 183     PciExBarBase = 0;
 184     PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
 185     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 186       //
 187       // The 32-bit PCI host aperture is expected to fall between the top of
 188       // low RAM and the base of the MMCONFIG area.
 189       //
 190       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
 191       ASSERT (PciBase < PciExBarBase);
 192       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
 193       PciSize = (UINT32)(PciExBarBase - PciBase);
 194     } else {
 195       PciSize = 0xFC000000 - PciBase;
 196     }
 197
 198     //
 199     // address       purpose   size
 200     // ------------  --------  -------------------------
 201     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 202     // 0xFC000000    gap                           44 MB
 203     // 0xFEC00000    IO-APIC                        4 KB
 204     // 0xFEC01000    gap                         1020 KB
 205     // 0xFED00000    HPET                           1 KB
 206     // 0xFED00400    gap                          111 KB
 207     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 208     // 0xFED20000    gap                          896 KB
 209     // 0xFEE00000    LAPIC                          1 MB
 210     //
 211     AddIoMemoryBaseSizeHob (PciBase, PciSize);
 212     PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);
 213     ASSERT_RETURN_ERROR (PcdStatus);
 214     PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);
 215     ASSERT_RETURN_ERROR (PcdStatus);
 216
 217     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 218     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 219     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 220       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 221       //
 222       // Note: there should be an
 223       //
 224       //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
 225       //
 226       // call below, just like the one above for RCBA. However, Linux insists
 227       // that the MMCONFIG area be marked in the E820 or UEFI memory map as
 228       // "reserved memory" -- Linux does not content itself with a simple gap
 229       // in the memory map wherever the MCFG ACPI table points to.
 230       //
 231       // This appears to be a safety measure. The PCI Firmware Specification
 232       // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
 233       // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
 234       // [...]". (Emphasis added here.)
 235       //
 236       // Normally we add memory resource descriptor HOBs in
 237       // QemuInitializeRam(), and pre-allocate from those with memory
 238       // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
 239       // is most definitely not RAM; so, as an exception, cover it with
 240       // uncacheable reserved memory right here.
 241       //
 242       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
 243       BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
 244         EfiReservedMemoryType);
 245     }
 246     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 247
 248     //
 249     // On Q35, the IO Port space is available for PCI resource allocations from
 250     // 0x6000 up.
 251     //
 252     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 253       PciIoBase = 0x6000;
 254       PciIoSize = 0xA000;
 255       ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
 256     }
 257   }
 258
 259   //
 260   // Add PCI IO Port space available for PCI resource allocations.
 261   //
 262   BuildResourceDescriptorHob (
 263     EFI_RESOURCE_IO,
 264     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 265     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 266     PciIoBase,
 267     PciIoSize
 268     );
 269   PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);
 270   ASSERT_RETURN_ERROR (PcdStatus);
 271   PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);
 272   ASSERT_RETURN_ERROR (PcdStatus);
 273 }
 274
 275 EFI_STATUS
 276 GetNamedFwCfgBoolean (
 277   IN  CHAR8   *FwCfgFileName,
 278   OUT BOOLEAN *Setting
 279   )
 280 {
 281   EFI_STATUS           Status;
 282   FIRMWARE_CONFIG_ITEM FwCfgItem;
 283   UINTN                FwCfgSize;
 284   UINT8                Value[3];
 285
 286   Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);
 287   if (EFI_ERROR (Status)) {
 288     return Status;
 289   }
 290   if (FwCfgSize > sizeof Value) {
 291     return EFI_BAD_BUFFER_SIZE;
 292   }
 293   QemuFwCfgSelectItem (FwCfgItem);
 294   QemuFwCfgReadBytes (FwCfgSize, Value);
 295
 296   if ((FwCfgSize == 1) ||
 297       (FwCfgSize == 2 && Value[1] == '\n') ||
 298       (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {
 299     switch (Value[0]) {
 300       case '0':
 301       case 'n':
 302       case 'N':
 303         *Setting = FALSE;
 304         return EFI_SUCCESS;
 305
 306       case '1':
 307       case 'y':
 308       case 'Y':
 309         *Setting = TRUE;
 310         return EFI_SUCCESS;
 311
 312       default:
 313         break;
 314     }
 315   }
 316   return EFI_PROTOCOL_ERROR;
 317 }
 318
 319 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \
 320           do {                                                      \
 321             BOOLEAN       Setting;                                  \
 322             RETURN_STATUS PcdStatus;                                \
 323                                                                     \
 324             if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \
 325                               "opt/ovmf/" #TokenName, &Setting))) { \
 326               PcdStatus = PcdSetBoolS (TokenName, Setting);         \
 327               ASSERT_RETURN_ERROR (PcdStatus);                      \
 328             }                                                       \
 329           } while (0)
 330
 331 VOID
 332 NoexecDxeInitialization (
 333   VOID
 334   )
 335 {
 336   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);
 337   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
 338 }
 339
 340 VOID
 341 PciExBarInitialization (
 342   VOID
 343   )
 344 {
 345   union {
 346     UINT64 Uint64;
 347     UINT32 Uint32[2];
 348   } PciExBarBase;
 349
 350   //
 351   // We only support the 256MB size for the MMCONFIG area:
 352   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 353   //
 354   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 355   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 356   //
 357   // Note that (b) also ensures that the minimum address width we have
 358   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 359   // for DXE's page tables to cover the MMCONFIG area.
 360   //
 361   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 362   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 363   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 364
 365   //
 366   // Clear the PCIEXBAREN bit first, before programming the high register.
 367   //
 368   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 369
 370   //
 371   // Program the high register. Then program the low register, setting the
 372   // MMCONFIG area size and enabling decoding at once.
 373   //
 374   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 375   PciWrite32 (
 376     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 377     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 378     );
 379 }
 380
 381 VOID
 382 MiscInitialization (
 383   VOID
 384   )
 385 {
 386   UINTN         PmCmd;
 387   UINTN         Pmba;
 388   UINT32        PmbaAndVal;
 389   UINT32        PmbaOrVal;
 390   UINTN         AcpiCtlReg;
 391   UINT8         AcpiEnBit;
 392   RETURN_STATUS PcdStatus;
 393
 394   //
 395   // Disable A20 Mask
 396   //
 397   IoOr8 (0x92, BIT1);
 398
 399   //
 400   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 401   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 402   // S3 resume as well, so we build it unconditionally.)
 403   //
 404   BuildCpuHob (mPhysMemAddressWidth, 16);
 405
 406   //
 407   // Determine platform type and save Host Bridge DID to PCD
 408   //
 409   switch (mHostBridgeDevId) {
 410     case INTEL_82441_DEVICE_ID:
 411       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 412       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 413       PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
 414       PmbaOrVal  = PIIX4_PMBA_VALUE;
 415       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 416       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 417       break;
 418     case INTEL_Q35_MCH_DEVICE_ID:
 419       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 420       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 421       PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
 422       PmbaOrVal  = ICH9_PMBASE_VALUE;
 423       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 424       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 425       break;
 426     default:
 427       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 428         __FUNCTION__, mHostBridgeDevId));
 429       ASSERT (FALSE);
 430       return;
 431   }
 432   PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 433   ASSERT_RETURN_ERROR (PcdStatus);
 434
 435   //
 436   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 437   // has been configured (e.g., by Xen) and skip the setup here.
 438   // This matches the logic in AcpiTimerLibConstructor ().
 439   //
 440   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 441     //
 442     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 443     // 1. set PMBA
 444     //
 445     PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 446
 447     //
 448     // 2. set PCICMD/IOSE
 449     //
 450     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 451
 452     //
 453     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 454     //
 455     PciOr8 (AcpiCtlReg, AcpiEnBit);
 456   }
 457
 458   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 459     //
 460     // Set Root Complex Register Block BAR
 461     //
 462     PciWrite32 (
 463       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 464       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 465       );
 466
 467     //
 468     // Set PCI Express Register Range Base Address
 469     //
 470     PciExBarInitialization ();
 471   }
 472 }
 473
 474
 475 VOID
 476 BootModeInitialization (
 477   VOID
 478   )
 479 {
 480   EFI_STATUS    Status;
 481
 482   if (CmosRead8 (0xF) == 0xFE) {
 483     mBootMode = BOOT_ON_S3_RESUME;
 484   }
 485   CmosWrite8 (0xF, 0x00);
 486
 487   Status = PeiServicesSetBootMode (mBootMode);
 488   ASSERT_EFI_ERROR (Status);
 489
 490   Status = PeiServicesInstallPpi (mPpiBootMode);
 491   ASSERT_EFI_ERROR (Status);
 492 }
 493
 494
 495 VOID
 496 ReserveEmuVariableNvStore (
 497   )
 498 {
 499   EFI_PHYSICAL_ADDRESS VariableStore;
 500   RETURN_STATUS        PcdStatus;
 501
 502   //
 503   // Allocate storage for NV variables early on so it will be
 504   // at a consistent address.  Since VM memory is preserved
 505   // across reboots, this allows the NV variable storage to survive
 506   // a VM reboot.
 507   //
 508   VariableStore =
 509     (EFI_PHYSICAL_ADDRESS)(UINTN)
 510       AllocateRuntimePages (
 511         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
 512         );
 513   DEBUG ((EFI_D_INFO,
 514           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 515           VariableStore,
 516           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 517         ));
 518   PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
 519   ASSERT_RETURN_ERROR (PcdStatus);
 520 }
 521
 522
 523 VOID
 524 DebugDumpCmos (
 525   VOID
 526   )
 527 {
 528   UINT32 Loop;
 529
 530   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 531
 532   for (Loop = 0; Loop < 0x80; Loop++) {
 533     if ((Loop % 0x10) == 0) {
 534       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 535     }
 536     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 537     if ((Loop % 0x10) == 0xf) {
 538       DEBUG ((EFI_D_INFO, "\n"));
 539     }
 540   }
 541 }
 542
 543
 544 VOID
 545 S3Verification (
 546   VOID
 547   )
 548 {
 549 #if defined (MDE_CPU_X64)
 550   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
 551     DEBUG ((EFI_D_ERROR,
 552       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
 553     DEBUG ((EFI_D_ERROR,
 554       "%a: Please disable S3 on the QEMU command line (see the README),\n",
 555       __FUNCTION__));
 556     DEBUG ((EFI_D_ERROR,
 557       "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
 558     ASSERT (FALSE);
 559     CpuDeadLoop ();
 560   }
 561 #endif
 562 }
 563
 564
 565 /**
 566   Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.
 567   Set the mMaxCpuCount variable.
 568 **/
 569 VOID
 570 MaxCpuCountInitialization (
 571   VOID
 572   )
 573 {
 574   UINT16        ProcessorCount;
 575   RETURN_STATUS PcdStatus;
 576
 577   QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);
 578   ProcessorCount = QemuFwCfgRead16 ();
 579   //
 580   // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount
 581   // from the PCD default. No change to PCDs.
 582   //
 583   if (ProcessorCount == 0) {
 584     mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
 585     return;
 586   }
 587   //
 588   // Otherwise, set mMaxCpuCount to the value reported by QEMU.
 589   //
 590   mMaxCpuCount = ProcessorCount;
 591   //
 592   // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)
 593   // to wait, in the initial AP bringup, exactly as long as it takes for all of
 594   // the APs to report in. For this, we set the longest representable timeout
 595   // (approx. 71 minutes).
 596   //
 597   PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);
 598   ASSERT_RETURN_ERROR (PcdStatus);
 599   PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);
 600   ASSERT_RETURN_ERROR (PcdStatus);
 601   DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,
 602     ProcessorCount));
 603 }
 604
 605
 606 /**
 607   Perform Platform PEI initialization.
 608
 609   @param  FileHandle      Handle of the file being invoked.
 610   @param  PeiServices     Describes the list of possible PEI Services.
 611
 612   @return EFI_SUCCESS     The PEIM initialized successfully.
 613
 614 **/
 615 EFI_STATUS
 616 EFIAPI
 617 InitializePlatform (
 618   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 619   IN CONST EFI_PEI_SERVICES     **PeiServices
 620   )
 621 {
 622   EFI_STATUS    Status;
 623
 624   DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
 625
 626   DebugDumpCmos ();
 627
 628   XenDetect ();
 629
 630   if (QemuFwCfgS3Enabled ()) {
 631     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
 632     mS3Supported = TRUE;
 633     Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
 634     ASSERT_EFI_ERROR (Status);
 635   }
 636
 637   S3Verification ();
 638   BootModeInitialization ();
 639   AddressWidthInitialization ();
 640   MaxCpuCountInitialization ();
 641
 642   //
 643   // Query Host Bridge DID
 644   //
 645   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 646
 647   if (FeaturePcdGet (PcdSmmSmramRequire)) {
 648     Q35TsegMbytesInitialization ();
 649   }
 650
 651   PublishPeiMemory ();
 652
 653   InitializeRamRegions ();
 654
 655   if (mXen) {
 656     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 657     InitializeXen ();
 658   }
 659
 660   if (mBootMode != BOOT_ON_S3_RESUME) {
 661     if (!FeaturePcdGet (PcdSmmSmramRequire)) {
 662       ReserveEmuVariableNvStore ();
 663     }
 664     PeiFvInitialization ();
 665     MemMapInitialization ();
 666     NoexecDxeInitialization ();
 667   }
 668
 669   InstallClearCacheCallback ();
 670   AmdSevInitialize ();
 671   MiscInitialization ();
 672   InstallFeatureControlCallback ();
 673
 674   return EFI_SUCCESS;
 675 }