OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 //
  18 // The package level header files this module uses
  19 //
  20 #include <PiPei.h>
  21
  22 //
  23 // The Library classes this module consumes
  24 //
  25 #include <Library/DebugLib.h>
  26 #include <Library/HobLib.h>
  27 #include <Library/IoLib.h>
  28 #include <Library/MemoryAllocationLib.h>
  29 #include <Library/PcdLib.h>
  30 #include <Library/PciLib.h>
  31 #include <Library/PeimEntryPoint.h>
  32 #include <Library/PeiServicesLib.h>
  33 #include <Library/ResourcePublicationLib.h>
  34 #include <Guid/MemoryTypeInformation.h>
  35 #include <Ppi/MasterBootMode.h>
  36 #include <IndustryStandard/Pci22.h>
  37
  38 #include "Platform.h"
  39 #include "Cmos.h"
  40
  41 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  42   { EfiACPIMemoryNVS,       0x004 },
  43   { EfiACPIReclaimMemory,   0x008 },
  44   { EfiReservedMemoryType,  0x004 },
  45   { EfiRuntimeServicesData, 0x024 },
  46   { EfiRuntimeServicesCode, 0x030 },
  47   { EfiBootServicesCode,    0x180 },
  48   { EfiBootServicesData,    0xF00 },
  49   { EfiMaxMemoryType,       0x000 }
  50 };
  51
  52
  53 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  54   {
  55     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  56     &gEfiPeiMasterBootModePpiGuid,
  57     NULL
  58   }
  59 };
  60
  61
  62 VOID
  63 AddIoMemoryBaseSizeHob (
  64   EFI_PHYSICAL_ADDRESS        MemoryBase,
  65   UINT64                      MemorySize
  66   )
  67 {
  68   BuildResourceDescriptorHob (
  69     EFI_RESOURCE_MEMORY_MAPPED_IO,
  70       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  71       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  72       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  73       EFI_RESOURCE_ATTRIBUTE_TESTED,
  74     MemoryBase,
  75     MemorySize
  76     );
  77 }
  78
  79 VOID
  80 AddReservedMemoryBaseSizeHob (
  81   EFI_PHYSICAL_ADDRESS        MemoryBase,
  82   UINT64                      MemorySize
  83   )
  84 {
  85   BuildResourceDescriptorHob (
  86     EFI_RESOURCE_MEMORY_RESERVED,
  87       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  88       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  89       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  90       EFI_RESOURCE_ATTRIBUTE_TESTED,
  91     MemoryBase,
  92     MemorySize
  93     );
  94 }
  95
  96 VOID
  97 AddIoMemoryRangeHob (
  98   EFI_PHYSICAL_ADDRESS        MemoryBase,
  99   EFI_PHYSICAL_ADDRESS        MemoryLimit
 100   )
 101 {
 102   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 103 }
 104
 105
 106 VOID
 107 AddMemoryBaseSizeHob (
 108   EFI_PHYSICAL_ADDRESS        MemoryBase,
 109   UINT64                      MemorySize
 110   )
 111 {
 112   BuildResourceDescriptorHob (
 113     EFI_RESOURCE_SYSTEM_MEMORY,
 114       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 115       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 116       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 117       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 118       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 119       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 120       EFI_RESOURCE_ATTRIBUTE_TESTED,
 121     MemoryBase,
 122     MemorySize
 123     );
 124 }
 125
 126
 127 VOID
 128 AddMemoryRangeHob (
 129   EFI_PHYSICAL_ADDRESS        MemoryBase,
 130   EFI_PHYSICAL_ADDRESS        MemoryLimit
 131   )
 132 {
 133   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 134 }
 135
 136
 137 VOID
 138 AddUntestedMemoryBaseSizeHob (
 139   EFI_PHYSICAL_ADDRESS        MemoryBase,
 140   UINT64                      MemorySize
 141   )
 142 {
 143   BuildResourceDescriptorHob (
 144     EFI_RESOURCE_SYSTEM_MEMORY,
 145       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 146       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 147       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 148       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 149       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 150       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
 151     MemoryBase,
 152     MemorySize
 153     );
 154 }
 155
 156
 157 VOID
 158 AddUntestedMemoryRangeHob (
 159   EFI_PHYSICAL_ADDRESS        MemoryBase,
 160   EFI_PHYSICAL_ADDRESS        MemoryLimit
 161   )
 162 {
 163   AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 164 }
 165
 166 VOID
 167 XenMemMapInitialization (
 168   VOID
 169   )
 170 {
 171   //
 172   // Create Memory Type Information HOB
 173   //
 174   BuildGuidDataHob (
 175     &gEfiMemoryTypeInformationGuid,
 176     mDefaultMemoryTypeInformation,
 177     sizeof(mDefaultMemoryTypeInformation)
 178     );
 179
 180   //
 181   // Add PCI IO Port space available for PCI resource allocations.
 182   //
 183   BuildResourceDescriptorHob (
 184     EFI_RESOURCE_IO,
 185     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 186     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 187     0xC000,
 188     0x4000
 189     );
 190
 191   //
 192   // Video memory + Legacy BIOS region
 193   //
 194   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 195
 196   XenPublishRamRegions ();
 197 }
 198
 199
 200 VOID
 201 MemMapInitialization (
 202   EFI_PHYSICAL_ADDRESS  TopOfMemory
 203   )
 204 {
 205   //
 206   // Create Memory Type Information HOB
 207   //
 208   BuildGuidDataHob (
 209     &gEfiMemoryTypeInformationGuid,
 210     mDefaultMemoryTypeInformation,
 211     sizeof(mDefaultMemoryTypeInformation)
 212     );
 213
 214   //
 215   // Add PCI IO Port space available for PCI resource allocations.
 216   //
 217   BuildResourceDescriptorHob (
 218     EFI_RESOURCE_IO,
 219     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 220     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 221     0xC000,
 222     0x4000
 223     );
 224
 225   //
 226   // Video memory + Legacy BIOS region
 227   //
 228   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 229
 230   //
 231   // address       purpose   size
 232   // ------------  --------  -------------------------
 233   // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 234   // 0xFC000000    gap                           44 MB
 235   // 0xFEC00000    IO-APIC                        4 KB
 236   // 0xFEC01000    gap                         1020 KB
 237   // 0xFED00000    HPET                           1 KB
 238   // 0xFED00400    gap                         1023 KB
 239   // 0xFEE00000    LAPIC                          1 MB
 240   //
 241   AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000);
 242   AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 243   AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 244   AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 245 }
 246
 247
 248 VOID
 249 MiscInitialization (
 250   VOID
 251   )
 252 {
 253   //
 254   // Disable A20 Mask
 255   //
 256   IoOr8 (0x92, BIT1);
 257
 258   //
 259   // Build the CPU hob with 36-bit addressing and 16-bits of IO space.
 260   //
 261   BuildCpuHob (36, 16);
 262
 263   //
 264   // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for
 265   // example by Xen) and skip the setup here. This matches the logic in
 266   // AcpiTimerLibConstructor ().
 267   //
 268   if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {
 269     //
 270     // The PEI phase should be exited with fully accessibe PIIX4 IO space:
 271     // 1. set PMBA
 272     //
 273     PciAndThenOr32 (
 274       PCI_LIB_ADDRESS (0, 1, 3, 0x40),
 275       (UINT32) ~0xFFC0,
 276       PcdGet16 (PcdAcpiPmBaseAddress)
 277       );
 278
 279     //
 280     // 2. set PCICMD/IOSE
 281     //
 282     PciOr8 (
 283       PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),
 284       EFI_PCI_COMMAND_IO_SPACE
 285       );
 286
 287     //
 288     // 3. set PMREGMISC/PMIOSE
 289     //
 290     PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);
 291   }
 292 }
 293
 294
 295 VOID
 296 BootModeInitialization (
 297   )
 298 {
 299   EFI_STATUS Status;
 300
 301   Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);
 302   ASSERT_EFI_ERROR (Status);
 303
 304   Status = PeiServicesInstallPpi (mPpiBootMode);
 305   ASSERT_EFI_ERROR (Status);
 306 }
 307
 308
 309 VOID
 310 ReserveEmuVariableNvStore (
 311   )
 312 {
 313   EFI_PHYSICAL_ADDRESS VariableStore;
 314
 315   //
 316   // Allocate storage for NV variables early on so it will be
 317   // at a consistent address.  Since VM memory is preserved
 318   // across reboots, this allows the NV variable storage to survive
 319   // a VM reboot.
 320   //
 321   VariableStore =
 322     (EFI_PHYSICAL_ADDRESS)(UINTN)
 323       AllocateAlignedRuntimePages (
 324         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
 325         PcdGet32 (PcdFlashNvStorageFtwSpareSize)
 326         );
 327   DEBUG ((EFI_D_INFO,
 328           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 329           VariableStore,
 330           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 331         ));
 332   PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
 333 }
 334
 335
 336 VOID
 337 DebugDumpCmos (
 338   VOID
 339   )
 340 {
 341   UINTN  Loop;
 342
 343   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 344
 345   for (Loop = 0; Loop < 0x80; Loop++) {
 346     if ((Loop % 0x10) == 0) {
 347       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 348     }
 349     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 350     if ((Loop % 0x10) == 0xf) {
 351       DEBUG ((EFI_D_INFO, "\n"));
 352     }
 353   }
 354 }
 355
 356
 357 /**
 358   Perform Platform PEI initialization.
 359
 360   @param  FileHandle      Handle of the file being invoked.
 361   @param  PeiServices     Describes the list of possible PEI Services.
 362
 363   @return EFI_SUCCESS     The PEIM initialized successfully.
 364
 365 **/
 366 EFI_STATUS
 367 EFIAPI
 368 InitializePlatform (
 369   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 370   IN CONST EFI_PEI_SERVICES     **PeiServices
 371   )
 372 {
 373   EFI_PHYSICAL_ADDRESS  TopOfMemory;
 374
 375   TopOfMemory = 0;
 376
 377   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
 378
 379   DebugDumpCmos ();
 380
 381   XenDetect ();
 382
 383   BootModeInitialization ();
 384
 385   PublishPeiMemory ();
 386
 387   if (mXen) {
 388     PcdSetBool (PcdPciDisableBusEnumeration, TRUE);
 389   } else {
 390     TopOfMemory = MemDetect ();
 391   }
 392
 393   if (mXen) {
 394     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 395     InitializeXen ();
 396   }
 397
 398   ReserveEmuVariableNvStore ();
 399
 400   PeiFvInitialization ();
 401
 402   if (mXen) {
 403     XenMemMapInitialization ();
 404   } else {
 405     MemMapInitialization (TopOfMemory);
 406   }
 407
 408   MiscInitialization ();
 409
 410   return EFI_SUCCESS;
 411 }