PcAtChipsetPkg/Include/Library/IoApicLib.h

   1 /** @file
   2   Public include file for I/O APIC library.
   3
   4   I/O APIC library assumes I/O APIC is enabled. It does not
   5   handles cases where I/O APIC is disabled.
   6
   7   Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
   8   SPDX-License-Identifier: BSD-2-Clause-Patent
   9
  10 **/
  11 #ifndef __IO_APIC_LIB_H__
  12 #define __IO_APIC_LIB_H__
  13
  14 /**
  15   Read a 32-bit I/O APIC register.
  16
  17   If Index is >= 0x100, then ASSERT().
  18
  19   @param  Index  Specifies the I/O APIC register to read.
  20
  21   @return  The 32-bit value read from the I/O APIC register specified by Index.
  22 **/
  23 UINT32
  24 EFIAPI
  25 IoApicRead (
  26   IN UINTN  Index
  27   );
  28
  29 /**
  30   Write a 32-bit I/O APIC register.
  31
  32   If Index is >= 0x100, then ASSERT().
  33
  34   @param  Index  Specifies the I/O APIC register to write.
  35   @param  Value  Specifies the value to write to the I/O APIC register specified by Index.
  36
  37   @return  The 32-bit value written to I/O APIC register specified by Index.
  38 **/
  39 UINT32
  40 EFIAPI
  41 IoApicWrite (
  42   IN UINTN   Index,
  43   IN UINT32  Value
  44   );
  45
  46 /**
  47   Set the interrupt mask of an I/O APIC interrupt.
  48
  49   If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
  50
  51   @param  Irq     Specifies the I/O APIC interrupt to enable or disable.
  52   @param  Enable  If TRUE, then enable the I/O APIC interrupt specified by Irq.
  53                   If FALSE, then disable the I/O APIC interrupt specified by Irq.
  54 **/
  55 VOID
  56 EFIAPI
  57 IoApicEnableInterrupt (
  58   IN UINTN    Irq,
  59   IN BOOLEAN  Enable
  60   );
  61
  62 /**
  63   Configures an I/O APIC interrupt.
  64
  65   Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical
  66   mode to the Local APIC of the currntly executing CPU.  The default state of the
  67   entry is for the interrupt to be disabled (masked).  IoApicEnableInterrupts() must
  68   be used to enable(unmask) the I/O APIC Interrupt.
  69
  70   If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
  71   If Vector >= 0x100, then ASSERT().
  72   If DeliveryMode is not supported, then ASSERT().
  73
  74   @param  Irq             Specifies the I/O APIC interrupt to initialize.
  75   @param  Vector          The 8-bit interrupt vector associated with the I/O APIC
  76                           Interrupt.  Must be in the range 0x10..0xFE.
  77   @param  DeliveryMode    A 3-bit value that specifies how the recept of the I/O APIC
  78                           interrupt is handled.  The only supported values are:
  79                             0: IO_APIC_DELIVERY_MODE_FIXED
  80                             1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY
  81                             2: IO_APIC_DELIVERY_MODE_SMI
  82                             4: IO_APIC_DELIVERY_MODE_NMI
  83                             5: IO_APIC_DELIVERY_MODE_INIT
  84                             7: IO_APIC_DELIVERY_MODE_EXTINT
  85   @param  LevelTriggered  TRUE specifies a level triggered interrupt.
  86                           FALSE specifies an edge triggered interrupt.
  87   @param  AssertionLevel  TRUE specified an active high interrupt.
  88                           FALSE specifies an active low interrupt.
  89 **/
  90 VOID
  91 EFIAPI
  92 IoApicConfigureInterrupt (
  93   IN UINTN    Irq,
  94   IN UINTN    Vector,
  95   IN UINTN    DeliveryMode,
  96   IN BOOLEAN  LevelTriggered,
  97   IN BOOLEAN  AssertionLevel
  98   );
  99 #endif