PcAtChipsetPkg/Include/Library/IoApicLib.h

   1 /** @file
   2   Public include file for I/O APIC library.
   3
   4   I/O APIC library assumes I/O APIC is enabled. It does not
   5   handles cases where I/O APIC is disabled.
   6
   7   Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
   8   This program and the accompanying materials
   9   are licensed and made available under the terms and conditions of the BSD License
  10   which accompanies this distribution.  The full text of the license may be found at
  11   http://opensource.org/licenses/bsd-license.php
  12
  13   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15
  16 **/
  17
  18 /**
  19   Read a 32-bit I/O APIC register.
  20
  21   If Index is >= 0x100, then ASSERT().
  22
  23   @param  Index  Specifies the I/O APIC register to read.
  24
  25   @return  The 32-bit value read from the I/O APIC register specified by Index.
  26 **/
  27 UINT32
  28 EFIAPI
  29 IoApicRead (
  30   IN UINTN  Index
  31   );
  32
  33 /**
  34   Write a 32-bit I/O APIC register.
  35
  36   If Index is >= 0x100, then ASSERT().
  37
  38   @param  Index  Specifies the I/O APIC register to write.
  39   @param  Value  Specifies the value to write to the I/O APIC register specified by Index.
  40
  41   @return  The 32-bit value written to I/O APIC register specified by Index.
  42 **/
  43 UINT32
  44 EFIAPI
  45 IoApicWrite (
  46   IN UINTN   Index,
  47   IN UINT32  Value
  48   );
  49
  50 /**
  51   Set the interrupt mask of an I/O APIC interrupt.
  52
  53   If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
  54
  55   @param  Irq     Specifies the I/O APIC interrupt to enable or disable.
  56   @param  Enable  If TRUE, then enable the I/O APIC interrupt specified by Irq.
  57                   If FALSE, then disable the I/O APIC interrupt specified by Irq.
  58 **/
  59 VOID
  60 EFIAPI
  61 IoApicEnableInterrupt (
  62   IN UINTN    Irq,
  63   IN BOOLEAN  Enable
  64   );
  65
  66 /**
  67   Configures an I/O APIC interrupt.
  68
  69   Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical
  70   mode to the Local APIC of the currntly executing CPU.  The default state of the
  71   entry is for the interrupt to be disabled (masked).  IoApicEnableInterrupts() must
  72   be used to enable(unmask) the I/O APIC Interrupt.
  73
  74   If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
  75   If Vector >= 0x100, then ASSERT().
  76   If DeliveryMode is not supported, then ASSERT().
  77
  78   @param  Irq             Specifies the I/O APIC interrupt to initialize.
  79   @param  Vector          The 8-bit interrupt vector associated with the I/O APIC
  80                           Interrupt.  Must be in the range 0x10..0xFE.
  81   @param  DeliveryMode    A 3-bit value that specifies how the recept of the I/O APIC
  82                           interrupt is handled.  The only supported values are:
  83                             0: IO_APIC_DELIVERY_MODE_FIXED
  84                             1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY
  85                             2: IO_APIC_DELIVERY_MODE_SMI
  86                             4: IO_APIC_DELIVERY_MODE_NMI
  87                             5: IO_APIC_DELIVERY_MODE_INIT
  88                             7: IO_APIC_DELIVERY_MODE_EXTINT
  89   @param  LevelTriggered  TRUE specifies a level triggered interrupt.
  90                           FALSE specifies an edge triggered interrupt.
  91   @param  AssertionLevel  TRUE specified an active high interrupt.
  92                           FALSE specifies an active low interrupt.
  93 **/
  94 VOID
  95 EFIAPI
  96 IoApicConfigureInterrupt (
  97   IN UINTN    Irq,
  98   IN UINTN    Vector,
  99   IN UINTN    DeliveryMode,
 100   IN BOOLEAN  LevelTriggered,
 101   IN BOOLEAN  AssertionLevel
 102   );