2 HPET register definitions from the IA-PC HPET (High Precision Event Timers)
3 Specification, Revision 1.0a, October 2004.
5 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef __HPET_REGISTER_H__
17 #define __HPET_REGISTER_H__
20 /// HPET General Register Offsets
22 #define HPET_GENERAL_CAPABILITIES_ID_OFFSET 0x000
23 #define HPET_GENERAL_CONFIGURATION_OFFSET 0x010
24 #define HPET_GENERAL_INTERRUPT_STATUS_OFFSET 0x020
27 /// HPET Timer Register Offsets
29 #define HPET_MAIN_COUNTER_OFFSET 0x0F0
30 #define HPET_TIMER_CONFIGURATION_OFFSET 0x100
31 #define HPET_TIMER_COMPARATOR_OFFSET 0x108
32 #define HPET_TIMER_MSI_ROUTE_OFFSET 0x110
35 /// Stride between sets of HPET Timer Registers
37 #define HPET_TIMER_STRIDE 0x20
42 /// HPET General Capabilities and ID Register
47 UINT32 NumberOfTimers
:5;
52 UINT32 CounterClockPeriod
:32;
55 } HPET_GENERAL_CAPABILITIES_ID_REGISTER
;
58 /// HPET General Configuration Register
62 UINT32 MainCounterEnable
:1;
63 UINT32 LegacyRouteEnable
:1;
68 } HPET_GENERAL_CONFIGURATION_REGISTER
;
71 /// HPET Timer Configuration Register
76 UINT32 LevelTriggeredInterrupt
:1;
77 UINT32 InterruptEnable
:1;
78 UINT32 PeriodicInterruptEnable
:1;
79 UINT32 PeriodicInterruptCapablity
:1;
80 UINT32 CounterSizeCapablity
:1;
81 UINT32 ValueSetEnable
:1;
83 UINT32 CounterSizeEnable
:1;
84 UINT32 InterruptRoute
:5;
85 UINT32 MsiInterruptEnable
:1;
86 UINT32 MsiInterruptCapablity
:1;
88 UINT32 InterruptRouteCapability
;
91 } HPET_TIMER_CONFIGURATION_REGISTER
;
94 /// HPET Timer MSI Route Register
102 } HPET_TIMER_MSI_ROUTE_REGISTER
;