2 HPET register definitions from the IA-PC HPET (High Precision Event Timers)
3 Specification, Revision 1.0a, October 2004.
5 Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #ifndef __HPET_REGISTER_H__
11 #define __HPET_REGISTER_H__
14 /// HPET General Register Offsets
16 #define HPET_GENERAL_CAPABILITIES_ID_OFFSET 0x000
17 #define HPET_GENERAL_CONFIGURATION_OFFSET 0x010
18 #define HPET_GENERAL_INTERRUPT_STATUS_OFFSET 0x020
21 /// HPET Timer Register Offsets
23 #define HPET_MAIN_COUNTER_OFFSET 0x0F0
24 #define HPET_TIMER_CONFIGURATION_OFFSET 0x100
25 #define HPET_TIMER_COMPARATOR_OFFSET 0x108
26 #define HPET_TIMER_MSI_ROUTE_OFFSET 0x110
29 /// Stride between sets of HPET Timer Registers
31 #define HPET_TIMER_STRIDE 0x20
36 /// HPET General Capabilities and ID Register
41 UINT32 NumberOfTimers
: 5;
42 UINT32 CounterSize
: 1;
44 UINT32 LegacyRoute
: 1;
46 UINT32 CounterClockPeriod
: 32;
49 } HPET_GENERAL_CAPABILITIES_ID_REGISTER
;
52 /// HPET General Configuration Register
56 UINT32 MainCounterEnable
: 1;
57 UINT32 LegacyRouteEnable
: 1;
58 UINT32 Reserved0
: 30;
59 UINT32 Reserved1
: 32;
62 } HPET_GENERAL_CONFIGURATION_REGISTER
;
65 /// HPET Timer Configuration Register
70 UINT32 LevelTriggeredInterrupt
: 1;
71 UINT32 InterruptEnable
: 1;
72 UINT32 PeriodicInterruptEnable
: 1;
73 UINT32 PeriodicInterruptCapability
: 1;
74 UINT32 CounterSizeCapability
: 1;
75 UINT32 ValueSetEnable
: 1;
77 UINT32 CounterSizeEnable
: 1;
78 UINT32 InterruptRoute
: 5;
79 UINT32 MsiInterruptEnable
: 1;
80 UINT32 MsiInterruptCapability
: 1;
81 UINT32 Reserved2
: 16;
82 UINT32 InterruptRouteCapability
;
85 } HPET_TIMER_CONFIGURATION_REGISTER
;
88 /// HPET Timer MSI Route Register
96 } HPET_TIMER_MSI_ROUTE_REGISTER
;