RefRefine soma code to make code run safely.
[mirror_edk2.git] / PcAtChipsetPkg / PciHostBridgeDxe / PciHostBridge.h
1 /** @file
2 The Header file of the Pci Host Bridge Driver
3
4 Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #ifndef _PCI_HOST_BRIDGE_H_
16 #define _PCI_HOST_BRIDGE_H_
17
18 #include <PiDxe.h>
19
20 #include <IndustryStandard/Pci.h>
21 #include <IndustryStandard/Acpi.h>
22
23 #include <Protocol/PciHostBridgeResourceAllocation.h>
24 #include <Protocol/PciRootBridgeIo.h>
25 #include <Protocol/Metronome.h>
26 #include <Protocol/DevicePath.h>
27
28
29 #include <Library/BaseLib.h>
30 #include <Library/DebugLib.h>
31 #include <Library/BaseMemoryLib.h>
32 #include <Library/MemoryAllocationLib.h>
33 #include <Library/UefiLib.h>
34 #include <Library/UefiBootServicesTableLib.h>
35 #include <Library/DxeServicesTableLib.h>
36 #include <Library/DevicePathLib.h>
37 #include <Library/IoLib.h>
38 #include <Library/PciLib.h>
39
40 //
41 // Hard code the host bridge number in the platform.
42 // In this chipset, there is only one host bridge.
43 //
44 #define HOST_BRIDGE_NUMBER 1
45
46 #define MAX_PCI_DEVICE_NUMBER 31
47 #define MAX_PCI_FUNCTION_NUMBER 7
48 #define MAX_PCI_REG_ADDRESS 0xFF
49
50 typedef enum {
51 IoOperation,
52 MemOperation,
53 PciOperation
54 } OPERATION_TYPE;
55
56 #define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't')
57 typedef struct {
58 UINTN Signature;
59 EFI_HANDLE HostBridgeHandle;
60 UINTN RootBridgeNumber;
61 LIST_ENTRY Head;
62 BOOLEAN ResourceSubmited;
63 BOOLEAN CanRestarted;
64 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;
65 } PCI_HOST_BRIDGE_INSTANCE;
66
67 #define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \
68 CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
69
70 //
71 // HostBridge Resource Allocation interface
72 //
73
74 /**
75 These are the notifications from the PCI bus driver that it is about to enter a certain
76 phase of the PCI enumeration process.
77
78 This member function can be used to notify the host bridge driver to perform specific actions,
79 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
80 Eight notification points are defined at this time. See belows:
81 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
82 structures. The PCI enumerator should issue this notification
83 before starting a fresh enumeration process. Enumeration cannot
84 be restarted after sending any other notification such as
85 EfiPciHostBridgeBeginBusAllocation.
86 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
87 required here. This notification can be used to perform any
88 chipset-specific programming.
89 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
90 specific action is required here. This notification can be used to
91 perform any chipset-specific programming.
92 EfiPciHostBridgeBeginResourceAllocation
93 The resource allocation phase is about to begin. No specific
94 action is required here. This notification can be used to perform
95 any chipset-specific programming.
96 EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
97 root bridges. These resource settings are returned on the next call to
98 GetProposedResources(). Before calling NotifyPhase() with a Phase of
99 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
100 for gathering I/O and memory requests for
101 all the PCI root bridges and submitting these requests using
102 SubmitResources(). This function pads the resource amount
103 to suit the root bridge hardware, takes care of dependencies between
104 the PCI root bridges, and calls the Global Coherency Domain (GCD)
105 with the allocation request. In the case of padding, the allocated range
106 could be bigger than what was requested.
107 EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
108 resources (proposed resources) for all the PCI root bridges. After the
109 hardware is programmed, reassigning resources will not be supported.
110 The bus settings are not affected.
111 EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
112 root bridges and resets the I/O and memory apertures to their initial
113 state. The bus settings are not affected. If the request to allocate
114 resources fails, the PCI enumerator can use this notification to
115 deallocate previous resources, adjust the requests, and retry
116 allocation.
117 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
118 required here. This notification can be used to perform any chipsetspecific
119 programming.
120
121 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
122 @param[in] Phase The phase during enumeration
123
124 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
125 is valid for a Phase of EfiPciHostBridgeAllocateResources if
126 SubmitResources() has not been called for one or more
127 PCI root bridges before this call
128 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
129 for a Phase of EfiPciHostBridgeSetResources.
130 @retval EFI_INVALID_PARAMETER Invalid phase parameter
131 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
132 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
133 previously submitted resource requests cannot be fulfilled or
134 were only partially fulfilled.
135 @retval EFI_SUCCESS The notification was accepted without any errors.
136
137 **/
138 EFI_STATUS
139 EFIAPI
140 NotifyPhase(
141 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
142 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
143 );
144
145 /**
146 Return the device handle of the next PCI root bridge that is associated with this Host Bridge.
147
148 This function is called multiple times to retrieve the device handles of all the PCI root bridges that
149 are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI
150 root bridges. On each call, the handle that was returned by the previous call is passed into the
151 interface, and on output the interface returns the device handle of the next PCI root bridge. The
152 caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
153 for that root bridge. When there are no more PCI root bridges to report, the interface returns
154 EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they
155 are returned by this function.
156 For D945 implementation, there is only one root bridge in PCI host bridge.
157
158 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
159 @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.
160
161 @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
162 specific Host bridge and return EFI_SUCCESS.
163 @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.
164 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was
165 returned on a previous call to GetNextRootBridge().
166 **/
167 EFI_STATUS
168 EFIAPI
169 GetNextRootBridge(
170 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
171 IN OUT EFI_HANDLE *RootBridgeHandle
172 );
173
174 /**
175 Returns the allocation attributes of a PCI root bridge.
176
177 The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary
178 from one PCI root bridge to another. These attributes are different from the decode-related
179 attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
180 RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device
181 handles of all the root bridges that are associated with this host bridge must be obtained by calling
182 GetNextRootBridge(). The attributes are static in the sense that they do not change during or
183 after the enumeration process. The hardware may provide mechanisms to change the attributes on
184 the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is
185 installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
186 "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.
187 For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to
188 include requests for the prefetchable memory in the nonprefetchable memory pool and not request any
189 prefetchable memory.
190 Attribute Description
191 ------------------------------------ ----------------------------------------------------------------------
192 EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate
193 windows for nonprefetchable and prefetchable memory. A PCI bus
194 driver needs to include requests for prefetchable memory in the
195 nonprefetchable memory pool.
196
197 EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory
198 windows. If this bit is not set, the PCI bus driver needs to include
199 requests for a 64-bit memory address in the corresponding 32-bit
200 memory pool.
201
202 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
203 @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type
204 EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
205 @param[out] Attributes The pointer to attribte of root bridge, it is output parameter
206
207 @retval EFI_INVALID_PARAMETER Attribute pointer is NULL
208 @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.
209 @retval EFI_SUCCESS Success to get attribute of interested root bridge.
210
211 **/
212 EFI_STATUS
213 EFIAPI
214 GetAttributes(
215 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
216 IN EFI_HANDLE RootBridgeHandle,
217 OUT UINT64 *Attributes
218 );
219
220 /**
221 Sets up the specified PCI root bridge for the bus enumeration process.
222
223 This member function sets up the root bridge for bus enumeration and returns the PCI bus range
224 over which the search should be performed in ACPI 2.0 resource descriptor format.
225
226 @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
227 @param[in] RootBridgeHandle The PCI Root Bridge to be set up.
228 @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.
229
230 @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
231 @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.
232 @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.
233
234 **/
235 EFI_STATUS
236 EFIAPI
237 StartBusEnumeration(
238 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
239 IN EFI_HANDLE RootBridgeHandle,
240 OUT VOID **Configuration
241 );
242
243 /**
244 Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
245
246 This member function programs the specified PCI root bridge to decode the bus range that is
247 specified by the input parameter Configuration.
248 The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.
249
250 @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
251 @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed
252 @param[in] Configuration The pointer to the PCI bus resource descriptor
253
254 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
255 @retval EFI_INVALID_PARAMETER Configuration is NULL.
256 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
257 @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.
258 @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than
259 bus descriptors.
260 @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.
261 @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.
262 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.
263 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
264 @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.
265
266 **/
267 EFI_STATUS
268 EFIAPI
269 SetBusNumbers(
270 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
271 IN EFI_HANDLE RootBridgeHandle,
272 IN VOID *Configuration
273 );
274
275 /**
276 Submits the I/O and memory resource requirements for the specified PCI root bridge.
277
278 This function is used to submit all the I/O and memory resources that are required by the specified
279 PCI root bridge. The input parameter Configuration is used to specify the following:
280 - The various types of resources that are required
281 - The associated lengths in terms of ACPI 2.0 resource descriptor format
282
283 @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
284 @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.
285 @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.
286
287 @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.
288 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
289 @retval EFI_INVALID_PARAMETER Configuration is NULL.
290 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
291 @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are
292 not supported by this PCI root bridge. This error will happen if the caller
293 did not combine resources according to Attributes that were returned by
294 GetAllocAttributes().
295 @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.
296 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.
297 @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.
298
299 **/
300 EFI_STATUS
301 EFIAPI
302 SubmitResources(
303 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
304 IN EFI_HANDLE RootBridgeHandle,
305 IN VOID *Configuration
306 );
307
308 /**
309 Returns the proposed resource settings for the specified PCI root bridge.
310
311 This member function returns the proposed resource settings for the specified PCI root bridge. The
312 proposed resource settings are prepared when NotifyPhase() is called with a Phase of
313 EfiPciHostBridgeAllocateResources. The output parameter Configuration
314 specifies the following:
315 - The various types of resources, excluding bus resources, that are allocated
316 - The associated lengths in terms of ACPI 2.0 resource descriptor format
317
318 @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
319 @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
320 @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.
321
322 @retval EFI_SUCCESS The requested parameters were returned.
323 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
324 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
325 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
326
327 **/
328 EFI_STATUS
329 EFIAPI
330 GetProposedResources(
331 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
332 IN EFI_HANDLE RootBridgeHandle,
333 OUT VOID **Configuration
334 );
335
336 /**
337 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
338 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
339 PCI controllers before enumeration.
340
341 This function is called during the PCI enumeration process. No specific action is expected from this
342 member function. It allows the host bridge driver to preinitialize individual PCI controllers before
343 enumeration.
344
345 @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
346 @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in
347 InstallProtocolInterface() in the UEFI 2.0 Specification.
348 @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the
349 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI
350 configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for
351 the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
352 @param Phase The phase of the PCI device enumeration.
353
354 @retval EFI_SUCCESS The requested parameters were returned.
355 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
356 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
357 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
358 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
359 not enumerate this device, including its child devices if it is a PCI-to-PCI
360 bridge.
361
362 **/
363 EFI_STATUS
364 EFIAPI
365 PreprocessController (
366 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
367 IN EFI_HANDLE RootBridgeHandle,
368 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
369 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
370 );
371
372
373 //
374 // Define resource status constant
375 //
376 #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
377 #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
378
379
380 //
381 // Driver Instance Data Prototypes
382 //
383
384 typedef struct {
385 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;
386 UINTN NumberOfBytes;
387 UINTN NumberOfPages;
388 EFI_PHYSICAL_ADDRESS HostAddress;
389 EFI_PHYSICAL_ADDRESS MappedHostAddress;
390 } MAP_INFO;
391
392 typedef struct {
393 ACPI_HID_DEVICE_PATH AcpiDevicePath;
394 EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
395 } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
396
397 typedef struct {
398 UINT64 BusBase;
399 UINT64 BusLimit;
400
401 UINT64 MemBase;
402 UINT64 MemLimit;
403
404 UINT64 IoBase;
405 UINT64 IoLimit;
406 } PCI_ROOT_BRIDGE_RESOURCE_APPETURE;
407
408 typedef enum {
409 TypeIo = 0,
410 TypeMem32,
411 TypePMem32,
412 TypeMem64,
413 TypePMem64,
414 TypeBus,
415 TypeMax
416 } PCI_RESOURCE_TYPE;
417
418 typedef enum {
419 ResNone = 0,
420 ResSubmitted,
421 ResRequested,
422 ResAllocated,
423 ResStatusMax
424 } RES_STATUS;
425
426 typedef struct {
427 PCI_RESOURCE_TYPE Type;
428 UINT64 Base;
429 UINT64 Length;
430 UINT64 Alignment;
431 RES_STATUS Status;
432 } PCI_RES_NODE;
433
434 #define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b')
435
436 typedef struct {
437 UINT32 Signature;
438 LIST_ENTRY Link;
439 EFI_HANDLE Handle;
440 UINT64 RootBridgeAttrib;
441 UINT64 Attributes;
442 UINT64 Supports;
443
444 //
445 // Specific for this memory controller: Bus, I/O, Mem
446 //
447 PCI_RES_NODE ResAllocNode[6];
448
449 //
450 // Addressing for Memory and I/O and Bus arrange
451 //
452 UINT64 BusBase;
453 UINT64 MemBase;
454 UINT64 IoBase;
455 UINT64 BusLimit;
456 UINT64 MemLimit;
457 UINT64 IoLimit;
458
459 UINTN PciAddress;
460 UINTN PciData;
461
462 EFI_DEVICE_PATH_PROTOCOL *DevicePath;
463 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
464
465 } PCI_ROOT_BRIDGE_INSTANCE;
466
467
468 //
469 // Driver Instance Data Macros
470 //
471 #define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \
472 CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
473
474
475 #define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \
476 CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)
477
478 /**
479
480 Construct the Pci Root Bridge Io protocol
481
482 @param Protocol Point to protocol instance
483 @param HostBridgeHandle Handle of host bridge
484 @param Attri Attribute of host bridge
485 @param ResAppeture ResourceAppeture for host bridge
486
487 @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
488
489 **/
490 EFI_STATUS
491 RootBridgeConstructor (
492 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,
493 IN EFI_HANDLE HostBridgeHandle,
494 IN UINT64 Attri,
495 IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture
496 );
497
498 #endif