2 PCI Root Bridge Io Protocol implementation
4 Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved. <BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "PciHostBridge.h"
18 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp
[TypeMax
];
19 EFI_ACPI_END_TAG_DESCRIPTOR EndDesp
;
20 } RESOURCE_CONFIGURATION
;
22 RESOURCE_CONFIGURATION Configuration
= {
23 {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},
24 {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0},
25 {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},
26 {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},
27 {0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},
28 {0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0}},
33 // Protocol Member Function Prototypes
37 Polls an address in memory mapped I/O space until an exit condition is met, or
40 This function provides a standard way to poll a PCI memory location. A PCI memory read
41 operation is performed at the PCI memory address specified by Address for the width specified
42 by Width. The result of this PCI memory read operation is stored in Result. This PCI memory
43 read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &
44 Mask) is equal to Value.
46 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
47 @param[in] Width Signifies the width of the memory operations.
48 @param[in] Address The base address of the memory operations. The caller is
49 responsible for aligning Address if required.
50 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
51 are ignored. The bits in the bytes below Width which are zero in
52 Mask are ignored when polling the memory address.
53 @param[in] Value The comparison value used for the polling exit criteria.
54 @param[in] Delay The number of 100 ns units to poll. Note that timer available may
55 be of poorer granularity.
56 @param[out] Result Pointer to the last value read from the memory location.
58 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
59 @retval EFI_INVALID_PARAMETER Width is invalid.
60 @retval EFI_INVALID_PARAMETER Result is NULL.
61 @retval EFI_TIMEOUT Delay expired before a match occurred.
62 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
68 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
69 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
78 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
79 satisfied or after a defined duration.
81 This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is
82 performed at the PCI I/O address specified by Address for the width specified by Width.
83 The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is
84 repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal
87 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
88 @param[in] Width Signifies the width of the I/O operations.
89 @param[in] Address The base address of the I/O operations. The caller is responsible
90 for aligning Address if required.
91 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
92 are ignored. The bits in the bytes below Width which are zero in
93 Mask are ignored when polling the I/O address.
94 @param[in] Value The comparison value used for the polling exit criteria.
95 @param[in] Delay The number of 100 ns units to poll. Note that timer available may
96 be of poorer granularity.
97 @param[out] Result Pointer to the last value read from the memory location.
99 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
100 @retval EFI_INVALID_PARAMETER Width is invalid.
101 @retval EFI_INVALID_PARAMETER Result is NULL.
102 @retval EFI_TIMEOUT Delay expired before a match occurred.
103 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
109 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
110 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
119 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
121 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
122 registers in the PCI root bridge memory space.
123 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
124 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
126 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
127 @param[in] Width Signifies the width of the memory operation.
128 @param[in] Address The base address of the memory operation. The caller is
129 responsible for aligning the Address if required.
130 @param[in] Count The number of memory operations to perform. Bytes moved is
131 Width size * Count, starting at Address.
132 @param[out] Buffer For read operations, the destination buffer to store the results. For
133 write operations, the source buffer to write data from.
135 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
136 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
137 @retval EFI_INVALID_PARAMETER Buffer is NULL.
138 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
143 RootBridgeIoMemRead (
144 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
145 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
152 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
154 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
155 registers in the PCI root bridge memory space.
156 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
157 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
159 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
160 @param[in] Width Signifies the width of the memory operation.
161 @param[in] Address The base address of the memory operation. The caller is
162 responsible for aligning the Address if required.
163 @param[in] Count The number of memory operations to perform. Bytes moved is
164 Width size * Count, starting at Address.
165 @param[out] Buffer For read operations, the destination buffer to store the results. For
166 write operations, the source buffer to write data from.
168 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
169 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
170 @retval EFI_INVALID_PARAMETER Buffer is NULL.
171 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
175 RootBridgeIoMemWrite (
176 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
177 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
184 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
186 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
187 @param[in] Width Signifies the width of the memory operations.
188 @param[in] Address The base address of the I/O operation. The caller is responsible for
189 aligning the Address if required.
190 @param[in] Count The number of I/O operations to perform. Bytes moved is Width
191 size * Count, starting at Address.
192 @param[out] Buffer For read operations, the destination buffer to store the results. For
193 write operations, the source buffer to write data from.
195 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
196 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
197 @retval EFI_INVALID_PARAMETER Buffer is NULL.
198 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
204 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
205 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
206 IN UINT64 UserAddress
,
208 IN OUT VOID
*UserBuffer
212 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
214 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
215 @param[in] Width Signifies the width of the memory operations.
216 @param[in] Address The base address of the I/O operation. The caller is responsible for
217 aligning the Address if required.
218 @param[in] Count The number of I/O operations to perform. Bytes moved is Width
219 size * Count, starting at Address.
220 @param[out] Buffer For read operations, the destination buffer to store the results. For
221 write operations, the source buffer to write data from.
223 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
224 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
225 @retval EFI_INVALID_PARAMETER Buffer is NULL.
226 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
231 RootBridgeIoIoWrite (
232 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
233 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
234 IN UINT64 UserAddress
,
236 IN OUT VOID
*UserBuffer
240 Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
241 root bridge memory space.
243 The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory
244 space to another region of PCI root bridge memory space. This is especially useful for video scroll
245 operation on a memory mapped video buffer.
246 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
247 any alignment and memory width restrictions that a PCI root bridge on a platform might require.
249 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
250 @param[in] Width Signifies the width of the memory operations.
251 @param[in] DestAddress The destination address of the memory operation. The caller is
252 responsible for aligning the DestAddress if required.
253 @param[in] SrcAddress The source address of the memory operation. The caller is
254 responsible for aligning the SrcAddress if required.
255 @param[in] Count The number of memory operations to perform. Bytes moved is
256 Width size * Count, starting at DestAddress and SrcAddress.
258 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
259 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
260 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
265 RootBridgeIoCopyMem (
266 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
267 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
268 IN UINT64 DestAddress
,
269 IN UINT64 SrcAddress
,
274 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
276 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
277 registers for a PCI controller.
278 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
279 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
282 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
283 @param[in] Width Signifies the width of the memory operations.
284 @param[in] Address The address within the PCI configuration space for the PCI controller.
285 @param[in] Count The number of PCI configuration operations to perform. Bytes
286 moved is Width size * Count, starting at Address.
287 @param[out] Buffer For read operations, the destination buffer to store the results. For
288 write operations, the source buffer to write data from.
290 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
291 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
292 @retval EFI_INVALID_PARAMETER Buffer is NULL.
293 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
298 RootBridgeIoPciRead (
299 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
300 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
307 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
309 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
310 registers for a PCI controller.
311 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
312 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
315 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
316 @param[in] Width Signifies the width of the memory operations.
317 @param[in] Address The address within the PCI configuration space for the PCI controller.
318 @param[in] Count The number of PCI configuration operations to perform. Bytes
319 moved is Width size * Count, starting at Address.
320 @param[out] Buffer For read operations, the destination buffer to store the results. For
321 write operations, the source buffer to write data from.
323 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
324 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
325 @retval EFI_INVALID_PARAMETER Buffer is NULL.
326 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
331 RootBridgeIoPciWrite (
332 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
333 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
340 Provides the PCI controller-specific addresses required to access system memory from a
343 The Map() function provides the PCI controller specific addresses needed to access system
344 memory. This function is used to map system memory for PCI bus master DMA accesses.
346 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
347 @param[in] Operation Indicates if the bus master is going to read or write to system memory.
348 @param[in] HostAddress The system memory address to map to the PCI controller.
349 @param[in][out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
350 @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use
351 to access the system memory's HostAddress.
352 @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
354 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
355 @retval EFI_INVALID_PARAMETER Operation is invalid.
356 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
357 @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.
358 @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.
359 @retval EFI_INVALID_PARAMETER Mapping is NULL.
360 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
361 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
362 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
368 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
369 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation
,
370 IN VOID
*HostAddress
,
371 IN OUT UINTN
*NumberOfBytes
,
372 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
377 Completes the Map() operation and releases any corresponding resources.
379 The Unmap() function completes the Map() operation and releases any corresponding resources.
380 If the operation was an EfiPciOperationBusMasterWrite or
381 EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.
382 Any resources used for the mapping are freed.
384 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
385 @param[in] Mapping The mapping value returned from Map().
387 @retval EFI_SUCCESS The range was unmapped.
388 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
389 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
395 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
400 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
401 EfiPciOperationBusMasterCommonBuffer64 mapping.
403 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
404 @param Type This parameter is not used and must be ignored.
405 @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
406 @param Pages The number of pages to allocate.
407 @param HostAddress A pointer to store the base system memory address of the allocated range.
408 @param Attributes The requested bit mask of attributes for the allocated range. Only
409 the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
410 and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
412 @retval EFI_SUCCESS The requested memory pages were allocated.
413 @retval EFI_INVALID_PARAMETER MemoryType is invalid.
414 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
415 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
416 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
417 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
422 RootBridgeIoAllocateBuffer (
423 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
424 IN EFI_ALLOCATE_TYPE Type
,
425 IN EFI_MEMORY_TYPE MemoryType
,
427 OUT VOID
**HostAddress
,
432 Frees memory that was allocated with AllocateBuffer().
434 The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
436 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
437 @param Pages The number of pages to free.
438 @param HostAddress The base system memory address of the allocated range.
440 @retval EFI_SUCCESS The requested memory pages were freed.
441 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
442 was not allocated with AllocateBuffer().
447 RootBridgeIoFreeBuffer (
448 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
450 OUT VOID
*HostAddress
454 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
456 The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system
457 memory. Posted write transactions are generated by PCI bus masters when they perform write
458 transactions to target addresses in system memory.
459 This function does not flush posted write transactions from any PCI bridges. A PCI controller
460 specific action must be taken to guarantee that the posted write transactions have been flushed from
461 the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with
462 a PCI read transaction from the PCI controller prior to calling Flush().
464 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
466 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
467 bridge to system memory.
468 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
469 host bridge due to a hardware error.
475 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
479 Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
480 attributes that a PCI root bridge is currently using.
482 The GetAttributes() function returns the mask of attributes that this PCI root bridge supports
483 and the mask of attributes that the PCI root bridge is currently using.
485 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
486 @param Supported A pointer to the mask of attributes that this PCI root bridge
487 supports setting with SetAttributes().
488 @param Attributes A pointer to the mask of attributes that this PCI root bridge is
491 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root
492 bridge supports is returned in Supports. If Attributes is
493 not NULL, then the attributes that the PCI root bridge is currently
494 using is returned in Attributes.
495 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
500 RootBridgeIoGetAttributes (
501 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
502 OUT UINT64
*Supported
,
503 OUT UINT64
*Attributes
507 Sets attributes for a resource range on a PCI root bridge.
509 The SetAttributes() function sets the attributes specified in Attributes for the PCI root
510 bridge on the resource range specified by ResourceBase and ResourceLength. Since the
511 granularity of setting these attributes may vary from resource type to resource type, and from
512 platform to platform, the actual resource range and the one passed in by the caller may differ. As a
513 result, this function may set the attributes specified by Attributes on a larger resource range
514 than the caller requested. The actual range is returned in ResourceBase and
515 ResourceLength. The caller is responsible for verifying that the actual range for which the
516 attributes were set is acceptable.
518 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
519 @param[in] Attributes The mask of attributes to set. If the attribute bit
520 MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
521 MEMORY_DISABLE is set, then the resource range is specified by
522 ResourceBase and ResourceLength. If
523 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
524 MEMORY_DISABLE are not set, then ResourceBase and
525 ResourceLength are ignored, and may be NULL.
526 @param[in][out] ResourceBase A pointer to the base address of the resource range to be modified
527 by the attributes specified by Attributes.
528 @param[in][out] ResourceLength A pointer to the length of the resource range to be modified by the
529 attributes specified by Attributes.
531 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
532 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
533 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
538 RootBridgeIoSetAttributes (
539 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
540 IN UINT64 Attributes
,
541 IN OUT UINT64
*ResourceBase
,
542 IN OUT UINT64
*ResourceLength
546 Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
547 resource descriptors.
549 There are only two resource descriptor types from the ACPI Specification that may be used to
550 describe the current resources allocated to a PCI root bridge. These are the QWORD Address
551 Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The
552 QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
553 or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD
554 Address Space Descriptors followed by an End Tag.
556 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
557 @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the
558 current configuration of this PCI root bridge. The storage for the
559 ACPI 2.0 resource descriptors is allocated by this function. The
560 caller must treat the return buffer as read-only data, and the buffer
561 must not be freed by the caller.
563 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
564 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
565 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
570 RootBridgeIoConfiguration (
571 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
576 // Sub Function Prototypes
579 Internal help function for read and write PCI configuration space.
581 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
582 @param[in] Write Switch value for Read or Write.
583 @param[in] Width Signifies the width of the memory operations.
584 @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
585 @param[in] Count The number of PCI configuration operations to perform. Bytes
586 moved is Width size * Count, starting at Address.
587 @param[out] UserBuffer For read operations, the destination buffer to store the results. For
588 write operations, the source buffer to write data from.
590 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
591 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
592 @retval EFI_INVALID_PARAMETER Buffer is NULL.
593 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
598 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
600 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
601 IN UINT64 UserAddress
,
603 IN OUT VOID
*UserBuffer
607 // Memory Controller Pci Root Bridge Io Module Variables
609 EFI_METRONOME_ARCH_PROTOCOL
*mMetronome
;
610 EFI_CPU_IO2_PROTOCOL
*mCpuIo
;
614 Construct the Pci Root Bridge Io protocol
616 @param Protocol Point to protocol instance
617 @param HostBridgeHandle Handle of host bridge
618 @param Attri Attribute of host bridge
619 @param ResAppeture ResourceAppeture for host bridge
621 @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
625 RootBridgeConstructor (
626 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*Protocol
,
627 IN EFI_HANDLE HostBridgeHandle
,
629 IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE
*ResAppeture
633 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
634 PCI_RESOURCE_TYPE Index
;
636 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol
);
639 // The host to pci bridge, the host memory and io addresses are
640 // direct mapped to pci addresses, so no need translate, set bases to 0.
642 PrivateData
->MemBase
= ResAppeture
->MemBase
;
643 PrivateData
->IoBase
= ResAppeture
->IoBase
;
646 // The host bridge only supports 32bit addressing for memory
647 // and standard IA32 16bit io
649 PrivateData
->MemLimit
= ResAppeture
->MemLimit
;
650 PrivateData
->IoLimit
= ResAppeture
->IoLimit
;
653 // Bus Appeture for this Root Bridge (Possible Range)
655 PrivateData
->BusBase
= ResAppeture
->BusBase
;
656 PrivateData
->BusLimit
= ResAppeture
->BusLimit
;
659 // Specific for this chipset
661 for (Index
= TypeIo
; Index
< TypeMax
; Index
++) {
662 PrivateData
->ResAllocNode
[Index
].Type
= Index
;
663 PrivateData
->ResAllocNode
[Index
].Base
= 0;
664 PrivateData
->ResAllocNode
[Index
].Length
= 0;
665 PrivateData
->ResAllocNode
[Index
].Status
= ResNone
;
669 EfiInitializeLock (&PrivateData
->PciLock
, TPL_HIGH_LEVEL
);
670 PrivateData
->PciAddress
= 0xCF8;
671 PrivateData
->PciData
= 0xCFC;
673 PrivateData
->RootBridgeAttrib
= Attri
;
675 PrivateData
->Attributes
= 0;
676 PrivateData
->Supports
= 0;
678 Protocol
->ParentHandle
= HostBridgeHandle
;
680 Protocol
->PollMem
= RootBridgeIoPollMem
;
681 Protocol
->PollIo
= RootBridgeIoPollIo
;
683 Protocol
->Mem
.Read
= RootBridgeIoMemRead
;
684 Protocol
->Mem
.Write
= RootBridgeIoMemWrite
;
686 Protocol
->Io
.Read
= RootBridgeIoIoRead
;
687 Protocol
->Io
.Write
= RootBridgeIoIoWrite
;
689 Protocol
->CopyMem
= RootBridgeIoCopyMem
;
691 Protocol
->Pci
.Read
= RootBridgeIoPciRead
;
692 Protocol
->Pci
.Write
= RootBridgeIoPciWrite
;
694 Protocol
->Map
= RootBridgeIoMap
;
695 Protocol
->Unmap
= RootBridgeIoUnmap
;
697 Protocol
->AllocateBuffer
= RootBridgeIoAllocateBuffer
;
698 Protocol
->FreeBuffer
= RootBridgeIoFreeBuffer
;
700 Protocol
->Flush
= RootBridgeIoFlush
;
702 Protocol
->GetAttributes
= RootBridgeIoGetAttributes
;
703 Protocol
->SetAttributes
= RootBridgeIoSetAttributes
;
705 Protocol
->Configuration
= RootBridgeIoConfiguration
;
707 Protocol
->SegmentNumber
= 0;
709 Status
= gBS
->LocateProtocol (&gEfiCpuIo2ProtocolGuid
, NULL
, (VOID
**)&mCpuIo
);
710 ASSERT_EFI_ERROR (Status
);
712 Status
= gBS
->LocateProtocol (&gEfiMetronomeArchProtocolGuid
, NULL
, (VOID
**)&mMetronome
);
713 ASSERT_EFI_ERROR (Status
);
719 Polls an address in memory mapped I/O space until an exit condition is met, or
722 This function provides a standard way to poll a PCI memory location. A PCI memory read
723 operation is performed at the PCI memory address specified by Address for the width specified
724 by Width. The result of this PCI memory read operation is stored in Result. This PCI memory
725 read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &
726 Mask) is equal to Value.
728 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
729 @param[in] Width Signifies the width of the memory operations.
730 @param[in] Address The base address of the memory operations. The caller is
731 responsible for aligning Address if required.
732 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
733 are ignored. The bits in the bytes below Width which are zero in
734 Mask are ignored when polling the memory address.
735 @param[in] Value The comparison value used for the polling exit criteria.
736 @param[in] Delay The number of 100 ns units to poll. Note that timer available may
737 be of poorer granularity.
738 @param[out] Result Pointer to the last value read from the memory location.
740 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
741 @retval EFI_INVALID_PARAMETER Width is invalid.
742 @retval EFI_INVALID_PARAMETER Result is NULL.
743 @retval EFI_TIMEOUT Delay expired before a match occurred.
744 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
749 RootBridgeIoPollMem (
750 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
751 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
760 UINT64 NumberOfTicks
;
763 if (Result
== NULL
) {
764 return EFI_INVALID_PARAMETER
;
767 if (Width
< 0 || Width
> EfiPciWidthUint64
) {
768 return EFI_INVALID_PARAMETER
;
772 // No matter what, always do a single poll.
774 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
775 if (EFI_ERROR (Status
)) {
778 if ((*Result
& Mask
) == Value
) {
788 // Determine the proper # of metronome ticks to wait for polling the
789 // location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
790 // The "+1" to account for the possibility of the first tick being short
791 // because we started in the middle of a tick.
793 // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome
794 // protocol definition is updated.
796 NumberOfTicks
= DivU64x32Remainder (Delay
, (UINT32
) mMetronome
->TickPeriod
, &Remainder
);
797 if (Remainder
!= 0) {
802 while (NumberOfTicks
) {
804 mMetronome
->WaitForTick (mMetronome
, 1);
806 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
807 if (EFI_ERROR (Status
)) {
811 if ((*Result
& Mask
) == Value
) {
822 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
823 satisfied or after a defined duration.
825 This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is
826 performed at the PCI I/O address specified by Address for the width specified by Width.
827 The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is
828 repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal
831 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
832 @param[in] Width Signifies the width of the I/O operations.
833 @param[in] Address The base address of the I/O operations. The caller is responsible
834 for aligning Address if required.
835 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
836 are ignored. The bits in the bytes below Width which are zero in
837 Mask are ignored when polling the I/O address.
838 @param[in] Value The comparison value used for the polling exit criteria.
839 @param[in] Delay The number of 100 ns units to poll. Note that timer available may
840 be of poorer granularity.
841 @param[out] Result Pointer to the last value read from the memory location.
843 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
844 @retval EFI_INVALID_PARAMETER Width is invalid.
845 @retval EFI_INVALID_PARAMETER Result is NULL.
846 @retval EFI_TIMEOUT Delay expired before a match occurred.
847 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
853 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
854 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
863 UINT64 NumberOfTicks
;
867 // No matter what, always do a single poll.
870 if (Result
== NULL
) {
871 return EFI_INVALID_PARAMETER
;
874 if (Width
< 0 || Width
> EfiPciWidthUint64
) {
875 return EFI_INVALID_PARAMETER
;
878 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
879 if (EFI_ERROR (Status
)) {
882 if ((*Result
& Mask
) == Value
) {
892 // Determine the proper # of metronome ticks to wait for polling the
893 // location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
894 // The "+1" to account for the possibility of the first tick being short
895 // because we started in the middle of a tick.
897 NumberOfTicks
= DivU64x32Remainder (Delay
, (UINT32
)mMetronome
->TickPeriod
, &Remainder
);
898 if (Remainder
!= 0) {
903 while (NumberOfTicks
) {
905 mMetronome
->WaitForTick (mMetronome
, 1);
907 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
908 if (EFI_ERROR (Status
)) {
912 if ((*Result
& Mask
) == Value
) {
923 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
925 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
926 registers in the PCI root bridge memory space.
927 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
928 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
930 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
931 @param[in] Width Signifies the width of the memory operation.
932 @param[in] Address The base address of the memory operation. The caller is
933 responsible for aligning the Address if required.
934 @param[in] Count The number of memory operations to perform. Bytes moved is
935 Width size * Count, starting at Address.
936 @param[out] Buffer For read operations, the destination buffer to store the results. For
937 write operations, the source buffer to write data from.
939 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
940 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
941 @retval EFI_INVALID_PARAMETER Buffer is NULL.
942 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
947 RootBridgeIoMemRead (
948 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
949 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
955 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
956 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth
;
959 if (Buffer
== NULL
) {
960 return EFI_INVALID_PARAMETER
;
963 if (Width
< 0 || Width
>= EfiPciWidthMaximum
) {
964 return EFI_INVALID_PARAMETER
;
967 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This
);
970 // Check memory access limit
972 if (Address
< PrivateData
->MemBase
) {
973 return EFI_INVALID_PARAMETER
;
979 if (Width
>= EfiPciWidthFifoUint8
&& Width
<= EfiPciWidthFifoUint64
) {
983 Width
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
)(Width
& 0x03);
985 if (Address
+ (((UINTN
)1 << Width
) * Count
) - 1 > PrivateData
->MemLimit
) {
986 return EFI_INVALID_PARAMETER
;
989 return mCpuIo
->Mem
.Read (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) OldWidth
,
990 Address
, OldCount
, Buffer
);
994 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
996 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
997 registers in the PCI root bridge memory space.
998 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
999 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
1001 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1002 @param[in] Width Signifies the width of the memory operation.
1003 @param[in] Address The base address of the memory operation. The caller is
1004 responsible for aligning the Address if required.
1005 @param[in] Count The number of memory operations to perform. Bytes moved is
1006 Width size * Count, starting at Address.
1007 @param[out] Buffer For read operations, the destination buffer to store the results. For
1008 write operations, the source buffer to write data from.
1010 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1011 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1012 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1013 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1017 RootBridgeIoMemWrite (
1018 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1019 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1025 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
1026 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth
;
1029 if (Buffer
== NULL
) {
1030 return EFI_INVALID_PARAMETER
;
1033 if (Width
< 0 || Width
>= EfiPciWidthMaximum
) {
1034 return EFI_INVALID_PARAMETER
;
1037 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This
);
1040 // Check memory access limit
1042 if (Address
< PrivateData
->MemBase
) {
1043 return EFI_INVALID_PARAMETER
;
1048 if (Width
>= EfiPciWidthFifoUint8
&& Width
<= EfiPciWidthFifoUint64
) {
1052 Width
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
)(Width
& 0x03);
1054 if (Address
+ (((UINTN
)1 << Width
) * Count
) - 1 > PrivateData
->MemLimit
) {
1055 return EFI_INVALID_PARAMETER
;
1058 return mCpuIo
->Mem
.Write (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) OldWidth
,
1059 Address
, OldCount
, Buffer
);
1063 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
1065 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1066 @param[in] Width Signifies the width of the memory operations.
1067 @param[in] Address The base address of the I/O operation. The caller is responsible for
1068 aligning the Address if required.
1069 @param[in] Count The number of I/O operations to perform. Bytes moved is Width
1070 size * Count, starting at Address.
1071 @param[out] Buffer For read operations, the destination buffer to store the results. For
1072 write operations, the source buffer to write data from.
1074 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1075 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1076 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1077 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1082 RootBridgeIoIoRead (
1083 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1084 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1093 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
1094 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth
;
1097 if (Buffer
== NULL
) {
1098 return EFI_INVALID_PARAMETER
;
1101 if (Width
< 0 || Width
>= EfiPciWidthMaximum
) {
1102 return EFI_INVALID_PARAMETER
;
1105 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This
);
1107 //AlignMask = (1 << Width) - 1;
1108 AlignMask
= (1 << (Width
& 0x03)) - 1;
1111 // check Io access limit
1113 if (Address
< PrivateData
->IoBase
) {
1114 return EFI_INVALID_PARAMETER
;
1119 if (Width
>= EfiPciWidthFifoUint8
&& Width
<= EfiPciWidthFifoUint64
) {
1123 Width
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
)(Width
& 0x03);
1125 if (Address
+ (((UINTN
)1 << Width
) * Count
) - 1 >= PrivateData
->IoLimit
) {
1126 return EFI_INVALID_PARAMETER
;
1129 if (Address
& AlignMask
) {
1130 return EFI_INVALID_PARAMETER
;
1133 return mCpuIo
->Io
.Read (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) OldWidth
,
1134 Address
, OldCount
, Buffer
);
1139 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
1141 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1142 @param[in] Width Signifies the width of the memory operations.
1143 @param[in] Address The base address of the I/O operation. The caller is responsible for
1144 aligning the Address if required.
1145 @param[in] Count The number of I/O operations to perform. Bytes moved is Width
1146 size * Count, starting at Address.
1147 @param[out] Buffer For read operations, the destination buffer to store the results. For
1148 write operations, the source buffer to write data from.
1150 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1151 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1152 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1153 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1158 RootBridgeIoIoWrite (
1159 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1160 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1167 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
1168 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth
;
1171 if (Buffer
== NULL
) {
1172 return EFI_INVALID_PARAMETER
;
1175 if (Width
< 0 || Width
>= EfiPciWidthMaximum
) {
1176 return EFI_INVALID_PARAMETER
;
1179 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This
);
1181 //AlignMask = (1 << Width) - 1;
1182 AlignMask
= (1 << (Width
& 0x03)) - 1;
1185 // Check Io access limit
1187 if (Address
< PrivateData
->IoBase
) {
1188 return EFI_INVALID_PARAMETER
;
1193 if (Width
>= EfiPciWidthFifoUint8
&& Width
<= EfiPciWidthFifoUint64
) {
1197 Width
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
)(Width
& 0x03);
1199 if (Address
+ (((UINTN
)1 << Width
) * Count
) - 1 >= PrivateData
->IoLimit
) {
1200 return EFI_INVALID_PARAMETER
;
1203 if (Address
& AlignMask
) {
1204 return EFI_INVALID_PARAMETER
;
1207 return mCpuIo
->Io
.Write (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) OldWidth
,
1208 Address
, OldCount
, Buffer
);
1213 Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
1214 root bridge memory space.
1216 The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory
1217 space to another region of PCI root bridge memory space. This is especially useful for video scroll
1218 operation on a memory mapped video buffer.
1219 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
1220 any alignment and memory width restrictions that a PCI root bridge on a platform might require.
1222 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
1223 @param[in] Width Signifies the width of the memory operations.
1224 @param[in] DestAddress The destination address of the memory operation. The caller is
1225 responsible for aligning the DestAddress if required.
1226 @param[in] SrcAddress The source address of the memory operation. The caller is
1227 responsible for aligning the SrcAddress if required.
1228 @param[in] Count The number of memory operations to perform. Bytes moved is
1229 Width size * Count, starting at DestAddress and SrcAddress.
1231 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
1232 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1233 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1238 RootBridgeIoCopyMem (
1239 IN
struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1240 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1241 IN UINT64 DestAddress
,
1242 IN UINT64 SrcAddress
,
1252 if (Width
< 0 || Width
> EfiPciWidthUint64
) {
1253 return EFI_INVALID_PARAMETER
;
1256 if (DestAddress
== SrcAddress
) {
1260 Stride
= (UINTN
)(1 << Width
);
1263 if ((DestAddress
> SrcAddress
) && (DestAddress
< (SrcAddress
+ Count
* Stride
))) {
1265 SrcAddress
= SrcAddress
+ (Count
-1) * Stride
;
1266 DestAddress
= DestAddress
+ (Count
-1) * Stride
;
1269 for (Index
= 0;Index
< Count
;Index
++) {
1270 Status
= RootBridgeIoMemRead (
1277 if (EFI_ERROR (Status
)) {
1280 Status
= RootBridgeIoMemWrite (
1287 if (EFI_ERROR (Status
)) {
1291 SrcAddress
+= Stride
;
1292 DestAddress
+= Stride
;
1294 SrcAddress
-= Stride
;
1295 DestAddress
-= Stride
;
1302 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
1304 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
1305 registers for a PCI controller.
1306 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
1307 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
1310 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1311 @param[in] Width Signifies the width of the memory operations.
1312 @param[in] Address The address within the PCI configuration space for the PCI controller.
1313 @param[in] Count The number of PCI configuration operations to perform. Bytes
1314 moved is Width size * Count, starting at Address.
1315 @param[out] Buffer For read operations, the destination buffer to store the results. For
1316 write operations, the source buffer to write data from.
1318 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1319 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1320 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1321 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1326 RootBridgeIoPciRead (
1327 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1328 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1335 if (Buffer
== NULL
) {
1336 return EFI_INVALID_PARAMETER
;
1339 if (Width
< 0 || Width
>= EfiPciWidthMaximum
) {
1340 return EFI_INVALID_PARAMETER
;
1343 // Read Pci configuration space
1345 return RootBridgeIoPciRW (This
, FALSE
, Width
, Address
, Count
, Buffer
);
1349 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
1351 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
1352 registers for a PCI controller.
1353 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
1354 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
1357 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1358 @param[in] Width Signifies the width of the memory operations.
1359 @param[in] Address The address within the PCI configuration space for the PCI controller.
1360 @param[in] Count The number of PCI configuration operations to perform. Bytes
1361 moved is Width size * Count, starting at Address.
1362 @param[out] Buffer For read operations, the destination buffer to store the results. For
1363 write operations, the source buffer to write data from.
1365 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1366 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1367 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1368 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1373 RootBridgeIoPciWrite (
1374 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1375 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1382 if (Buffer
== NULL
) {
1383 return EFI_INVALID_PARAMETER
;
1386 if (Width
< 0 || Width
>= EfiPciWidthMaximum
) {
1387 return EFI_INVALID_PARAMETER
;
1390 // Write Pci configuration space
1392 return RootBridgeIoPciRW (This
, TRUE
, Width
, Address
, Count
, Buffer
);
1396 Provides the PCI controller-specific addresses required to access system memory from a
1399 The Map() function provides the PCI controller specific addresses needed to access system
1400 memory. This function is used to map system memory for PCI bus master DMA accesses.
1402 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1403 @param[in] Operation Indicates if the bus master is going to read or write to system memory.
1404 @param[in] HostAddress The system memory address to map to the PCI controller.
1405 @param[in][out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
1406 @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use
1407 to access the system memory's HostAddress.
1408 @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
1410 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
1411 @retval EFI_INVALID_PARAMETER Operation is invalid.
1412 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
1413 @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.
1414 @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.
1415 @retval EFI_INVALID_PARAMETER Mapping is NULL.
1416 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
1417 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
1418 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1424 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1425 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation
,
1426 IN VOID
*HostAddress
,
1427 IN OUT UINTN
*NumberOfBytes
,
1428 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
1433 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1436 if (HostAddress
== NULL
|| NumberOfBytes
== NULL
|| DeviceAddress
== NULL
|| Mapping
== NULL
) {
1437 return EFI_INVALID_PARAMETER
;
1441 // Initialize the return values to their defaults
1446 // Make sure that Operation is valid
1448 if (Operation
< 0 || Operation
>= EfiPciOperationMaximum
) {
1449 return EFI_INVALID_PARAMETER
;
1453 // Most PCAT like chipsets can not handle performing DMA above 4GB.
1454 // If any part of the DMA transfer being mapped is above 4GB, then
1455 // map the DMA transfer to a buffer below 4GB.
1457 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
;
1458 if ((PhysicalAddress
+ *NumberOfBytes
) > 0x100000000ULL
) {
1461 // Common Buffer operations can not be remapped. If the common buffer
1462 // if above 4GB, then it is not possible to generate a mapping, so return
1465 if (Operation
== EfiPciOperationBusMasterCommonBuffer
|| Operation
== EfiPciOperationBusMasterCommonBuffer64
) {
1466 return EFI_UNSUPPORTED
;
1470 // Allocate a MAP_INFO structure to remember the mapping when Unmap() is
1473 Status
= gBS
->AllocatePool (
1474 EfiBootServicesData
,
1478 if (EFI_ERROR (Status
)) {
1484 // Return a pointer to the MAP_INFO structure in Mapping
1489 // Initialize the MAP_INFO structure
1491 MapInfo
->Operation
= Operation
;
1492 MapInfo
->NumberOfBytes
= *NumberOfBytes
;
1493 MapInfo
->NumberOfPages
= EFI_SIZE_TO_PAGES(*NumberOfBytes
);
1494 MapInfo
->HostAddress
= PhysicalAddress
;
1495 MapInfo
->MappedHostAddress
= 0x00000000ffffffff;
1498 // Allocate a buffer below 4GB to map the transfer to.
1500 Status
= gBS
->AllocatePages (
1502 EfiBootServicesData
,
1503 MapInfo
->NumberOfPages
,
1504 &MapInfo
->MappedHostAddress
1506 if (EFI_ERROR (Status
)) {
1507 gBS
->FreePool (MapInfo
);
1513 // If this is a read operation from the Bus Master's point of view,
1514 // then copy the contents of the real buffer into the mapped buffer
1515 // so the Bus Master can read the contents of the real buffer.
1517 if (Operation
== EfiPciOperationBusMasterRead
|| Operation
== EfiPciOperationBusMasterRead64
) {
1519 (VOID
*)(UINTN
)MapInfo
->MappedHostAddress
,
1520 (VOID
*)(UINTN
)MapInfo
->HostAddress
,
1521 MapInfo
->NumberOfBytes
1526 // The DeviceAddress is the address of the maped buffer below 4GB
1528 *DeviceAddress
= MapInfo
->MappedHostAddress
;
1531 // The transfer is below 4GB, so the DeviceAddress is simply the HostAddress
1533 *DeviceAddress
= PhysicalAddress
;
1540 Completes the Map() operation and releases any corresponding resources.
1542 The Unmap() function completes the Map() operation and releases any corresponding resources.
1543 If the operation was an EfiPciOperationBusMasterWrite or
1544 EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.
1545 Any resources used for the mapping are freed.
1547 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1548 @param[in] Mapping The mapping value returned from Map().
1550 @retval EFI_SUCCESS The range was unmapped.
1551 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
1552 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
1558 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1565 // See if the Map() operation associated with this Unmap() required a mapping buffer.
1566 // If a mapping buffer was not required, then this function simply returns EFI_SUCCESS.
1568 if (Mapping
!= NULL
) {
1570 // Get the MAP_INFO structure from Mapping
1572 MapInfo
= (MAP_INFO
*)Mapping
;
1575 // If this is a write operation from the Bus Master's point of view,
1576 // then copy the contents of the mapped buffer into the real buffer
1577 // so the processor can read the contents of the real buffer.
1579 if (MapInfo
->Operation
== EfiPciOperationBusMasterWrite
|| MapInfo
->Operation
== EfiPciOperationBusMasterWrite64
) {
1581 (VOID
*)(UINTN
)MapInfo
->HostAddress
,
1582 (VOID
*)(UINTN
)MapInfo
->MappedHostAddress
,
1583 MapInfo
->NumberOfBytes
1588 // Free the mapped buffer and the MAP_INFO structure.
1590 gBS
->FreePages (MapInfo
->MappedHostAddress
, MapInfo
->NumberOfPages
);
1591 gBS
->FreePool (Mapping
);
1597 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
1598 EfiPciOperationBusMasterCommonBuffer64 mapping.
1600 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1601 @param Type This parameter is not used and must be ignored.
1602 @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
1603 @param Pages The number of pages to allocate.
1604 @param HostAddress A pointer to store the base system memory address of the allocated range.
1605 @param Attributes The requested bit mask of attributes for the allocated range. Only
1606 the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
1607 and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
1609 @retval EFI_SUCCESS The requested memory pages were allocated.
1610 @retval EFI_INVALID_PARAMETER MemoryType is invalid.
1611 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
1612 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
1613 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
1614 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
1619 RootBridgeIoAllocateBuffer (
1620 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1621 IN EFI_ALLOCATE_TYPE Type
,
1622 IN EFI_MEMORY_TYPE MemoryType
,
1624 OUT VOID
**HostAddress
,
1625 IN UINT64 Attributes
1629 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1632 // Validate Attributes
1634 if (Attributes
& EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER
) {
1635 return EFI_UNSUPPORTED
;
1639 // Check for invalid inputs
1641 if (HostAddress
== NULL
) {
1642 return EFI_INVALID_PARAMETER
;
1646 // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
1648 if (MemoryType
!= EfiBootServicesData
&& MemoryType
!= EfiRuntimeServicesData
) {
1649 return EFI_INVALID_PARAMETER
;
1653 // Limit allocations to memory below 4GB
1655 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
)(0xffffffff);
1657 Status
= gBS
->AllocatePages (AllocateMaxAddress
, MemoryType
, Pages
, &PhysicalAddress
);
1658 if (EFI_ERROR (Status
)) {
1662 *HostAddress
= (VOID
*)(UINTN
)PhysicalAddress
;
1668 Frees memory that was allocated with AllocateBuffer().
1670 The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
1672 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1673 @param Pages The number of pages to free.
1674 @param HostAddress The base system memory address of the allocated range.
1676 @retval EFI_SUCCESS The requested memory pages were freed.
1677 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
1678 was not allocated with AllocateBuffer().
1683 RootBridgeIoFreeBuffer (
1684 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1686 OUT VOID
*HostAddress
1689 return gBS
->FreePages ((EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
, Pages
);
1693 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
1695 The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system
1696 memory. Posted write transactions are generated by PCI bus masters when they perform write
1697 transactions to target addresses in system memory.
1698 This function does not flush posted write transactions from any PCI bridges. A PCI controller
1699 specific action must be taken to guarantee that the posted write transactions have been flushed from
1700 the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with
1701 a PCI read transaction from the PCI controller prior to calling Flush().
1703 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1705 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
1706 bridge to system memory.
1707 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
1708 host bridge due to a hardware error.
1714 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
1718 // not supported yet
1724 Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
1725 attributes that a PCI root bridge is currently using.
1727 The GetAttributes() function returns the mask of attributes that this PCI root bridge supports
1728 and the mask of attributes that the PCI root bridge is currently using.
1730 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1731 @param Supported A pointer to the mask of attributes that this PCI root bridge
1732 supports setting with SetAttributes().
1733 @param Attributes A pointer to the mask of attributes that this PCI root bridge is
1736 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root
1737 bridge supports is returned in Supports. If Attributes is
1738 not NULL, then the attributes that the PCI root bridge is currently
1739 using is returned in Attributes.
1740 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1745 RootBridgeIoGetAttributes (
1746 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1747 OUT UINT64
*Supported
,
1748 OUT UINT64
*Attributes
1751 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
1753 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This
);
1755 if (Attributes
== NULL
&& Supported
== NULL
) {
1756 return EFI_INVALID_PARAMETER
;
1760 // Set the return value for Supported and Attributes
1763 *Supported
= PrivateData
->Supports
;
1767 *Attributes
= PrivateData
->Attributes
;
1774 Sets attributes for a resource range on a PCI root bridge.
1776 The SetAttributes() function sets the attributes specified in Attributes for the PCI root
1777 bridge on the resource range specified by ResourceBase and ResourceLength. Since the
1778 granularity of setting these attributes may vary from resource type to resource type, and from
1779 platform to platform, the actual resource range and the one passed in by the caller may differ. As a
1780 result, this function may set the attributes specified by Attributes on a larger resource range
1781 than the caller requested. The actual range is returned in ResourceBase and
1782 ResourceLength. The caller is responsible for verifying that the actual range for which the
1783 attributes were set is acceptable.
1785 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1786 @param[in] Attributes The mask of attributes to set. If the attribute bit
1787 MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
1788 MEMORY_DISABLE is set, then the resource range is specified by
1789 ResourceBase and ResourceLength. If
1790 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
1791 MEMORY_DISABLE are not set, then ResourceBase and
1792 ResourceLength are ignored, and may be NULL.
1793 @param[in][out] ResourceBase A pointer to the base address of the resource range to be modified
1794 by the attributes specified by Attributes.
1795 @param[in][out] ResourceLength A pointer to the length of the resource range to be modified by the
1796 attributes specified by Attributes.
1798 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
1799 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
1800 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1805 RootBridgeIoSetAttributes (
1806 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1807 IN UINT64 Attributes
,
1808 IN OUT UINT64
*ResourceBase
,
1809 IN OUT UINT64
*ResourceLength
1812 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
1814 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This
);
1817 if ((Attributes
& (~(PrivateData
->Supports
))) != 0) {
1818 return EFI_UNSUPPORTED
;
1823 // This is a generic driver for a PC-AT class system. It does not have any
1824 // chipset specific knowlegde, so none of the attributes can be set or
1825 // cleared. Any attempt to set attribute that are already set will succeed,
1826 // and any attempt to set an attribute that is not supported will fail.
1828 if (Attributes
& (~PrivateData
->Attributes
)) {
1829 return EFI_UNSUPPORTED
;
1836 Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
1837 resource descriptors.
1839 There are only two resource descriptor types from the ACPI Specification that may be used to
1840 describe the current resources allocated to a PCI root bridge. These are the QWORD Address
1841 Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The
1842 QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
1843 or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD
1844 Address Space Descriptors followed by an End Tag.
1846 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1847 @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the
1848 current configuration of this PCI root bridge. The storage for the
1849 ACPI 2.0 resource descriptors is allocated by this function. The
1850 caller must treat the return buffer as read-only data, and the buffer
1851 must not be freed by the caller.
1853 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
1854 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
1855 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1860 RootBridgeIoConfiguration (
1861 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1862 OUT VOID
**Resources
1865 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
1868 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This
);
1870 for (Index
= 0; Index
< TypeMax
; Index
++) {
1871 if (PrivateData
->ResAllocNode
[Index
].Status
== ResAllocated
) {
1872 Configuration
.SpaceDesp
[Index
].AddrRangeMin
= PrivateData
->ResAllocNode
[Index
].Base
;
1873 Configuration
.SpaceDesp
[Index
].AddrRangeMax
= PrivateData
->ResAllocNode
[Index
].Base
+ PrivateData
->ResAllocNode
[Index
].Length
- 1;
1874 Configuration
.SpaceDesp
[Index
].AddrLen
= PrivateData
->ResAllocNode
[Index
].Length
;
1878 *Resources
= &Configuration
;
1883 // Internal function
1886 Internal help function for read and write PCI configuration space.
1888 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1889 @param[in] Write Switch value for Read or Write.
1890 @param[in] Width Signifies the width of the memory operations.
1891 @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
1892 @param[in] Count The number of PCI configuration operations to perform. Bytes
1893 moved is Width size * Count, starting at Address.
1894 @param[out] UserBuffer For read operations, the destination buffer to store the results. For
1895 write operations, the source buffer to write data from.
1897 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1898 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1899 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1900 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1905 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1907 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1908 IN UINT64 UserAddress
,
1910 IN OUT VOID
*UserBuffer
1913 PCI_CONFIG_ACCESS_CF8 Pci
;
1914 PCI_CONFIG_ACCESS_CF8 PciAligned
;
1918 UINTN PciDataStride
;
1919 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
1920 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress
;
1922 if (Width
< 0 || Width
>= EfiPciWidthMaximum
) {
1923 return EFI_INVALID_PARAMETER
;
1926 if ((Width
& 0x03) >= EfiPciWidthUint64
) {
1927 return EFI_INVALID_PARAMETER
;
1930 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This
);
1932 InStride
= 1 << (Width
& 0x03);
1933 OutStride
= InStride
;
1934 if (Width
>= EfiCpuIoWidthFifoUint8
&& Width
<= EfiCpuIoWidthFifoUint64
) {
1938 if (Width
>= EfiCpuIoWidthFillUint8
&& Width
<= EfiCpuIoWidthFillUint64
) {
1942 CopyMem (&PciAddress
, &UserAddress
, sizeof(UINT64
));
1944 if (PciAddress
.ExtendedRegister
> 0xFF) {
1945 return EFI_UNSUPPORTED
;
1948 if (PciAddress
.ExtendedRegister
!= 0) {
1949 Pci
.Bits
.Reg
= PciAddress
.ExtendedRegister
& 0xFF;
1951 Pci
.Bits
.Reg
= PciAddress
.Register
;
1954 Pci
.Bits
.Func
= PciAddress
.Function
;
1955 Pci
.Bits
.Dev
= PciAddress
.Device
;
1956 Pci
.Bits
.Bus
= PciAddress
.Bus
;
1957 Pci
.Bits
.Reserved
= 0;
1958 Pci
.Bits
.Enable
= 1;
1961 // PCI Config access are all 32-bit alligned, but by accessing the
1962 // CONFIG_DATA_REGISTER (0xcfc) with different widths more cycle types
1963 // are possible on PCI.
1965 // To read a byte of PCI config space you load 0xcf8 and
1966 // read 0xcfc, 0xcfd, 0xcfe, 0xcff
1968 PciDataStride
= Pci
.Bits
.Reg
& 0x03;
1971 CopyMem (&PciAligned
, &Pci
, sizeof (PciAligned
));
1972 PciAligned
.Bits
.Reg
&= 0xfc;
1973 PciData
= (UINTN
)PrivateData
->PciData
+ PciDataStride
;
1974 EfiAcquireLock(&PrivateData
->PciLock
);
1975 This
->Io
.Write (This
, EfiPciWidthUint32
, PrivateData
->PciAddress
, 1, &PciAligned
);
1977 This
->Io
.Write (This
, Width
, PciData
, 1, UserBuffer
);
1979 This
->Io
.Read (This
, Width
, PciData
, 1, UserBuffer
);
1981 EfiReleaseLock(&PrivateData
->PciLock
);
1982 UserBuffer
= ((UINT8
*)UserBuffer
) + OutStride
;
1983 PciDataStride
= (PciDataStride
+ InStride
) % 4;
1984 Pci
.Bits
.Reg
+= InStride
;