PerformancePkg/Library/TscTimerLib/TscTimerLib.c

   1 /** @file
   2   A Timer Library implementation which uses the Time Stamp Counter in the processor.
   3
   4   For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]);
   5     for Intel Core Solo and Intel Core Duo processors (family [06H], model [0EH]);
   6     for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors (family [06H], model [0FH]);
   7     for Intel Core 2 and Intel Xeon processors (family [06H], display_model [17H]);
   8     for Intel Atom processors (family [06H], display_model [1CH]):
   9   the time-stamp counter increments at a constant rate.
  10   That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by
  11   the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may
  12   differ from the maximum qualified frequency of the processor.
  13
  14   The specific processor configuration determines the behavior. Constant TSC behavior ensures that the
  15   duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if
  16   the processor core changes frequency.  This is the architectural behavior moving forward.
  17
  18   A Processor\92s support for invariant TSC is indicated by CPUID.0x80000007.EDX[8].
  19
  20   Copyright (c) 2009-2010, Intel Corporation. All rights reserved.<BR>
  21   This program and the accompanying materials
  22   are licensed and made available under the terms and conditions of the BSD License
  23   which accompanies this distribution.  The full text of the license may be found at
  24   http://opensource.org/licenses/bsd-license.php
  25
  26   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  27   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  28
  29 **/
  30
  31 #include <Base.h>
  32 #include <Ich/GenericIch.h>
  33
  34 #include <Library/TimerLib.h>
  35 #include <Library/BaseLib.h>
  36 #include <Library/IoLib.h>
  37 #include <Library/PciLib.h>
  38 #include <Library/PcdLib.h>
  39
  40 STATIC UINT64   mTscFrequency;
  41
  42 #ifndef R_ICH_ACPI_PM1_TMR
  43 #define R_ICH_ACPI_PM1_TMR  R_ACPI_PM1_TMR
  44 #endif
  45
  46 /** The constructor function determines the actual TSC frequency.
  47
  48   The TSC counting frequency is determined by comparing how far it counts
  49   during a 1ms period as determined by the ACPI timer.  The ACPI timer is
  50   used because it counts at a known frequency.
  51   If ACPI I/O space not enabled, this function will enable it.  Then the
  52   TSC is sampled, followed by waiting for 3579 clocks of the ACPI timer, or 1ms.
  53   The TSC is then sampled again. The difference multiplied by 1000 is the TSC
  54   frequency.  There will be a small error because of the overhead of reading
  55   the ACPI timer.  An attempt is made to determine and compensate for this error.
  56   This function will always return RETURN_SUCCESS.
  57
  58   @retval RETURN_SUCCESS   The constructor always returns RETURN_SUCCESS.
  59
  60 **/
  61 RETURN_STATUS
  62 EFIAPI
  63 TscTimerLibConstructor (
  64   VOID
  65   )
  66 {
  67   UINT64      StartTSC;
  68   UINT64      EndTSC;
  69   UINT32      TimerAddr;
  70   UINT32      Ticks;
  71
  72   //
  73   // If ACPI I/O space is not enabled yet, program ACPI I/O base address and enable it.
  74   //
  75   if ((PciRead8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT)) & B_ICH_LPC_ACPI_CNT_ACPI_EN) == 0) {
  76     PciWrite16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE), PcdGet16 (PcdPerfPkgAcpiIoPortBaseAddress));
  77     PciOr8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT), B_ICH_LPC_ACPI_CNT_ACPI_EN);
  78   }
  79
  80   TimerAddr = PcdGet16 (PcdPerfPkgAcpiIoPortBaseAddress) + R_ACPI_PM1_TMR;  // Locate the ACPI Timer
  81   Ticks    = IoRead32( TimerAddr) + (3579);   // Set Ticks to 1ms in the future
  82   StartTSC = AsmReadTsc();                    // Get base value for the TSC
  83   //
  84   // Wait until the ACPI timer has counted 1ms.
  85   // Timer wrap-arounds are handled correctly by this function.
  86   // When the current ACPI timer value is greater than 'Ticks', the while loop will exit.
  87   //
  88   while (((Ticks - IoRead32( TimerAddr)) & BIT23) == 0) {
  89     CpuPause();
  90   }
  91   EndTSC = AsmReadTsc();    // TSC value 1ms later
  92
  93   mTscFrequency =   MultU64x32 (
  94                       (EndTSC - StartTSC),    // Number of TSC counts in 1ms
  95                       1000                    // Number of ms in a second
  96                     );
  97   //
  98   // mTscFrequency is now equal to the number of TSC counts per second
  99   //
 100   return RETURN_SUCCESS;
 101 }
 102
 103 /**  Stalls the CPU for at least the given number of ticks.
 104
 105   Stalls the CPU for at least the given number of ticks. It's invoked by
 106   MicroSecondDelay() and NanoSecondDelay().
 107
 108   @param[in]  Delay     A period of time to delay in ticks.
 109
 110 **/
 111 STATIC
 112 VOID
 113 InternalX86Delay (
 114   IN      UINT64                    Delay
 115   )
 116 {
 117   UINT64                             Ticks;
 118
 119   //
 120   // The target timer count is calculated here
 121   //
 122   Ticks = AsmReadTsc() + Delay;
 123
 124   //
 125   // Wait until time out
 126   // Timer wrap-arounds are NOT handled correctly by this function.
 127   // Thus, this function must be called within 10 years of reset since
 128   // Intel guarantees a minimum of 10 years before the TSC wraps.
 129   //
 130   while (AsmReadTsc() <= Ticks) CpuPause();
 131 }
 132
 133 /**  Stalls the CPU for at least the specified number of MicroSeconds.
 134
 135   @param[in]  MicroSeconds  The minimum number of microseconds to delay.
 136
 137   @return The value of MicroSeconds input.
 138
 139 **/
 140 UINTN
 141 EFIAPI
 142 MicroSecondDelay (
 143   IN      UINTN                     MicroSeconds
 144   )
 145 {
 146   InternalX86Delay (
 147     DivU64x32 (
 148       MultU64x64 (
 149         mTscFrequency,
 150         MicroSeconds
 151       ),
 152       1000000u
 153     )
 154   );
 155   return MicroSeconds;
 156 }
 157
 158 /**  Stalls the CPU for at least the specified number of NanoSeconds.
 159
 160   @param[in]  NanoSeconds The minimum number of nanoseconds to delay.
 161
 162   @return The value of NanoSeconds input.
 163
 164 **/
 165 UINTN
 166 EFIAPI
 167 NanoSecondDelay (
 168   IN      UINTN                     NanoSeconds
 169   )
 170 {
 171   InternalX86Delay (
 172     DivU64x32 (
 173       MultU64x32 (
 174         mTscFrequency,
 175         (UINT32)NanoSeconds
 176       ),
 177     1000000000u
 178     )
 179   );
 180   return NanoSeconds;
 181 }
 182
 183 /**  Retrieves the current value of the 64-bit free running Time-Stamp counter.
 184
 185   The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M,
 186   Pentium 4, Intel Xeon, Intel Core Solo and Intel Core Duo processors and
 187   later processors) is a 64-bit counter that is set to 0 following a RESET of
 188   the processor.  Following a RESET, the counter increments even when the
 189   processor is halted by the HLT instruction or the external STPCLK# pin. Note
 190   that the assertion of the external DPSLP# pin may cause the time-stamp
 191   counter to stop.
 192
 193   The properties of the counter can be retrieved by the
 194   GetPerformanceCounterProperties() function.
 195
 196   @return The current value of the free running performance counter.
 197
 198 **/
 199 UINT64
 200 EFIAPI
 201 GetPerformanceCounter (
 202   VOID
 203   )
 204 {
 205   return AsmReadTsc();
 206 }
 207
 208 /**  Retrieves the 64-bit frequency in Hz and the range of performance counter
 209   values.
 210
 211   If StartValue is not NULL, then the value that the performance counter starts
 212   with, 0x0, is returned in StartValue. If EndValue is not NULL, then the value
 213   that the performance counter end with, 0xFFFFFFFFFFFFFFFF, is returned in
 214   EndValue.
 215
 216   The 64-bit frequency of the performance counter, in Hz, is always returned.
 217   To determine average processor clock frequency, Intel recommends the use of
 218   EMON logic to count processor core clocks over the period of time for which
 219   the average is required.
 220
 221
 222   @param[out]   StartValue  Pointer to where the performance counter's starting value is saved, or NULL.
 223   @param[out]   EndValue    Pointer to where the performance counter's ending value is saved, or NULL.
 224
 225   @return The frequency in Hz.
 226
 227 **/
 228 UINT64
 229 EFIAPI
 230 GetPerformanceCounterProperties (
 231   OUT      UINT64                    *StartValue,  OPTIONAL
 232   OUT      UINT64                    *EndValue     OPTIONAL
 233   )
 234 {
 235   if (StartValue != NULL) {
 236     *StartValue = 0;
 237   }
 238   if (EndValue != NULL) {
 239     *EndValue = 0xFFFFFFFFFFFFFFFFull;
 240   }
 241
 242   return mTscFrequency;
 243 }