PerformancePkg/Library/TscTimerLib/TscTimerLib.c

   1 /** @file
   2   A Timer Library implementation which uses the Time Stamp Counter in the processor.
   3
   4   For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]);
   5     for Intel Core Solo and Intel Core Duo processors (family [06H], model [0EH]);
   6     for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors (family [06H], model [0FH]);
   7     for Intel Core 2 and Intel Xeon processors (family [06H], display_model [17H]);
   8     for Intel Atom processors (family [06H], display_model [1CH]):
   9   the time-stamp counter increments at a constant rate.
  10   That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by
  11   the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may
  12   differ from the maximum qualified frequency of the processor.
  13
  14   The specific processor configuration determines the behavior. Constant TSC behavior ensures that the
  15   duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if
  16   the processor core changes frequency.  This is the architectural behavior moving forward.
  17
  18   A Processor's support for invariant TSC is indicated by CPUID.0x80000007.EDX[8].
  19
  20   Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
  21   This program and the accompanying materials
  22   are licensed and made available under the terms and conditions of the BSD License
  23   which accompanies this distribution.  The full text of the license may be found at
  24   http://opensource.org/licenses/bsd-license.php
  25
  26   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  27   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  28
  29 **/
  30
  31 #include <Base.h>
  32 #include <Ich/GenericIch.h>
  33
  34 #include <Library/TimerLib.h>
  35 #include <Library/BaseLib.h>
  36 #include <Library/IoLib.h>
  37 #include <Library/PciLib.h>
  38 #include <Library/PcdLib.h>
  39
  40 STATIC UINT64   mTscFrequency;
  41
  42 /** The constructor function determines the actual TSC frequency.
  43
  44   The TSC counting frequency is determined by comparing how far it counts
  45   during a 1ms period as determined by the ACPI timer.  The ACPI timer is
  46   used because it counts at a known frequency.
  47   If ACPI I/O space not enabled, this function will enable it.  Then the
  48   TSC is sampled, followed by waiting for 3579 clocks of the ACPI timer, or 1ms.
  49   The TSC is then sampled again. The difference multiplied by 1000 is the TSC
  50   frequency.  There will be a small error because of the overhead of reading
  51   the ACPI timer.  An attempt is made to determine and compensate for this error.
  52   This function will always return RETURN_SUCCESS.
  53
  54   @retval RETURN_SUCCESS   The constructor always returns RETURN_SUCCESS.
  55
  56 **/
  57 RETURN_STATUS
  58 EFIAPI
  59 TscTimerLibConstructor (
  60   VOID
  61   )
  62 {
  63   UINT64      StartTSC;
  64   UINT64      EndTSC;
  65   UINT32      TimerAddr;
  66   UINT32      Ticks;
  67
  68   //
  69   // If ACPI I/O space is not enabled yet, program ACPI I/O base address and enable it.
  70   //
  71   if ((PciRead8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT)) & B_ICH_LPC_ACPI_CNT_ACPI_EN) == 0) {
  72     PciWrite16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE), PcdGet16 (PcdPerfPkgAcpiIoPortBaseAddress));
  73     PciOr8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT), B_ICH_LPC_ACPI_CNT_ACPI_EN);
  74   }
  75
  76   TimerAddr = PcdGet16 (PcdPerfPkgAcpiIoPortBaseAddress) + R_ACPI_PM1_TMR;  // Locate the ACPI Timer
  77   Ticks    = IoRead32( TimerAddr) + (3579);   // Set Ticks to 1ms in the future
  78   StartTSC = AsmReadTsc();                    // Get base value for the TSC
  79   //
  80   // Wait until the ACPI timer has counted 1ms.
  81   // Timer wrap-arounds are handled correctly by this function.
  82   // When the current ACPI timer value is greater than 'Ticks', the while loop will exit.
  83   //
  84   while (((Ticks - IoRead32( TimerAddr)) & BIT23) == 0) {
  85     CpuPause();
  86   }
  87   EndTSC = AsmReadTsc();    // TSC value 1ms later
  88
  89   mTscFrequency =   MultU64x32 (
  90                       (EndTSC - StartTSC),    // Number of TSC counts in 1ms
  91                       1000                    // Number of ms in a second
  92                     );
  93   //
  94   // mTscFrequency is now equal to the number of TSC counts per second
  95   //
  96   return RETURN_SUCCESS;
  97 }
  98
  99 /**  Stalls the CPU for at least the given number of ticks.
 100
 101   Stalls the CPU for at least the given number of ticks. It's invoked by
 102   MicroSecondDelay() and NanoSecondDelay().
 103
 104   @param[in]  Delay     A period of time to delay in ticks.
 105
 106 **/
 107 VOID
 108 InternalX86Delay (
 109   IN      UINT64                    Delay
 110   )
 111 {
 112   UINT64                             Ticks;
 113
 114   //
 115   // The target timer count is calculated here
 116   //
 117   Ticks = AsmReadTsc() + Delay;
 118
 119   //
 120   // Wait until time out
 121   // Timer wrap-arounds are NOT handled correctly by this function.
 122   // Thus, this function must be called within 10 years of reset since
 123   // Intel guarantees a minimum of 10 years before the TSC wraps.
 124   //
 125   while (AsmReadTsc() <= Ticks) CpuPause();
 126 }
 127
 128 /**  Stalls the CPU for at least the specified number of MicroSeconds.
 129
 130   @param[in]  MicroSeconds  The minimum number of microseconds to delay.
 131
 132   @return The value of MicroSeconds input.
 133
 134 **/
 135 UINTN
 136 EFIAPI
 137 MicroSecondDelay (
 138   IN      UINTN                     MicroSeconds
 139   )
 140 {
 141   InternalX86Delay (
 142     DivU64x32 (
 143       MultU64x64 (
 144         mTscFrequency,
 145         MicroSeconds
 146       ),
 147       1000000u
 148     )
 149   );
 150   return MicroSeconds;
 151 }
 152
 153 /**  Stalls the CPU for at least the specified number of NanoSeconds.
 154
 155   @param[in]  NanoSeconds The minimum number of nanoseconds to delay.
 156
 157   @return The value of NanoSeconds input.
 158
 159 **/
 160 UINTN
 161 EFIAPI
 162 NanoSecondDelay (
 163   IN      UINTN                     NanoSeconds
 164   )
 165 {
 166   InternalX86Delay (
 167     DivU64x32 (
 168       MultU64x32 (
 169         mTscFrequency,
 170         (UINT32)NanoSeconds
 171       ),
 172     1000000000u
 173     )
 174   );
 175   return NanoSeconds;
 176 }
 177
 178 /**  Retrieves the current value of the 64-bit free running Time-Stamp counter.
 179
 180   The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M,
 181   Pentium 4, Intel Xeon, Intel Core Solo and Intel Core Duo processors and
 182   later processors) is a 64-bit counter that is set to 0 following a RESET of
 183   the processor.  Following a RESET, the counter increments even when the
 184   processor is halted by the HLT instruction or the external STPCLK# pin. Note
 185   that the assertion of the external DPSLP# pin may cause the time-stamp
 186   counter to stop.
 187
 188   The properties of the counter can be retrieved by the
 189   GetPerformanceCounterProperties() function.
 190
 191   @return The current value of the free running performance counter.
 192
 193 **/
 194 UINT64
 195 EFIAPI
 196 GetPerformanceCounter (
 197   VOID
 198   )
 199 {
 200   return AsmReadTsc();
 201 }
 202
 203 /**  Retrieves the 64-bit frequency in Hz and the range of performance counter
 204   values.
 205
 206   If StartValue is not NULL, then the value that the performance counter starts
 207   with, 0x0, is returned in StartValue. If EndValue is not NULL, then the value
 208   that the performance counter end with, 0xFFFFFFFFFFFFFFFF, is returned in
 209   EndValue.
 210
 211   The 64-bit frequency of the performance counter, in Hz, is always returned.
 212   To determine average processor clock frequency, Intel recommends the use of
 213   EMON logic to count processor core clocks over the period of time for which
 214   the average is required.
 215
 216
 217   @param[out]   StartValue  Pointer to where the performance counter's starting value is saved, or NULL.
 218   @param[out]   EndValue    Pointer to where the performance counter's ending value is saved, or NULL.
 219
 220   @return The frequency in Hz.
 221
 222 **/
 223 UINT64
 224 EFIAPI
 225 GetPerformanceCounterProperties (
 226   OUT      UINT64                    *StartValue,  OPTIONAL
 227   OUT      UINT64                    *EndValue     OPTIONAL
 228   )
 229 {
 230   if (StartValue != NULL) {
 231     *StartValue = 0;
 232   }
 233   if (EndValue != NULL) {
 234     *EndValue = 0xFFFFFFFFFFFFFFFFull;
 235   }
 236
 237   return mTscFrequency;
 238 }